This is a DRAM tuning/overclocking stability report for various Allwinner A10/A13/A20 based devices.It can be automatically generated by the tools from https://github.com/ssvb/a10-meminfo. Here we primarily focus on finding optimal dram_tpr3 values, tuned individually for every sunxi device. Currently these values need to be hardcoded into the sources of the u-boot-sunxi bootloader. The dram_tpr3 parameter is just a hexadecimal number with the following bit fields:

bits [22:20] - MFWDLY of the command lane
bits [18:16] - MFBDLY of the command lane
bits [15:12] - SDPHASE of the byte lane 3
bits [11:8] - SDPHASE of the byte lane 2
bits [7:4] - SDPHASE of the byte lane 1
bits [3:0] - SDPHASE of the byte lane 0

The RK30XX manual can be checked for more details about the MFWDLY, MFBDLY and SDPHASE bit fields. The Rockchip 30XX family of SoCs is apparently using the same DRAM controller IP.

Results interpretation (some results are actually a mix of RED and YELLOW):

RED - the hardware locks up relatively quickly.
YELLOW - may run for a relatively long time, but still deadlocks or suffers from data corruption.
GREEN - no problems detected during roughly ~5 minutes of lima-memtester run.

A10-Lime, dram_clock=528MHz (reliability for different dram_tpr3 settings)

dram_clk = 528
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 16
dram_cas = 9
dram_zq = 0x7f
dram_odt_en = 0
dram_tpr0 = 0x42d899b7
dram_tpr1 = 0xa090
dram_tpr2 = 0x22a00
dram_tpr3 = 0x0
dram_emr1 = 0x4
dram_emr2 = 0x10
dram_emr3 = 0x0

MFxDLY \ SDPHASE	36	54	72	90	108	126	144
7	0x073333	0x072222	0x071111	0x070000	0x07EEEE	0x07DDDD	0x07CCCC
6	0x063333	0x062222	0x061111	0x060000	0x06EEEE	0x06DDDD	0x06CCCC
5	0x053333	0x052222	0x051111	0x050000	0x05EEEE	0x05DDDD	0x05CCCC
4	0x043333	0x042222	0x041111	0x040000	0x04EEEE	0x04DDDD	0x04CCCC
3	0x033333	0x032222	0x031111	0x030000	0x03EEEE	0x03DDDD	0x03CCCC
2	0x023333	0x022222	0x021111	0x020000	0x02EEEE	0x02DDDD	0x02CCCC
1	0x013333	0x012222	0x011111	0x010000	0x01EEEE	0x01DDDD	0x01CCCC
0	0x003333	0x002222	0x001111	0x000000	0x00EEEE	0x00DDDD	0x00CCCC
8	0x083333	0x082222	0x081111	0x080000	0x08EEEE	0x08DDDD	0x08CCCC
10	0x103333	0x102222	0x101111	0x100000	0x10EEEE	0x10DDDD	0x10CCCC
18	0x183333	0x182222	0x181111	0x180000	0x18EEEE	0x18DDDD	0x18CCCC
20	0x203333	0x202222	0x201111	0x200000	0x20EEEE	0x20DDDD	0x20CCCC
28	0x283333	0x282222	0x281111	0x280000	0x28EEEE	0x28DDDD	0x28CCCC
30	0x303333	0x302222	0x301111	0x300000	0x30EEEE	0x30DDDD	0x30CCCC
38	0x383333	0x382222	0x381111	0x380000	0x38EEEE	0x38DDDD	0x38CCCC

Cubieboard1, dram_clock=528MHz (reliability for different dram_tpr3 settings)

dram_clk = 528
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 16
dram_bus_width = 32
dram_cas = 9
dram_zq = 0x7f
dram_odt_en = 0
dram_tpr0 = 0x42d899b7
dram_tpr1 = 0xa090
dram_tpr2 = 0x22a00
dram_tpr3 = 0x0
dram_emr1 = 0x4
dram_emr2 = 0x10
dram_emr3 = 0x0

MFxDLY \ SDPHASE	36	54	72	90	108	126	144
7	0x073333	0x072222	0x071111	0x070000	0x07EEEE	0x07DDDD	0x07CCCC
6	0x063333	0x062222	0x061111	0x060000	0x06EEEE	0x06DDDD	0x06CCCC
5	0x053333	0x052222	0x051111	0x050000	0x05EEEE	0x05DDDD	0x05CCCC
4	0x043333	0x042222	0x041111	0x040000	0x04EEEE	0x04DDDD	0x04CCCC
3	0x033333	0x032222	0x031111	0x030000	0x03EEEE	0x03DDDD	0x03CCCC
2	0x023333	0x022222	0x021111	0x020000	0x02EEEE	0x02DDDD	0x02CCCC
1	0x013333	0x012222	0x011111	0x010000	0x01EEEE	0x01DDDD	0x01CCCC
0	0x003333	0x002222	0x001111	0x000000	0x00EEEE	0x00DDDD	0x00CCCC
8	0x083333	0x082222	0x081111	0x080000	0x08EEEE	0x08DDDD	0x08CCCC
10	0x103333	0x102222	0x101111	0x100000	0x10EEEE	0x10DDDD	0x10CCCC
18	0x183333	0x182222	0x181111	0x180000	0x18EEEE	0x18DDDD	0x18CCCC
20	0x203333	0x202222	0x201111	0x200000	0x20EEEE	0x20DDDD	0x20CCCC
28	0x283333	0x282222	0x281111	0x280000	0x28EEEE	0x28DDDD	0x28CCCC
30	0x303333	0x302222	0x301111	0x300000	0x30EEEE	0x30DDDD	0x30CCCC
38	0x383333	0x382222	0x381111	0x380000	0x38EEEE	0x38DDDD	0x38CCCC

Cubieboard2, dram_clock=528MHz, dcdc3=1.25v (reliability for different dram_tpr3 settings)

MFxDLY \ SDPHASE	36	54	72	90	108	126	144
7	0x073333	0x072222	0x071111	0x070000	0x07EEEE	0x07DDDD	0x07CCCC
6	0x063333	0x062222	0x061111	0x060000	0x06EEEE	0x06DDDD	0x06CCCC
5	0x053333	0x052222	0x051111	0x050000	0x05EEEE	0x05DDDD	0x05CCCC
4	0x043333	0x042222	0x041111	0x040000	0x04EEEE	0x04DDDD	0x04CCCC
3	0x033333	0x032222	0x031111	0x030000	0x03EEEE	0x03DDDD	0x03CCCC
2	0x023333	0x022222	0x021111	0x020000	0x02EEEE	0x02DDDD	0x02CCCC
1	0x013333	0x012222	0x011111	0x010000	0x01EEEE	0x01DDDD	0x01CCCC
0	0x003333	0x002222	0x001111	0x000000	0x00EEEE	0x00DDDD	0x00CCCC
8	0x083333	0x082222	0x081111	0x080000	0x08EEEE	0x08DDDD	0x08CCCC
10	0x103333	0x102222	0x101111	0x100000	0x10EEEE	0x10DDDD	0x10CCCC
18	0x183333	0x182222	0x181111	0x180000	0x18EEEE	0x18DDDD	0x18CCCC
20	0x203333	0x202222	0x201111	0x200000	0x20EEEE	0x20DDDD	0x20CCCC
28	0x283333	0x282222	0x281111	0x280000	0x28EEEE	0x28DDDD	0x28CCCC
30	0x303333	0x302222	0x301111	0x300000	0x30EEEE	0x30DDDD	0x30CCCC
38	0x383333	0x382222	0x381111	0x380000	0x38EEEE	0x38DDDD	0x38CCCC

MFxDLY \ SDPHASE	36	54	72	90	108	126	144
7	0x073333	0x072222	0x071111	0x070000	0x07EEEE	0x07DDDD	0x07CCCC
6	0x063333	0x062222	0x061111	0x060000	0x06EEEE	0x06DDDD	0x06CCCC
5	0x053333	0x052222	0x051111	0x050000	0x05EEEE	0x05DDDD	0x05CCCC
4	0x043333	0x042222	0x041111	0x040000	0x04EEEE	0x04DDDD	0x04CCCC
3	0x033333	0x032222	0x031111	0x030000	0x03EEEE	0x03DDDD	0x03CCCC
2	0x023333	0x022222	0x021111	0x020000	0x02EEEE	0x02DDDD	0x02CCCC
1	0x013333	0x012222	0x011111	0x010000	0x01EEEE	0x01DDDD	0x01CCCC
0	0x003333	0x002222	0x001111	0x000000	0x00EEEE	0x00DDDD	0x00CCCC
8	0x083333	0x082222	0x081111	0x080000	0x08EEEE	0x08DDDD	0x08CCCC
10	0x103333	0x102222	0x101111	0x100000	0x10EEEE	0x10DDDD	0x10CCCC
18	0x183333	0x182222	0x181111	0x180000	0x18EEEE	0x18DDDD	0x18CCCC
20	0x203333	0x202222	0x201111	0x200000	0x20EEEE	0x20DDDD	0x20CCCC
28	0x283333	0x282222	0x281111	0x280000	0x28EEEE	0x28DDDD	0x28CCCC
30	0x303333	0x302222	0x301111	0x300000	0x30EEEE	0x30DDDD	0x30CCCC
38	0x383333	0x382222	0x381111	0x380000	0x38EEEE	0x38DDDD	0x38CCCC

Cubietruck, dram_clock=552MHz, dcdc3=1.35v - overvolted! (reliability for different dram_tpr3 settings)

dram_clk = 552
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 8
dram_bus_width = 32
dram_cas = 9
dram_zq = 0x7f
dram_odt_en = 0
dram_tpr0 = 0x3c9688b4
dram_tpr1 = 0xa090
dram_tpr2 = 0x210c0
dram_tpr3 = 0x72222
dram_emr1 = 0x4
dram_emr2 = 0x10
dram_emr3 = 0x0

MFxDLY \ SDPHASE	36	54	72	90	108	126	144
7	0x073333	0x072222	0x071111	0x070000	0x07EEEE	0x07DDDD	0x07CCCC
6	0x063333	0x062222	0x061111	0x060000	0x06EEEE	0x06DDDD	0x06CCCC
5	0x053333	0x052222	0x051111	0x050000	0x05EEEE	0x05DDDD	0x05CCCC
4	0x043333	0x042222	0x041111	0x040000	0x04EEEE	0x04DDDD	0x04CCCC
3	0x033333	0x032222	0x031111	0x030000	0x03EEEE	0x03DDDD	0x03CCCC
2	0x023333	0x022222	0x021111	0x020000	0x02EEEE	0x02DDDD	0x02CCCC
1	0x013333	0x012222	0x011111	0x010000	0x01EEEE	0x01DDDD	0x01CCCC
0	0x003333	0x002222	0x001111	0x000000	0x00EEEE	0x00DDDD	0x00CCCC
8	0x083333	0x082222	0x081111	0x080000	0x08EEEE	0x08DDDD	0x08CCCC
10	0x103333	0x102222	0x101111	0x100000	0x10EEEE	0x10DDDD	0x10CCCC
18	0x183333	0x182222	0x181111	0x180000	0x18EEEE	0x18DDDD	0x18CCCC
20	0x203333	0x202222	0x201111	0x200000	0x20EEEE	0x20DDDD	0x20CCCC
28	0x283333	0x282222	0x281111	0x280000	0x28EEEE	0x28DDDD	0x28CCCC
30	0x303333	0x302222	0x301111	0x300000	0x30EEEE	0x30DDDD	0x30CCCC
38	0x383333	0x382222	0x381111	0x380000	0x38EEEE	0x38DDDD	0x38CCCC

MFxDLY \ SDPHASE	36	54	72	90	108	126	144
7	0x073333	0x072222	0x071111	0x070000	0x07EEEE	0x07DDDD	0x07CCCC
6	0x063333	0x062222	0x061111	0x060000	0x06EEEE	0x06DDDD	0x06CCCC
5	0x053333	0x052222	0x051111	0x050000	0x05EEEE	0x05DDDD	0x05CCCC
4	0x043333	0x042222	0x041111	0x040000	0x04EEEE	0x04DDDD	0x04CCCC
3	0x033333	0x032222	0x031111	0x030000	0x03EEEE	0x03DDDD	0x03CCCC
2	0x023333	0x022222	0x021111	0x020000	0x02EEEE	0x02DDDD	0x02CCCC
1	0x013333	0x012222	0x011111	0x010000	0x01EEEE	0x01DDDD	0x01CCCC
0	0x003333	0x002222	0x001111	0x000000	0x00EEEE	0x00DDDD	0x00CCCC
8	0x083333	0x082222	0x081111	0x080000	0x08EEEE	0x08DDDD	0x08CCCC
10	0x103333	0x102222	0x101111	0x100000	0x10EEEE	0x10DDDD	0x10CCCC
18	0x183333	0x182222	0x181111	0x180000	0x18EEEE	0x18DDDD	0x18CCCC
20	0x203333	0x202222	0x201111	0x200000	0x20EEEE	0x20DDDD	0x20CCCC
28	0x283333	0x282222	0x281111	0x280000	0x28EEEE	0x28DDDD	0x28CCCC
30	0x303333	0x302222	0x301111	0x300000	0x30EEEE	0x30DDDD	0x30CCCC
38	0x383333	0x382222	0x381111	0x380000	0x38EEEE	0x38DDDD	0x38CCCC

Mele A2000, dram_clock=480MHz (reliability for different dram_tpr3 settings)

dram_clk = 480
dram_type = 3
dram_rank_num = 1
dram_chip_density = 2048
dram_io_width = 16
dram_bus_width = 32
dram_cas = 9
dram_zq = 0x7f
dram_odt_en = 0
dram_tpr0 = 0x42d899b7
dram_tpr1 = 0xa090
dram_tpr2 = 0x22a00
dram_tpr3 = 0x0
dram_emr1 = 0x4
dram_emr2 = 0x10
dram_emr3 = 0x0

MFxDLY \ SDPHASE	36	54	72	90	108	126	144
7	0x073333	0x072222	0x071111	0x070000	0x07EEEE	0x07DDDD	0x07CCCC
6	0x063333	0x062222	0x061111	0x060000	0x06EEEE	0x06DDDD	0x06CCCC
5	0x053333	0x052222	0x051111	0x050000	0x05EEEE	0x05DDDD	0x05CCCC
4	0x043333	0x042222	0x041111	0x040000	0x04EEEE	0x04DDDD	0x04CCCC
3	0x033333	0x032222	0x031111	0x030000	0x03EEEE	0x03DDDD	0x03CCCC
2	0x023333	0x022222	0x021111	0x020000	0x02EEEE	0x02DDDD	0x02CCCC
1	0x013333	0x012222	0x011111	0x010000	0x01EEEE	0x01DDDD	0x01CCCC
0	0x003333	0x002222	0x001111	0x000000	0x00EEEE	0x00DDDD	0x00CCCC
8	0x083333	0x082222	0x081111	0x080000	0x08EEEE	0x08DDDD	0x08CCCC
10	0x103333	0x102222	0x101111	0x100000	0x10EEEE	0x10DDDD	0x10CCCC
18	0x183333	0x182222	0x181111	0x180000	0x18EEEE	0x18DDDD	0x18CCCC
20	0x203333	0x202222	0x201111	0x200000	0x20EEEE	0x20DDDD	0x20CCCC
28	0x283333	0x282222	0x281111	0x280000	0x28EEEE	0x28DDDD	0x28CCCC
30	0x303333	0x302222	0x301111	0x300000	0x30EEEE	0x30DDDD	0x30CCCC
38	0x383333	0x382222	0x381111	0x380000	0x38EEEE	0x38DDDD	0x38CCCC

Notes:

The default settings (dram_tpr3=0x0) are exactly in the center cells of the tables. They tend to be not the very best.
Having some dram_tpr3 setting marked as GREEN does not mean that this particular setup is really stable. More like it is just a good candidate for more extensive testing. It is recommended to run lima-memtester for at least 8-10 hours before deciding that this configuration is really usable.
Even after identifying the highest dram clock speed, where lima-memtester can't detect any problems during a long run, it is still a good idea to reduce the dram clock speed by at least 24MHz from that point (in order to have some extra safety headroom).