VPU Handles the Global Video Processing, it includes management of the clocks gates, blocks reset lines and power domains.
What is missing :
The Amlogic Meson Display controller is composed of several components that are going to be documented below:
DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
| vd1 _______ _____________ _________________ | |
D |-------| |----| | | | | HDMI PLL |
D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
R |-------| |----| Processing | | | | |
| osd2 | | | |---| Enci ----------|----|-----VDAC------|
R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
A | osd1 | | | Blenders | | Encl ----------|----|---------------|
M |-------|______|----|____________| |________________| | |
___|__________________________________________________________|_______________|
VIU Handles the Pixel scanout and the basic Colorspace conversions We handle the following features :
What is missing :
VPP Handles all the Post Processing after the Scanout from the VIU We handle the following post processings :
We exclude OSD2, VS1, VS1 and Preblend output
use it only for interlace scanout
Intermediate FIFO with default Amlogic values
What is missing :
VENC Handle the pixels encoding to the output formats. We handle the following encodings :
What is missing :
VENC paths :
_____ _____ ____________________
vd1---| |-| | | VENC /---------|----VDAC
vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
osd1--| |-| | | \ | X--HDMI-TX
osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
| | |
| \--ENCL-----------|----LVDS
|____________________|
The ENCI is designed for PAl or NTSC encoding and can go through the VDAC directly for CVBS encoding or through the ENCI_DVI encoder for HDMI. The ENCP is designed for Progressive encoding but can also generate 1080i interlaced pixels, and was initialy desined to encode pixels for VDAC to output RGB ou YUV analog outputs. It’s output is only used through the ENCP_DVI encoder for HDMI. The ENCL LVDS encoder is not implemented.
The ENCI and ENCP encoders needs specially defined parameters for each supported mode and thus cannot be determined from standard video timings.
The ENCI end ENCP DVI encoders are more generic and can generate any timings from the pixel data generated by ENCI or ENCP, so can use the standard video timings are source for HW parameters.
CANVAS is a memory zone where physical memory frames information are stored for the VIU to scanout.
VCLK is the “Pixel Clock” frequency generator from a dedicated PLL. We handle the following encodings :
What is missing :
Clock generator scheme :
__________ _________ _____
| | | | | |--ENCI
| HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
|__________| |_________| \ | MUX |--ENCP
--VCLK2-| |--VDAC
|_____|--HDMI-TX
Final clocks can take input for either VCLK or VCLK2, but VCLK is the preferred path for HDMI clocking and VCLK2 is the preferred path for CVBS VDAC clocking.
VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
The PLL_DIV can achieve an additional fractional dividing like 1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.
HDMI Output is composed of :
___________________________________
| HDMI TOP |<= HPD
|___________________________________|
| | |
| Synopsys HDMI | HDMI PHY |=> TMDS
| Controller |________________|
|___________________________________|<=> DDC
The HDMI TOP block only supports HPD sensing. The Synopsys HDMI Controller interrupt is routed through the TOP Block interrupt. Communication to the TOP Block and the Synopsys HDMI Controller is done a pair of addr+read/write registers. The HDMI PHY is configured by registers in the HHI register block.
Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux selects either the ENCI encoder for the 576i or 480i formats or the ENCP encoder for all the other formats including interlaced HD formats. The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate DVI timings for the HDMI controller.
GXBB, GXL and GXM embeds the Synopsys DesignWare HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF audio source interfaces.
We handle the following features :
What is missing :