19:41 perimantus: Booth recoding is likely supported by dma microcontroller, so that's a win on branching, we carry all branchings in hash, so I showed a procedure as to how branches get filtered, so there's no control flow in the stream, you can swizzle the memory through cache controller configurations and dissipate heat. So the content gets continuously decompressed from hash. As dma is faster doing alus in a burst, the latency is hidden, so it does 512
19:41 perimantus: subtracts and appends a decompressed content of branch to stream and removes earlier streams that were already executed, so booth runahead recoding based dma branch decoder and appender. So altogether CPU pushes branches to the 512 bounded regions, and alus to 1024 bounded regions. So 256 is common value for branch , but 512 for Io write. Io writes just get handled on CPU, braches on dma, decompression is done on dma for both so are operan
19:41 perimantus: ds loaded to CPU with DMA. So CPU accepts dma operands, then if those are loaded executes alu compressed and batched procedures, branches are pushed as a result of alus to PC region, Io writes to mem write region.so dma polls mem writes off that stream address, from Io offsets, and appends branch underlying content like alus to it
19:42 perimantus: to it/To stream
20:21 perimantus: Everything should work out, cause bus of memory is sequenced at maximum throughput
20:22 perimantus: Interrupts are for only interrupting the calculus by external device , but SW interrupts are handled as io
20:23 perimantus: I have it all figured out for sometime now, let's see the coding process quickness a bit later, since my schedule is pretty full ATM.
20:26 perimantus: Things have to be in that order since Io writes, does affect the control flow, so Io writes have to be done per branch before if there was any, and we do not do those on CPU however can be, but it's better to perform Io on dma compute node