14:34 haasn: what's the point of shaderInt8 etc. if the subgroup size is fixed at 64? wouldn't you just store 64 8-bit integers in your 2048-bit SIMD registers, thus wasting 3/4s of the space?
14:34 haasn: it seems that taking advantage of 8-bit integers would require increasing the subgrooup size to 256
14:35 haasn: to make full use of the hardware wouldn't you need to pack four bytes into a 32-bit uint and make sure none of your operations overflow into the next integer
14:37 haasn: or can you pack a u8vec4 into a single SIMD register?
14:37 haasn: (but then, why doesn't GLSL provide a cast from uint to u8vec4 and back?)
14:37 haasn: it feels like I'm missing something obvious
14:42 haasn: really what I want is the 16-bit packed math instructions to be exposed in GLSL
15:05 haasn: ah, judging by GPUOpen presentations, u16vec2 *is* packed into a single 32-bit register
17:04 bnieuwenhuizen: haasn: yeah it is packed
17:04 bnieuwenhuizen: on newer GPUs you can also do single element instructions using low/high bits easily