03:54tonyk: no luck so far with the IB offset. I set GRBM_GFX_CNTL with the current ring data (me, pipe, queue), but all those values are 0x0, because it's the gfx_0.0.0 ring. But GRBM_GFX_CNTL is 0x0 by default anyway, so I was expecting that HQD registers would instantiate gfx_0.0.0 by default?
03:54tonyk: this is my current diff https://paste.debian.net/1278495/
03:54tonyk: the GPU is vangogh (steam deck)
03:55tonyk: mareko: agd5f: ^^
14:01agd5f: tonyk, they are all really just scratch registers. I guess maybe the FW doesn't populate them? I'll ask the FW team
14:26pepp: tonyk: you can achieve the same thing from userspace with umr (eg: "umr -b 0 1 0 -r "*.*.mmCP_HQD_IB_CONTROL"); I get 0s as well though
14:45tonyk: agd5f: what do you mean by "they are all really just scratch registers." that the FW uses SCRATCH_REGX for the IB offset?
14:46tonyk: pepp: yeah, I did something similar with umr --gui, but I thought that I would need to do from the kernel to properly set GRBM_GFX_CNTL and lock that mutex before reading mmCP_HQD_IB_CONTROL
15:03pepp: the gui doesn't support bank selection, but "-b x y z" is equivalent to the kernel's nv_grbm_select(x, y, z) (I think)
15:16tonyk: pepp: gotcha, didn't notice the -b flag
16:02agd5f: tonyk, pretty much all of the CP_* registers have no instrinsic meaning. they are just memory. The meaning of the registers is imparted by the behavior of the FW
16:03agd5f: i.e., there is no HW state behind the registers like say a display register
16:45tonyk: agd5f: ok, thank you
16:48Venemo: agd5f: do you know what this message might mean? [ 1603.651755] amdgpu 0000:63:00.0: [drm] *ERROR* [CRTC:72:crtc-0] flip_done timed out
16:48Venemo: I get this a few times everyday on my Rembrandt laptop
16:48Venemo: followed by a kernel crash
16:48tonyk: so there might be or not be a CP_ register with the IB offset