18:39 jiaozhou_: <Ristovski> I found out that when the screen resolution is downgraded, the ASIC_IS_DCE3(rdev) is 1 and it went to RADEON_HPD_2 branch, hpd = 1 and connected = 1 as well. When I plugged out the display cable, connected becomes 0, after I plugged the display cable back in again, it went to the same branch, hpd = 1 and connected = 1
18:40 jiaozhou_: Is this sufficient testing? or if I somehow misunderstood and missed something?
18:42 Ristovski: I believe that should rule out HPD sense as the culprit. agd5f any ideas ^ ?
21:02 jiaozhou_: may I know what radeon_process_aux_ch function is doing? does reading EDID happened inside this function? Will dp_aux_ch timeout cause issue to read EDID? Thanks
21:13 agd5f: jiaozhou_, it's for talking aux with the monitor
21:15 jiaozhou_: so this should not affect reading edid?
21:15 jiaozhou_: I think the key to my problem is that EDID is not detected somehow through display cable
21:16 jiaozhou_: can you suggest me some steps to debug the issue and possible fix the issue?
21:17 agd5f: it is. i2c over aux is used to read the EDID on DP
21:20 jiaozhou_: Okay, so what should I do next to fix my problem?
21:23 agd5f: jiaozhou_, maybe try retrying the transactions. ucReplyStatus == 1 means the transaction timed out
21:28 jiaozhou_: I think it is already retried in the code. I saw this log repeated 10 times before we set default resolution
21:28 jiaozhou_: [003] <...>-3904 1586.447471: [drm:radeon_process_aux_ch [radeon]] dp_aux_ch timeout
21:28 jiaozhou_: [003] <...>-3904 1586.447474: [drm:drm_dp_i2c_do_msg] (null): transaction timed out
21:35 agd5f: jiaozhou_, seems like the monitor is in a bad state until you unplug it for some reason
21:40 jiaozhou_: yes, and I tried with a different monitor and different cable, same issue happens
21:42 Remco: Different brand and model monitor?
21:44 jiaozhou_: yes different brand and model
21:49 jiaozhou_: The display also back to normal after sleep and wake up
21:56 agd5f: jiaozhou_, you could try and bring the link down before reading the EDID, but then you'll lose the display until you do a mode set
21:57 jiaozhou_: how to bring the link down?
22:01 agd5f: jiaozhou_, something like radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
22:12 Ristovski: agd5f: How is FGCG implemented? (mainly interested in why it's not there for GFX9)
22:15 agd5f: Ristovski, IIRC, it was handled internally in hw on pre-gfx10
22:16 agd5f: i.e., there wasn't a control bit for sw
22:17 Ristovski: agd5f: Ah. I was just going over all the "Off" entries in amdgpu_pm_info, I assume those without sw control will simply show up as Off since they are not even being read?
22:18 agd5f: Ristovski, right, if the hw does have the feature or there is no knob for sw, it shows up as off
22:18 agd5f: *doesn't
22:20 Ristovski: And I assume the status is not exported via registers in that case?
22:21 Ristovski: (inferring that from the name, as those regs all have _OVERRIDE in the name, i.e. they seem intentional)
22:23 agd5f: right
22:24 agd5f: I don't remember of FGCG is just always on or if it's tied to one of the other CGs on pre-gfx10
22:25 agd5f: but we didn't add a separate driver flag for it until gfx10 because that was the first gen where it was directly sw controllable
22:26 Ristovski: One more question: Why are some IPs mapped to different addresses? (that is when ip_discovery/die/0/XYZ/0/base_addr returns multiple)? Are they mapped with various "permission" levels or something?
22:26 Ristovski: to multiple different*
22:27 agd5f: they need more than a page of register space
22:27 agd5f: like sparse mappings
22:28 Ristovski: Aaah! That makes sense :)
22:29 agd5f: we try and keep them contiguous, but sometimes there is no space before you hit another IP's page, so you could end up with multiple ranges for an IP
22:30 agd5f: the SRBM maps the CPU accessible register space to back to the actual register blocks in the IPs
22:42 Ristovski: Interesting, thanks!
22:48 Ristovski: heh, DIO and DAZ IPs return 127.127.63 in their {major,minor,revision}
23:26 Frogging101: OpenCL on RDNA 2 when?
23:28 Frogging101: last time I tried to use rocm it failed, maybe it's time to try again