diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 40ab6d9..a4f7a54 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1467,17 +1467,37 @@ void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master)
 
 	/* Update the frame offsets for both CRTCs
 	 */
-	BEGIN_RING(6);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
+		BEGIN_RING(10);
 
-	RADEON_WAIT_UNTIL_3D_IDLE();
-	OUT_RING_REG(RADEON_CRTC_OFFSET,
-		     ((sarea->frame.y * dev_priv->front_pitch +
-		       sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
-		     + offset);
-	OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base
-		     + offset);
+		RADEON_WAIT_UNTIL_3D_IDLE();
+		OUT_RING_REG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS,
+			     ((sarea->frame.y * dev_priv->front_pitch +
+			       sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
+			     + offset + dev_priv->fb_location);
+		OUT_RING_REG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS,
+			     ((sarea->frame.y * dev_priv->front_pitch +
+			       sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
+			     + offset + dev_priv->fb_location);
+		OUT_RING_REG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, master_priv->sarea_priv->crtc2_base
+			     + offset + dev_priv->fb_location);
+		OUT_RING_REG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, master_priv->sarea_priv->crtc2_base
+			     + offset + dev_priv->fb_location);
 
-	ADVANCE_RING();
+		ADVANCE_RING();
+	} else {
+		BEGIN_RING(6);
+
+		RADEON_WAIT_UNTIL_3D_IDLE();
+		OUT_RING_REG(RADEON_CRTC_OFFSET,
+			     ((sarea->frame.y * dev_priv->front_pitch +
+			       sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
+			     + offset);
+		OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base
+			     + offset);
+
+		ADVANCE_RING();
+	}
 
 	/* Increment the frame counter.  The client-side 3D driver must
 	 * throttle the framerate by waiting for this value before