diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index e9e45ea..ad1ea7d 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -674,7 +674,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 
 	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
 	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
-	cgts_tcc_disable = RREG32(CGTS_TCC_DISABLE);
+	cgts_tcc_disable = 0xff000000;
 	gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
 	gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
 	cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
@@ -874,7 +874,9 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 	smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
 	WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 
-	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
+	WREG32(SMX_EVENT_CTL, 0x0000009b);
+	WREG32(SPI_CONFIG_CNTL_1, (CRC_SIMD_ID_WADDR_DISABLE |
+				   PC_LIMIT_SIZE(0x100)));
 
 	/* need to be explicitly zero-ed */
 	WREG32(VGT_OFFCHIP_LDS_BASE, 0);
@@ -897,6 +899,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 
 
 	WREG32(VGT_NUM_INSTANCES, 1);
+	WREG32(VGT_FIFO_DEPTHS, 0x0f40df40);
 
 	WREG32(CP_PERFMON_CNTL, 0);
 
@@ -905,7 +908,9 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 				  DONE_FIFO_HIWATER(0xe0) |
 				  ALU_UPDATE_FIFO_HIWATER(0x8)));
 
-	WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
+	WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS(96) |
+					NUM_VS_GPRS(96) |
+					NUM_CLAUSE_TEMP_GPRS(4)));
 	WREG32(SQ_CONFIG, (VC_ENABLE |
 			   EXPORT_SRC_C |
 			   GFX_PRIO(0) |
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 0f9a08b..c689b87 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -239,6 +239,7 @@
 #define			ES_AUTO						1
 #define			GS_AUTO						2
 #define			ES_AND_GS_AUTO					3
+#define	VGT_FIFO_DEPTHS					0x88D0
 #define	VGT_GS_VERTEX_REUSE				0x88D4
 
 #define CC_GC_SHADER_PIPE_CONFIG			0x8950
@@ -313,6 +314,7 @@
 #define		VTX_DONE_DELAY(x)				((x) << 0)
 #define		INTERP_ONE_PRIM_PER_ROW				(1 << 4)
 #define		CRC_SIMD_ID_WADDR_DISABLE			(1 << 8)
+#define		PC_LIMIT_SIZE(x)				((x) << 16)
 
 #define	CGTS_TCC_DISABLE				0x9148
 #define	CGTS_USER_TCC_DISABLE				0x914C