diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index e9e45ea..62f7320 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -833,6 +833,33 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 	rdev->config.cayman.tile_config |=
 		((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 
+
+	WREG32(CGTS_SYS_TCC_DISABLE, 0xff000000);
+	WREG32(CGTS_TCC_DISABLE, 0xff000000);
+	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0xff000000);
+	WREG32(CGTS_USER_TCC_DISABLE, 0xff000000);
+	WREG32(DMIF_ADDR_CONFIG, 0x00011003);
+	WREG32(GB_ADDR_CONFIG, 0x02011003);
+	WREG32(GB_BACKEND_MAP, 0x76541032);
+	WREG32(HDP_ADDR_CONFIG, 0x42010001);
+
+	WREG32(PA_CL_ENHANCE, 0x00000007);
+	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, 0x00ff0fff);
+	WREG32(PA_SC_LINE_STIPPLE_STATE, 0x00000000);
+
+	WREG32(SMX_EVENT_CTL, 0x0000009b);
+	WREG32(SPI_CONFIG_CNTL_1, 0x01000100);
+	WREG32(SQ_GPR_RESOURCE_MGMT_1, 0x40600060);
+
+	WREG32(TA_CNTL_AUX, 0x00000002);
+	WREG32(TCP_CHAN_STEER_LO, 0x54763210);
+	WREG32(VGT_CACHE_INVALIDATION, 0x00000082);
+	WREG32(VGT_FIFO_DEPTHS, 0x0f40df40);
+	WREG32(VGT_GS_VERTEX_REUSE, 0x00000010);
+	WREG32(VGT_NUM_INSTANCES, 0x00000000);
+
+	return;
+
 	WREG32(GB_BACKEND_MAP, gb_backend_map);
 	WREG32(GB_ADDR_CONFIG, gb_addr_config);
 	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 0f9a08b..1801c9b 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -239,6 +239,7 @@
 #define			ES_AUTO						1
 #define			GS_AUTO						2
 #define			ES_AND_GS_AUTO					3
+#define	VGT_FIFO_DEPTHS					0x88D0
 #define	VGT_GS_VERTEX_REUSE				0x88D4
 
 #define CC_GC_SHADER_PIPE_CONFIG			0x8950