From 2f5e5b1fb3b20f139a1cf205fed6359f60a94e6c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 10 Feb 2011 03:30:43 -0500 Subject: [PATCH] kms/r6xx+: enable linear aligned --- src/drmmode_display.c | 6 +--- src/evergreen_exa.c | 26 +++++++++++++++++++++ src/evergreen_textured_videofuncs.c | 12 ++++++++++ src/r600_exa.c | 42 ++++++++++++++++++++++++++++++++++- src/r600_textured_videofuncs.c | 12 ++++++++++ src/radeon.h | 1 + 6 files changed, 94 insertions(+), 5 deletions(-) diff --git a/src/drmmode_display.c b/src/drmmode_display.c index d5ad211..06cfd95 100644 --- a/src/drmmode_display.c +++ b/src/drmmode_display.c @@ -1130,10 +1130,8 @@ int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe, uint32_t tiling) /* further restrictions for scanout */ pitch_align = MAX(info->group_bytes / bpe, pitch_align); } else { - /* general surface requirements */ - pitch_align = info->group_bytes / bpe; - /* further restrictions for scanout */ - pitch_align = MAX(32, pitch_align); + /* linear aligned requirements */ + pitch_align = MAX(64, info->group_bytes / bpe); } } else { /* general surface requirements */ diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c index c4e1062..ddeead7 100644 --- a/src/evergreen_exa.c +++ b/src/evergreen_exa.c @@ -84,11 +84,17 @@ EVERGREENSetAccelState(ScrnInfoPtr pScrn, { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; + uint32_t pitch = 0; int ret; if (src0) { memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object)); accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8); + ret = radeon_bo_get_tiling(accel_state->src_obj[0].bo, + &accel_state->src_obj[0].tiling_flags, + &pitch); + if (ret) + RADEON_FALLBACK(("src0 radeon_bo_get_tiling failed\n")); } else { memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object)); accel_state->src_size[0] = 0; @@ -97,6 +103,11 @@ EVERGREENSetAccelState(ScrnInfoPtr pScrn, if (src1) { memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object)); accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8); + ret = radeon_bo_get_tiling(accel_state->src_obj[1].bo, + &accel_state->src_obj[1].tiling_flags, + &pitch); + if (ret) + RADEON_FALLBACK(("src1 radeon_bo_get_tiling failed\n")); } else { memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object)); accel_state->src_size[1] = 0; @@ -105,6 +116,11 @@ EVERGREENSetAccelState(ScrnInfoPtr pScrn, if (dst) { memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object)); accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8); + ret = radeon_bo_get_tiling(accel_state->dst_obj.bo, + &accel_state->dst_obj.tiling_flags, + &pitch); + if (ret) + RADEON_FALLBACK(("dst radeon_bo_get_tiling failed\n")); } else { memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object)); accel_state->dst_size = 0; @@ -252,6 +268,8 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) } cb_conf.source_format = EXPORT_4C_16BPC; cb_conf.blend_clamp = 1; + if (accel_state->dst_obj.tiling_flags == 0) + cb_conf.array_mode = 1; evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); /* Render setup */ @@ -450,6 +468,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn) tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); tex_samp.id = 0; @@ -479,6 +499,8 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn) } cb_conf.source_format = EXPORT_4C_16BPC; cb_conf.blend_clamp = 1; + if (accel_state->dst_obj.tiling_flags == 0) + cb_conf.array_mode = 1; evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); /* Render setup */ @@ -1073,6 +1095,8 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix, tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; + if (accel_state->src_obj[unit].tiling_flags == 0) + tex_res.array_mode = 1; evergreen_set_tex_resource (pScrn, &tex_res, accel_state->src_obj[unit].domain); tex_samp.id = unit; @@ -1378,6 +1402,8 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture, } cb_conf.source_format = EXPORT_4C_16BPC; cb_conf.blend_clamp = 1; + if (accel_state->dst_obj.tiling_flags == 0) + cb_conf.array_mode = 1; evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); blendcntl = EVERGREENGetBlendCntl(op, pMaskPicture, pDstPicture->format); diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c index e1e43a0..9d2d8a3 100644 --- a/src/evergreen_textured_videofuncs.c +++ b/src/evergreen_textured_videofuncs.c @@ -268,6 +268,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.last_level = 0; tex_res.perf_modulation = 0; tex_res.interlaced = 0; + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* Y sampler */ @@ -299,6 +301,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset; tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* U or V sampler */ @@ -320,6 +324,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset; tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* UV sampler */ @@ -357,6 +363,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.last_level = 0; tex_res.perf_modulation = 0; tex_res.interlaced = 0; + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* Y sampler */ @@ -392,6 +400,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.base = accel_state->src_obj[0].offset; tex_res.mip_base = accel_state->src_obj[0].offset; tex_res.size = accel_state->src_size[0]; + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.array_mode = 1; evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); /* UV sampler */ @@ -426,6 +436,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) cb_conf.source_format = EXPORT_4C_16BPC; cb_conf.blend_clamp = 1; + if (accel_state->dst_obj.tiling_flags == 0) + cb_conf.array_mode = 1; evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); /* Render setup */ diff --git a/src/r600_exa.c b/src/r600_exa.c index 5fc41ad..db2733d 100644 --- a/src/r600_exa.c +++ b/src/r600_exa.c @@ -72,10 +72,23 @@ R600SetAccelState(ScrnInfoPtr pScrn, { RADEONInfoPtr info = RADEONPTR(pScrn); struct radeon_accel_state *accel_state = info->accel_state; + uint32_t pitch = 0; +#if defined(XF86DRM_MODE) + int ret; +#endif if (src0) { memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object)); accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8); +#if defined(XF86DRM_MODE) + if (info->cs) { + ret = radeon_bo_get_tiling(accel_state->src_obj[0].bo, + &accel_state->src_obj[0].tiling_flags, + &pitch); + if (ret) + RADEON_FALLBACK(("src0 radeon_bo_get_tiling failed\n")); + } +#endif } else { memset(&accel_state->src_obj[0], 0, sizeof(struct r600_accel_object)); accel_state->src_size[0] = 0; @@ -84,6 +97,15 @@ R600SetAccelState(ScrnInfoPtr pScrn, if (src1) { memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object)); accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8); +#if defined(XF86DRM_MODE) + if (info->cs) { + ret = radeon_bo_get_tiling(accel_state->src_obj[1].bo, + &accel_state->src_obj[1].tiling_flags, + &pitch); + if (ret) + RADEON_FALLBACK(("src1 radeon_bo_get_tiling failed\n")); + } +#endif } else { memset(&accel_state->src_obj[1], 0, sizeof(struct r600_accel_object)); accel_state->src_size[1] = 0; @@ -92,6 +114,15 @@ R600SetAccelState(ScrnInfoPtr pScrn, if (dst) { memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object)); accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8); +#if defined(XF86DRM_MODE) + if (info->cs) { + ret = radeon_bo_get_tiling(accel_state->dst_obj.bo, + &accel_state->dst_obj.tiling_flags, + &pitch); + if (ret) + RADEON_FALLBACK(("dst radeon_bo_get_tiling failed\n")); + } +#endif } else { memset(&accel_state->dst_obj, 0, sizeof(struct r600_accel_object)); accel_state->dst_size = 0; @@ -126,7 +157,6 @@ R600SetAccelState(ScrnInfoPtr pScrn, accel_state->ps_size = 512; #if defined(XF86DRM_MODE) if (info->cs) { - int ret; accel_state->vs_mc_addr = vs_offset; accel_state->ps_mc_addr = ps_offset; @@ -253,6 +283,8 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; + if (accel_state->dst_obj.tiling_flags == 0) + cb_conf.array_mode = 1; r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); /* Render setup */ @@ -443,6 +475,8 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); tex_samp.id = 0; @@ -472,6 +506,8 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn) } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; + if (accel_state->dst_obj.tiling_flags == 0) + cb_conf.array_mode = 1; r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); /* Render setup */ @@ -1062,6 +1098,8 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix, tex_res.base_level = 0; tex_res.last_level = 0; tex_res.perf_modulation = 0; + if (accel_state->src_obj[unit].tiling_flags == 0) + tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[unit].domain); tex_samp.id = unit; @@ -1405,6 +1443,8 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture, } cb_conf.source_format = 1; cb_conf.blend_clamp = 1; + if (accel_state->dst_obj.tiling_flags == 0) + cb_conf.array_mode = 1; r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); BEGIN_BATCH(24); diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c index f71a61b..411c7c1 100644 --- a/src/r600_textured_videofuncs.c +++ b/src/r600_textured_videofuncs.c @@ -280,6 +280,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.last_level = 0; tex_res.perf_modulation = 0; tex_res.interlaced = 0; + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); /* Y sampler */ @@ -311,6 +313,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.base = accel_state->src_obj[0].offset + pPriv->planev_offset; tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planev_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); /* U or V sampler */ @@ -332,6 +336,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.base = accel_state->src_obj[0].offset + pPriv->planeu_offset; tex_res.mip_base = accel_state->src_obj[0].offset + pPriv->planeu_offset; tex_res.size = tex_res.pitch * (pPriv->h >> 1); + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); /* UV sampler */ @@ -370,6 +376,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.last_level = 0; tex_res.perf_modulation = 0; tex_res.interlaced = 0; + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); /* Y sampler */ @@ -406,6 +414,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) tex_res.base = accel_state->src_obj[0].offset; tex_res.mip_base = accel_state->src_obj[0].offset; tex_res.size = accel_state->src_size[0]; + if (accel_state->src_obj[0].tiling_flags == 0) + tex_res.tile_mode = 1; r600_set_tex_resource(pScrn, accel_state->ib, &tex_res, accel_state->src_obj[0].domain); /* UV sampler */ @@ -440,6 +450,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) cb_conf.source_format = 1; cb_conf.blend_clamp = 1; + if (accel_state->dst_obj.tiling_flags == 0) + cb_conf.array_mode = 1; r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain); /* Render setup */ diff --git a/src/radeon.h b/src/radeon.h index b72c4b0..0f0d2f4 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -684,6 +684,7 @@ struct r600_accel_object { int bpp; uint32_t domain; struct radeon_bo *bo; + uint32_t tiling_flags; }; struct radeon_vbo_object { -- 1.7.1.1