*** IR Dump Before Module Verifier ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %mul = mul nsw i32 %add.i132, %src_step
  %0 = sext i32 %mul to i64
  %mul6 = mul nsw i32 %add.i, %src2_step
  %1 = sext i32 %mul6 to i64
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %add27.lcssa = phi float [ %add27, %for.body ]
  %2 = add i32 %width, -1
  %3 = and i32 %2, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %3, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27.lcssa, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %mul32 = mul nsw i32 %add.i132, %src_step
  %mul34 = mul nsw i32 %add.i, %src2_step
  %4 = sext i32 %t.0.lcssa to i64
  %5 = sext i32 %mul34 to i64
  %6 = sext i32 %mul32 to i64
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %indvars.iv171 = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next172, %for.body ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %add.ptr.sum = add i64 %indvars.iv171, %0
  %add.ptr4 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr.sum
  %7 = load float addrspace(1)* %add.ptr4, align 4, !tbaa !4
  %8 = insertelement <8 x float> undef, float %7, i32 0
  %add.ptr4.sum = add i64 %add.ptr.sum, 1
  %arrayidx2.i.i.i112 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum
  %9 = load float addrspace(1)* %arrayidx2.i.i.i112, align 4, !tbaa !4
  %10 = insertelement <8 x float> %8, float %9, i32 1
  %add.ptr4.sum133 = add i64 %add.ptr.sum, 2
  %arrayidx6.i.i.i113 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum133
  %11 = load float addrspace(1)* %arrayidx6.i.i.i113, align 4, !tbaa !4
  %12 = insertelement <8 x float> %10, float %11, i32 2
  %add.ptr4.sum134 = add i64 %add.ptr.sum, 3
  %arrayidx10.i.i.i114 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum134
  %13 = load float addrspace(1)* %arrayidx10.i.i.i114, align 4, !tbaa !4
  %14 = insertelement <8 x float> %12, float %13, i32 3
  %add.ptr4.sum135 = add i64 %add.ptr.sum, 4
  %arrayidx.i.i.i115 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum135
  %15 = load float addrspace(1)* %arrayidx.i.i.i115, align 4, !tbaa !4
  %16 = insertelement <8 x float> undef, float %15, i32 0
  %add.ptr4.sum136 = add i64 %add.ptr.sum, 5
  %arrayidx2.i9.i.i116 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum136
  %17 = load float addrspace(1)* %arrayidx2.i9.i.i116, align 4, !tbaa !4
  %18 = insertelement <8 x float> %16, float %17, i32 1
  %add.ptr4.sum137 = add i64 %add.ptr.sum, 6
  %arrayidx6.i11.i.i117 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum137
  %19 = load float addrspace(1)* %arrayidx6.i11.i.i117, align 4, !tbaa !4
  %20 = insertelement <8 x float> %18, float %19, i32 2
  %add.ptr4.sum138 = add i64 %add.ptr.sum, 7
  %arrayidx10.i13.i.i118 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum138
  %21 = load float addrspace(1)* %arrayidx10.i13.i.i118, align 4, !tbaa !4
  %22 = insertelement <8 x float> %20, float %21, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %14, <8 x float> %22, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %add.ptr4.sum139 = add i64 %add.ptr.sum, 8
  %arrayidx.i.i121 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum139
  %23 = load float addrspace(1)* %arrayidx.i.i121, align 4, !tbaa !4
  %24 = insertelement <8 x float> undef, float %23, i32 0
  %add.ptr4.sum140 = add i64 %add.ptr.sum, 9
  %arrayidx2.i.i8.i122 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum140
  %25 = load float addrspace(1)* %arrayidx2.i.i8.i122, align 4, !tbaa !4
  %26 = insertelement <8 x float> %24, float %25, i32 1
  %add.ptr4.sum141 = add i64 %add.ptr.sum, 10
  %arrayidx6.i.i9.i123 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum141
  %27 = load float addrspace(1)* %arrayidx6.i.i9.i123, align 4, !tbaa !4
  %28 = insertelement <8 x float> %26, float %27, i32 2
  %add.ptr4.sum142 = add i64 %add.ptr.sum, 11
  %arrayidx10.i.i10.i124 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum142
  %29 = load float addrspace(1)* %arrayidx10.i.i10.i124, align 4, !tbaa !4
  %30 = insertelement <8 x float> %28, float %29, i32 3
  %add.ptr4.sum143 = add i64 %add.ptr.sum, 12
  %arrayidx.i.i11.i125 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum143
  %31 = load float addrspace(1)* %arrayidx.i.i11.i125, align 4, !tbaa !4
  %32 = insertelement <8 x float> undef, float %31, i32 0
  %add.ptr4.sum144 = add i64 %add.ptr.sum, 13
  %arrayidx2.i9.i12.i126 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum144
  %33 = load float addrspace(1)* %arrayidx2.i9.i12.i126, align 4, !tbaa !4
  %34 = insertelement <8 x float> %32, float %33, i32 1
  %add.ptr4.sum145 = add i64 %add.ptr.sum, 14
  %arrayidx6.i11.i13.i127 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum145
  %35 = load float addrspace(1)* %arrayidx6.i11.i13.i127, align 4, !tbaa !4
  %36 = insertelement <8 x float> %34, float %35, i32 2
  %add.ptr4.sum146 = add i64 %add.ptr.sum, 15
  %arrayidx10.i13.i14.i128 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum146
  %37 = load float addrspace(1)* %arrayidx10.i13.i14.i128, align 4, !tbaa !4
  %38 = insertelement <8 x float> %36, float %37, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %30, <8 x float> %38, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %add.ptr7.sum = add i64 %indvars.iv171, %1
  %add.ptr8 = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr7.sum
  %39 = load float addrspace(1)* %add.ptr8, align 4, !tbaa !4
  %40 = insertelement <8 x float> undef, float %39, i32 0
  %add.ptr8.sum = add i64 %add.ptr7.sum, 1
  %arrayidx2.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum
  %41 = load float addrspace(1)* %arrayidx2.i.i.i, align 4, !tbaa !4
  %42 = insertelement <8 x float> %40, float %41, i32 1
  %add.ptr8.sum147 = add i64 %add.ptr7.sum, 2
  %arrayidx6.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum147
  %43 = load float addrspace(1)* %arrayidx6.i.i.i, align 4, !tbaa !4
  %44 = insertelement <8 x float> %42, float %43, i32 2
  %add.ptr8.sum148 = add i64 %add.ptr7.sum, 3
  %arrayidx10.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum148
  %45 = load float addrspace(1)* %arrayidx10.i.i.i, align 4, !tbaa !4
  %46 = insertelement <8 x float> %44, float %45, i32 3
  %add.ptr8.sum149 = add i64 %add.ptr7.sum, 4
  %arrayidx.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum149
  %47 = load float addrspace(1)* %arrayidx.i.i.i, align 4, !tbaa !4
  %48 = insertelement <8 x float> undef, float %47, i32 0
  %add.ptr8.sum150 = add i64 %add.ptr7.sum, 5
  %arrayidx2.i9.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum150
  %49 = load float addrspace(1)* %arrayidx2.i9.i.i, align 4, !tbaa !4
  %50 = insertelement <8 x float> %48, float %49, i32 1
  %add.ptr8.sum151 = add i64 %add.ptr7.sum, 6
  %arrayidx6.i11.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum151
  %51 = load float addrspace(1)* %arrayidx6.i11.i.i, align 4, !tbaa !4
  %52 = insertelement <8 x float> %50, float %51, i32 2
  %add.ptr8.sum152 = add i64 %add.ptr7.sum, 7
  %arrayidx10.i13.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum152
  %53 = load float addrspace(1)* %arrayidx10.i13.i.i, align 4, !tbaa !4
  %54 = insertelement <8 x float> %52, float %53, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %46, <8 x float> %54, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %add.ptr8.sum153 = add i64 %add.ptr7.sum, 8
  %arrayidx.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum153
  %55 = load float addrspace(1)* %arrayidx.i.i, align 4, !tbaa !4
  %56 = insertelement <8 x float> undef, float %55, i32 0
  %add.ptr8.sum154 = add i64 %add.ptr7.sum, 9
  %arrayidx2.i.i8.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum154
  %57 = load float addrspace(1)* %arrayidx2.i.i8.i, align 4, !tbaa !4
  %58 = insertelement <8 x float> %56, float %57, i32 1
  %add.ptr8.sum155 = add i64 %add.ptr7.sum, 10
  %arrayidx6.i.i9.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum155
  %59 = load float addrspace(1)* %arrayidx6.i.i9.i, align 4, !tbaa !4
  %60 = insertelement <8 x float> %58, float %59, i32 2
  %add.ptr8.sum156 = add i64 %add.ptr7.sum, 11
  %arrayidx10.i.i10.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum156
  %61 = load float addrspace(1)* %arrayidx10.i.i10.i, align 4, !tbaa !4
  %62 = insertelement <8 x float> %60, float %61, i32 3
  %add.ptr8.sum157 = add i64 %add.ptr7.sum, 12
  %arrayidx.i.i11.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum157
  %63 = load float addrspace(1)* %arrayidx.i.i11.i, align 4, !tbaa !4
  %64 = insertelement <8 x float> undef, float %63, i32 0
  %add.ptr8.sum158 = add i64 %add.ptr7.sum, 13
  %arrayidx2.i9.i12.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum158
  %65 = load float addrspace(1)* %arrayidx2.i9.i12.i, align 4, !tbaa !4
  %66 = insertelement <8 x float> %64, float %65, i32 1
  %add.ptr8.sum159 = add i64 %add.ptr7.sum, 14
  %arrayidx6.i11.i13.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum159
  %67 = load float addrspace(1)* %arrayidx6.i11.i13.i, align 4, !tbaa !4
  %68 = insertelement <8 x float> %66, float %67, i32 2
  %add.ptr8.sum160 = add i64 %add.ptr7.sum, 15
  %arrayidx10.i13.i14.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum160
  %69 = load float addrspace(1)* %arrayidx10.i13.i14.i, align 4, !tbaa !4
  %70 = insertelement <8 x float> %68, float %69, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %62, <8 x float> %70, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %71 = extractelement <16 x float> %mul12, i32 0
  %72 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %71, %72
  %73 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %73, %add
  %74 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %74, %add13
  %75 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %75, %add14
  %76 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %76, %add15
  %77 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %77, %add16
  %78 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %78, %add17
  %79 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %79, %add18
  %80 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %80, %add19
  %81 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %81, %add20
  %82 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %82, %add21
  %83 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %83, %add22
  %84 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %84, %add23
  %85 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %85, %add24
  %86 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %86, %add25
  %add27 = fadd float %temp.0165, %add26
  %indvars.iv.next172 = add nuw nsw i64 %indvars.iv171, 16
  %87 = trunc i64 %indvars.iv.next172 to i32
  %cmp3 = icmp slt i32 %87, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %indvars.iv = phi i64 [ %4, %for.body31.lr.ph ], [ %indvars.iv.next, %for.body31 ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %88 = add nsw i64 %indvars.iv, %6
  %arrayidx = getelementptr inbounds float addrspace(1)* %src, i64 %88
  %89 = load float addrspace(1)* %arrayidx, align 4, !tbaa !4
  %90 = add nsw i64 %indvars.iv, %5
  %arrayidx36 = getelementptr inbounds float addrspace(1)* %src2, i64 %90
  %91 = load float addrspace(1)* %arrayidx36, align 4, !tbaa !4
  %sub37 = fsub float %89, %91
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
  %exitcond = icmp eq i32 %lftr.wideiv, %width
  br i1 %exitcond, label %for.end48.loopexit, label %for.body31

for.end48.loopexit:                               ; preds = %for.body31
  %add46.lcssa = phi float [ %add46, %for.body31 ]
  br label %for.end48

for.end48:                                        ; preds = %for.end48.loopexit, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46.lcssa, %for.end48.loopexit ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %92 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %92
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before Canonicalize natural loops ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %mul = mul nsw i32 %add.i132, %src_step
  %0 = sext i32 %mul to i64
  %mul6 = mul nsw i32 %add.i, %src2_step
  %1 = sext i32 %mul6 to i64
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %add27.lcssa = phi float [ %add27, %for.body ]
  %2 = add i32 %width, -1
  %3 = and i32 %2, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %3, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27.lcssa, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %mul32 = mul nsw i32 %add.i132, %src_step
  %mul34 = mul nsw i32 %add.i, %src2_step
  %4 = sext i32 %t.0.lcssa to i64
  %5 = sext i32 %mul34 to i64
  %6 = sext i32 %mul32 to i64
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %indvars.iv171 = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next172, %for.body ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %add.ptr.sum = add i64 %indvars.iv171, %0
  %add.ptr4 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr.sum
  %7 = load float addrspace(1)* %add.ptr4, align 4, !tbaa !4
  %8 = insertelement <8 x float> undef, float %7, i32 0
  %add.ptr4.sum = add i64 %add.ptr.sum, 1
  %arrayidx2.i.i.i112 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum
  %9 = load float addrspace(1)* %arrayidx2.i.i.i112, align 4, !tbaa !4
  %10 = insertelement <8 x float> %8, float %9, i32 1
  %add.ptr4.sum133 = add i64 %add.ptr.sum, 2
  %arrayidx6.i.i.i113 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum133
  %11 = load float addrspace(1)* %arrayidx6.i.i.i113, align 4, !tbaa !4
  %12 = insertelement <8 x float> %10, float %11, i32 2
  %add.ptr4.sum134 = add i64 %add.ptr.sum, 3
  %arrayidx10.i.i.i114 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum134
  %13 = load float addrspace(1)* %arrayidx10.i.i.i114, align 4, !tbaa !4
  %14 = insertelement <8 x float> %12, float %13, i32 3
  %add.ptr4.sum135 = add i64 %add.ptr.sum, 4
  %arrayidx.i.i.i115 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum135
  %15 = load float addrspace(1)* %arrayidx.i.i.i115, align 4, !tbaa !4
  %16 = insertelement <8 x float> undef, float %15, i32 0
  %add.ptr4.sum136 = add i64 %add.ptr.sum, 5
  %arrayidx2.i9.i.i116 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum136
  %17 = load float addrspace(1)* %arrayidx2.i9.i.i116, align 4, !tbaa !4
  %18 = insertelement <8 x float> %16, float %17, i32 1
  %add.ptr4.sum137 = add i64 %add.ptr.sum, 6
  %arrayidx6.i11.i.i117 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum137
  %19 = load float addrspace(1)* %arrayidx6.i11.i.i117, align 4, !tbaa !4
  %20 = insertelement <8 x float> %18, float %19, i32 2
  %add.ptr4.sum138 = add i64 %add.ptr.sum, 7
  %arrayidx10.i13.i.i118 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum138
  %21 = load float addrspace(1)* %arrayidx10.i13.i.i118, align 4, !tbaa !4
  %22 = insertelement <8 x float> %20, float %21, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %14, <8 x float> %22, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %add.ptr4.sum139 = add i64 %add.ptr.sum, 8
  %arrayidx.i.i121 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum139
  %23 = load float addrspace(1)* %arrayidx.i.i121, align 4, !tbaa !4
  %24 = insertelement <8 x float> undef, float %23, i32 0
  %add.ptr4.sum140 = add i64 %add.ptr.sum, 9
  %arrayidx2.i.i8.i122 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum140
  %25 = load float addrspace(1)* %arrayidx2.i.i8.i122, align 4, !tbaa !4
  %26 = insertelement <8 x float> %24, float %25, i32 1
  %add.ptr4.sum141 = add i64 %add.ptr.sum, 10
  %arrayidx6.i.i9.i123 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum141
  %27 = load float addrspace(1)* %arrayidx6.i.i9.i123, align 4, !tbaa !4
  %28 = insertelement <8 x float> %26, float %27, i32 2
  %add.ptr4.sum142 = add i64 %add.ptr.sum, 11
  %arrayidx10.i.i10.i124 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum142
  %29 = load float addrspace(1)* %arrayidx10.i.i10.i124, align 4, !tbaa !4
  %30 = insertelement <8 x float> %28, float %29, i32 3
  %add.ptr4.sum143 = add i64 %add.ptr.sum, 12
  %arrayidx.i.i11.i125 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum143
  %31 = load float addrspace(1)* %arrayidx.i.i11.i125, align 4, !tbaa !4
  %32 = insertelement <8 x float> undef, float %31, i32 0
  %add.ptr4.sum144 = add i64 %add.ptr.sum, 13
  %arrayidx2.i9.i12.i126 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum144
  %33 = load float addrspace(1)* %arrayidx2.i9.i12.i126, align 4, !tbaa !4
  %34 = insertelement <8 x float> %32, float %33, i32 1
  %add.ptr4.sum145 = add i64 %add.ptr.sum, 14
  %arrayidx6.i11.i13.i127 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum145
  %35 = load float addrspace(1)* %arrayidx6.i11.i13.i127, align 4, !tbaa !4
  %36 = insertelement <8 x float> %34, float %35, i32 2
  %add.ptr4.sum146 = add i64 %add.ptr.sum, 15
  %arrayidx10.i13.i14.i128 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum146
  %37 = load float addrspace(1)* %arrayidx10.i13.i14.i128, align 4, !tbaa !4
  %38 = insertelement <8 x float> %36, float %37, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %30, <8 x float> %38, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %add.ptr7.sum = add i64 %indvars.iv171, %1
  %add.ptr8 = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr7.sum
  %39 = load float addrspace(1)* %add.ptr8, align 4, !tbaa !4
  %40 = insertelement <8 x float> undef, float %39, i32 0
  %add.ptr8.sum = add i64 %add.ptr7.sum, 1
  %arrayidx2.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum
  %41 = load float addrspace(1)* %arrayidx2.i.i.i, align 4, !tbaa !4
  %42 = insertelement <8 x float> %40, float %41, i32 1
  %add.ptr8.sum147 = add i64 %add.ptr7.sum, 2
  %arrayidx6.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum147
  %43 = load float addrspace(1)* %arrayidx6.i.i.i, align 4, !tbaa !4
  %44 = insertelement <8 x float> %42, float %43, i32 2
  %add.ptr8.sum148 = add i64 %add.ptr7.sum, 3
  %arrayidx10.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum148
  %45 = load float addrspace(1)* %arrayidx10.i.i.i, align 4, !tbaa !4
  %46 = insertelement <8 x float> %44, float %45, i32 3
  %add.ptr8.sum149 = add i64 %add.ptr7.sum, 4
  %arrayidx.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum149
  %47 = load float addrspace(1)* %arrayidx.i.i.i, align 4, !tbaa !4
  %48 = insertelement <8 x float> undef, float %47, i32 0
  %add.ptr8.sum150 = add i64 %add.ptr7.sum, 5
  %arrayidx2.i9.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum150
  %49 = load float addrspace(1)* %arrayidx2.i9.i.i, align 4, !tbaa !4
  %50 = insertelement <8 x float> %48, float %49, i32 1
  %add.ptr8.sum151 = add i64 %add.ptr7.sum, 6
  %arrayidx6.i11.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum151
  %51 = load float addrspace(1)* %arrayidx6.i11.i.i, align 4, !tbaa !4
  %52 = insertelement <8 x float> %50, float %51, i32 2
  %add.ptr8.sum152 = add i64 %add.ptr7.sum, 7
  %arrayidx10.i13.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum152
  %53 = load float addrspace(1)* %arrayidx10.i13.i.i, align 4, !tbaa !4
  %54 = insertelement <8 x float> %52, float %53, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %46, <8 x float> %54, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %add.ptr8.sum153 = add i64 %add.ptr7.sum, 8
  %arrayidx.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum153
  %55 = load float addrspace(1)* %arrayidx.i.i, align 4, !tbaa !4
  %56 = insertelement <8 x float> undef, float %55, i32 0
  %add.ptr8.sum154 = add i64 %add.ptr7.sum, 9
  %arrayidx2.i.i8.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum154
  %57 = load float addrspace(1)* %arrayidx2.i.i8.i, align 4, !tbaa !4
  %58 = insertelement <8 x float> %56, float %57, i32 1
  %add.ptr8.sum155 = add i64 %add.ptr7.sum, 10
  %arrayidx6.i.i9.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum155
  %59 = load float addrspace(1)* %arrayidx6.i.i9.i, align 4, !tbaa !4
  %60 = insertelement <8 x float> %58, float %59, i32 2
  %add.ptr8.sum156 = add i64 %add.ptr7.sum, 11
  %arrayidx10.i.i10.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum156
  %61 = load float addrspace(1)* %arrayidx10.i.i10.i, align 4, !tbaa !4
  %62 = insertelement <8 x float> %60, float %61, i32 3
  %add.ptr8.sum157 = add i64 %add.ptr7.sum, 12
  %arrayidx.i.i11.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum157
  %63 = load float addrspace(1)* %arrayidx.i.i11.i, align 4, !tbaa !4
  %64 = insertelement <8 x float> undef, float %63, i32 0
  %add.ptr8.sum158 = add i64 %add.ptr7.sum, 13
  %arrayidx2.i9.i12.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum158
  %65 = load float addrspace(1)* %arrayidx2.i9.i12.i, align 4, !tbaa !4
  %66 = insertelement <8 x float> %64, float %65, i32 1
  %add.ptr8.sum159 = add i64 %add.ptr7.sum, 14
  %arrayidx6.i11.i13.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum159
  %67 = load float addrspace(1)* %arrayidx6.i11.i13.i, align 4, !tbaa !4
  %68 = insertelement <8 x float> %66, float %67, i32 2
  %add.ptr8.sum160 = add i64 %add.ptr7.sum, 15
  %arrayidx10.i13.i14.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum160
  %69 = load float addrspace(1)* %arrayidx10.i13.i14.i, align 4, !tbaa !4
  %70 = insertelement <8 x float> %68, float %69, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %62, <8 x float> %70, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %71 = extractelement <16 x float> %mul12, i32 0
  %72 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %71, %72
  %73 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %73, %add
  %74 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %74, %add13
  %75 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %75, %add14
  %76 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %76, %add15
  %77 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %77, %add16
  %78 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %78, %add17
  %79 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %79, %add18
  %80 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %80, %add19
  %81 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %81, %add20
  %82 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %82, %add21
  %83 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %83, %add22
  %84 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %84, %add23
  %85 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %85, %add24
  %86 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %86, %add25
  %add27 = fadd float %temp.0165, %add26
  %indvars.iv.next172 = add nuw nsw i64 %indvars.iv171, 16
  %87 = trunc i64 %indvars.iv.next172 to i32
  %cmp3 = icmp slt i32 %87, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %indvars.iv = phi i64 [ %4, %for.body31.lr.ph ], [ %indvars.iv.next, %for.body31 ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %88 = add nsw i64 %indvars.iv, %6
  %arrayidx = getelementptr inbounds float addrspace(1)* %src, i64 %88
  %89 = load float addrspace(1)* %arrayidx, align 4, !tbaa !4
  %90 = add nsw i64 %indvars.iv, %5
  %arrayidx36 = getelementptr inbounds float addrspace(1)* %src2, i64 %90
  %91 = load float addrspace(1)* %arrayidx36, align 4, !tbaa !4
  %sub37 = fsub float %89, %91
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
  %exitcond = icmp eq i32 %lftr.wideiv, %width
  br i1 %exitcond, label %for.end48.loopexit, label %for.body31

for.end48.loopexit:                               ; preds = %for.body31
  %add46.lcssa = phi float [ %add46, %for.body31 ]
  br label %for.end48

for.end48:                                        ; preds = %for.end48.loopexit, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46.lcssa, %for.end48.loopexit ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %92 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %92
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before Loop Strength Reduction ***
for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %indvars.iv = phi i64 [ %4, %for.body31.lr.ph ], [ %indvars.iv.next, %for.body31 ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %88 = add nsw i64 %indvars.iv, %6
  %arrayidx = getelementptr inbounds float addrspace(1)* %src, i64 %88
  %89 = load float addrspace(1)* %arrayidx, align 4, !tbaa !4
  %90 = add nsw i64 %indvars.iv, %5
  %arrayidx36 = getelementptr inbounds float addrspace(1)* %src2, i64 %90
  %91 = load float addrspace(1)* %arrayidx36, align 4, !tbaa !4
  %sub37 = fsub float %89, %91
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %indvars.iv.next = add nsw i64 %indvars.iv, 1
  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
  %exitcond = icmp eq i32 %lftr.wideiv, %width
  br i1 %exitcond, label %for.end48.loopexit, label %for.body31
*** IR Dump Before Loop Strength Reduction ***
for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %indvars.iv171 = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next172, %for.body ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %add.ptr.sum = add i64 %indvars.iv171, %0
  %add.ptr4 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr.sum
  %16 = load float addrspace(1)* %add.ptr4, align 4, !tbaa !4
  %17 = insertelement <8 x float> undef, float %16, i32 0
  %add.ptr4.sum = add i64 %add.ptr.sum, 1
  %arrayidx2.i.i.i112 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum
  %18 = load float addrspace(1)* %arrayidx2.i.i.i112, align 4, !tbaa !4
  %19 = insertelement <8 x float> %17, float %18, i32 1
  %add.ptr4.sum133 = add i64 %add.ptr.sum, 2
  %arrayidx6.i.i.i113 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum133
  %20 = load float addrspace(1)* %arrayidx6.i.i.i113, align 4, !tbaa !4
  %21 = insertelement <8 x float> %19, float %20, i32 2
  %add.ptr4.sum134 = add i64 %add.ptr.sum, 3
  %arrayidx10.i.i.i114 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum134
  %22 = load float addrspace(1)* %arrayidx10.i.i.i114, align 4, !tbaa !4
  %23 = insertelement <8 x float> %21, float %22, i32 3
  %add.ptr4.sum135 = add i64 %add.ptr.sum, 4
  %arrayidx.i.i.i115 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum135
  %24 = load float addrspace(1)* %arrayidx.i.i.i115, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %add.ptr4.sum136 = add i64 %add.ptr.sum, 5
  %arrayidx2.i9.i.i116 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum136
  %26 = load float addrspace(1)* %arrayidx2.i9.i.i116, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %add.ptr4.sum137 = add i64 %add.ptr.sum, 6
  %arrayidx6.i11.i.i117 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum137
  %28 = load float addrspace(1)* %arrayidx6.i11.i.i117, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %add.ptr4.sum138 = add i64 %add.ptr.sum, 7
  %arrayidx10.i13.i.i118 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum138
  %30 = load float addrspace(1)* %arrayidx10.i13.i.i118, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %23, <8 x float> %31, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %add.ptr4.sum139 = add i64 %add.ptr.sum, 8
  %arrayidx.i.i121 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum139
  %32 = load float addrspace(1)* %arrayidx.i.i121, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %add.ptr4.sum140 = add i64 %add.ptr.sum, 9
  %arrayidx2.i.i8.i122 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum140
  %34 = load float addrspace(1)* %arrayidx2.i.i8.i122, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %add.ptr4.sum141 = add i64 %add.ptr.sum, 10
  %arrayidx6.i.i9.i123 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum141
  %36 = load float addrspace(1)* %arrayidx6.i.i9.i123, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %add.ptr4.sum142 = add i64 %add.ptr.sum, 11
  %arrayidx10.i.i10.i124 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum142
  %38 = load float addrspace(1)* %arrayidx10.i.i10.i124, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %add.ptr4.sum143 = add i64 %add.ptr.sum, 12
  %arrayidx.i.i11.i125 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum143
  %40 = load float addrspace(1)* %arrayidx.i.i11.i125, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %add.ptr4.sum144 = add i64 %add.ptr.sum, 13
  %arrayidx2.i9.i12.i126 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum144
  %42 = load float addrspace(1)* %arrayidx2.i9.i12.i126, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %add.ptr4.sum145 = add i64 %add.ptr.sum, 14
  %arrayidx6.i11.i13.i127 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum145
  %44 = load float addrspace(1)* %arrayidx6.i11.i13.i127, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %add.ptr4.sum146 = add i64 %add.ptr.sum, 15
  %arrayidx10.i13.i14.i128 = getelementptr inbounds float addrspace(1)* %src, i64 %add.ptr4.sum146
  %46 = load float addrspace(1)* %arrayidx10.i13.i14.i128, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %39, <8 x float> %47, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %add.ptr7.sum = add i64 %indvars.iv171, %1
  %add.ptr8 = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr7.sum
  %48 = load float addrspace(1)* %add.ptr8, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %add.ptr8.sum = add i64 %add.ptr7.sum, 1
  %arrayidx2.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum
  %50 = load float addrspace(1)* %arrayidx2.i.i.i, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %add.ptr8.sum147 = add i64 %add.ptr7.sum, 2
  %arrayidx6.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum147
  %52 = load float addrspace(1)* %arrayidx6.i.i.i, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %add.ptr8.sum148 = add i64 %add.ptr7.sum, 3
  %arrayidx10.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum148
  %54 = load float addrspace(1)* %arrayidx10.i.i.i, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %add.ptr8.sum149 = add i64 %add.ptr7.sum, 4
  %arrayidx.i.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum149
  %56 = load float addrspace(1)* %arrayidx.i.i.i, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %add.ptr8.sum150 = add i64 %add.ptr7.sum, 5
  %arrayidx2.i9.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum150
  %58 = load float addrspace(1)* %arrayidx2.i9.i.i, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %add.ptr8.sum151 = add i64 %add.ptr7.sum, 6
  %arrayidx6.i11.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum151
  %60 = load float addrspace(1)* %arrayidx6.i11.i.i, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %add.ptr8.sum152 = add i64 %add.ptr7.sum, 7
  %arrayidx10.i13.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum152
  %62 = load float addrspace(1)* %arrayidx10.i13.i.i, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %55, <8 x float> %63, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %add.ptr8.sum153 = add i64 %add.ptr7.sum, 8
  %arrayidx.i.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum153
  %64 = load float addrspace(1)* %arrayidx.i.i, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %add.ptr8.sum154 = add i64 %add.ptr7.sum, 9
  %arrayidx2.i.i8.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum154
  %66 = load float addrspace(1)* %arrayidx2.i.i8.i, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %add.ptr8.sum155 = add i64 %add.ptr7.sum, 10
  %arrayidx6.i.i9.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum155
  %68 = load float addrspace(1)* %arrayidx6.i.i9.i, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %add.ptr8.sum156 = add i64 %add.ptr7.sum, 11
  %arrayidx10.i.i10.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum156
  %70 = load float addrspace(1)* %arrayidx10.i.i10.i, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %add.ptr8.sum157 = add i64 %add.ptr7.sum, 12
  %arrayidx.i.i11.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum157
  %72 = load float addrspace(1)* %arrayidx.i.i11.i, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %add.ptr8.sum158 = add i64 %add.ptr7.sum, 13
  %arrayidx2.i9.i12.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum158
  %74 = load float addrspace(1)* %arrayidx2.i9.i12.i, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %add.ptr8.sum159 = add i64 %add.ptr7.sum, 14
  %arrayidx6.i11.i13.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum159
  %76 = load float addrspace(1)* %arrayidx6.i11.i13.i, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %add.ptr8.sum160 = add i64 %add.ptr7.sum, 15
  %arrayidx10.i13.i14.i = getelementptr inbounds float addrspace(1)* %src2, i64 %add.ptr8.sum160
  %78 = load float addrspace(1)* %arrayidx10.i13.i14.i, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %71, <8 x float> %79, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %80 = extractelement <16 x float> %mul12, i32 0
  %81 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %80, %81
  %82 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %82, %add
  %83 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %83, %add13
  %84 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %84, %add14
  %85 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %85, %add15
  %86 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %86, %add16
  %87 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %87, %add17
  %88 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %88, %add18
  %89 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %89, %add19
  %90 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %90, %add20
  %91 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %91, %add21
  %92 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %92, %add22
  %93 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %93, %add23
  %94 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %94, %add24
  %95 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %95, %add25
  %add27 = fadd float %temp.0165, %add26
  %indvars.iv.next172 = add nuw nsw i64 %indvars.iv171, 16
  %96 = trunc i64 %indvars.iv.next172 to i32
  %cmp3 = icmp slt i32 %96, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge
*** IR Dump Before Lower Garbage Collection Instructions ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %add27.lcssa = phi float [ %add27, %for.body ]
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27.lcssa, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %for.end48.loopexit, label %for.body31

for.end48.loopexit:                               ; preds = %for.body31
  %add46.lcssa = phi float [ %add46, %for.body31 ]
  br label %for.end48

for.end48:                                        ; preds = %for.end48.loopexit, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46.lcssa, %for.end48.loopexit ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %106 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %106
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before Remove unreachable blocks from the CFG ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %add27.lcssa = phi float [ %add27, %for.body ]
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27.lcssa, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %for.end48.loopexit, label %for.body31

for.end48.loopexit:                               ; preds = %for.body31
  %add46.lcssa = phi float [ %add46, %for.body31 ]
  br label %for.end48

for.end48:                                        ; preds = %for.end48.loopexit, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46.lcssa, %for.end48.loopexit ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %106 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %106
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before Constant Hoisting ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %add27.lcssa = phi float [ %add27, %for.body ]
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27.lcssa, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %for.end48.loopexit, label %for.body31

for.end48.loopexit:                               ; preds = %for.body31
  %add46.lcssa = phi float [ %add46, %for.body31 ]
  br label %for.end48

for.end48:                                        ; preds = %for.end48.loopexit, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46.lcssa, %for.end48.loopexit ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %106 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %106
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before CodeGen Prepare ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %add27.lcssa = phi float [ %add27, %for.body ]
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27.lcssa, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %for.end48.loopexit, label %for.body31

for.end48.loopexit:                               ; preds = %for.body31
  %add46.lcssa = phi float [ %add46, %for.body31 ]
  br label %for.end48

for.end48:                                        ; preds = %for.end48.loopexit, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46.lcssa, %for.end48.loopexit ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %106 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %106
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before Lower invoke and unwind, for unwindless code generators ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %for.end48, label %for.body31

for.end48:                                        ; preds = %for.body31, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46, %for.body31 ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %106 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %106
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before Remove unreachable blocks from the CFG ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %for.end48, label %for.body31

for.end48:                                        ; preds = %for.body31, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46, %for.body31 ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %106 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %106
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before Flatten the CFG ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %for.end48, label %for.body31

for.end48:                                        ; preds = %for.body31, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46, %for.body31 ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %106 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %106
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before Lower SwitchInst's to branches ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %for.end48, label %for.body31

for.end48:                                        ; preds = %for.body31, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46, %for.body31 ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %106 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %106
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.end58:                                         ; preds = %if.else, %if.then51, %entry
  ret void
}
*** IR Dump Before Structurize control flow ***
for.end48:                                        ; preds = %for.body31, %for.cond29.preheader
  %temp.1.lcssa = phi float [ %temp.0.lcssa, %for.cond29.preheader ], [ %add46, %for.body31 ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %106 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %106
  br i1 %cmp50, label %if.then51, label %if.else

if.then51:                                        ; preds = %for.end48
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %if.end58
*** IR Dump Before Structurize control flow ***
for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %for.end48, label %for.body31
*** IR Dump Before Structurize control flow ***
for.cond29.preheader:                             ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %t.0.lcssa = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  %temp.0.lcssa = phi float [ %add27, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %for.end48

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body31:                                       ; preds = %for.body31, %for.body31.lr.ph
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep3, %for.body31.lr.ph ], [ %scevgep5, %for.body31 ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep, %for.body31.lr.ph ], [ %scevgep2, %for.body31 ]
  %lsr.iv = phi i32 [ %12, %for.body31.lr.ph ], [ %lsr.iv.next, %for.body31 ]
  %temp.1162 = phi float [ %temp.0.lcssa, %for.body31.lr.ph ], [ %add46, %for.body31 ]
  %104 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %105 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %104, %105
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %Flow45, label %for.body31

Flow45:                                           ; preds = %for.body31
  br label %for.end48
*** IR Dump Before Structurize control flow ***
for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  br i1 %cmp3, label %for.body, label %for.cond.for.cond29.preheader_crit_edge
*** IR Dump Before Structurize control flow ***
for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %for.cond29.preheader

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.body:                                         ; preds = %for.body, %for.body.lr.ph
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep26, %for.body.lr.ph ], [ %scevgep28, %for.body ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep8, %for.body.lr.ph ], [ %scevgep10, %for.body ]
  %lsr.iv6 = phi i32 [ 0, %for.body.lr.ph ], [ %lsr.iv.next7, %for.body ]
  %temp.0165 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add27, %for.body ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %24 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %25 = insertelement <8 x float> undef, float %24, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %26 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %27 = insertelement <8 x float> %25, float %26, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %28 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %30 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %32 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %33 = insertelement <8 x float> undef, float %32, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %34 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %35 = insertelement <8 x float> %33, float %34, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %36 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %38 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %31, <8 x float> %39, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %40 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %41 = insertelement <8 x float> undef, float %40, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %42 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %44 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %46 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %48 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %49 = insertelement <8 x float> undef, float %48, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %50 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %52 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %54 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %47, <8 x float> %55, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %56 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %57 = insertelement <8 x float> undef, float %56, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %58 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %60 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %62 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %64 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %65 = insertelement <8 x float> undef, float %64, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %66 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %68 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %70 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %63, <8 x float> %71, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %72 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %73 = insertelement <8 x float> undef, float %72, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %74 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %76 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %78 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %80 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %81 = insertelement <8 x float> undef, float %80, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %82 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %84 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %86 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %79, <8 x float> %87, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %88 = extractelement <16 x float> %mul12, i32 0
  %89 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %88, %89
  %90 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %90, %add
  %91 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %91, %add13
  %92 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %92, %add14
  %93 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %93, %add15
  %94 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %94, %add16
  %95 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %95, %add17
  %96 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %96, %add18
  %97 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %97, %add19
  %98 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %98, %add20
  %99 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %99, %add21
  %100 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %100, %add22
  %101 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %101, %add23
  %102 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %102, %add24
  %103 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %103, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  %104 = xor i1 %cmp3, true
  br i1 %104, label %for.cond.for.cond29.preheader_crit_edge, label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %for.cond29.preheader
*** IR Dump Before Structurize control flow ***
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %if.end58

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %Flow47

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.body:                                         ; preds = %for.body.lr.ph, %for.body
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ %add27, %for.body ], [ 0.000000e+00, %for.body.lr.ph ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %26 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %27 = insertelement <8 x float> undef, float %26, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %28 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %30 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %32 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %33 = insertelement <8 x float> %31, float %32, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %34 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %35 = insertelement <8 x float> undef, float %34, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %36 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %38 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %40 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %41 = insertelement <8 x float> %39, float %40, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %33, <8 x float> %41, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %42 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %43 = insertelement <8 x float> undef, float %42, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %44 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %46 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %48 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %49 = insertelement <8 x float> %47, float %48, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %50 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %51 = insertelement <8 x float> undef, float %50, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %52 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %54 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %56 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %57 = insertelement <8 x float> %55, float %56, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %49, <8 x float> %57, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %58 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %59 = insertelement <8 x float> undef, float %58, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %60 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %62 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %64 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %65 = insertelement <8 x float> %63, float %64, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %66 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %67 = insertelement <8 x float> undef, float %66, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %68 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %70 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %72 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %73 = insertelement <8 x float> %71, float %72, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %65, <8 x float> %73, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %74 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %75 = insertelement <8 x float> undef, float %74, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %76 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %78 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %80 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %81 = insertelement <8 x float> %79, float %80, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %82 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %83 = insertelement <8 x float> undef, float %82, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %84 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %86 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %88 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %89 = insertelement <8 x float> %87, float %88, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %81, <8 x float> %89, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %90 = extractelement <16 x float> %mul12, i32 0
  %91 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %90, %91
  %92 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %92, %add
  %93 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %93, %add13
  %94 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %94, %add14
  %95 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %95, %add15
  %96 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %96, %add16
  %97 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %97, %add17
  %98 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %98, %add18
  %99 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %99, %add19
  %100 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %100, %add20
  %101 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %101, %add21
  %102 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %102, %add22
  %103 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %103, %add23
  %104 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %104, %add24
  %105 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %105, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  %106 = xor i1 %cmp3, true
  br i1 %106, label %for.cond.for.cond29.preheader_crit_edge, label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %Flow47

Flow47:                                           ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %24 = phi float [ %add27, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %25 = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %Flow47
  %t.0.lcssa = phi i32 [ %25, %Flow47 ]
  %temp.0.lcssa = phi float [ %24, %Flow47 ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %Flow46

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body31:                                       ; preds = %for.body31.lr.ph, %for.body31
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %add46, %for.body31 ], [ %temp.0.lcssa, %for.body31.lr.ph ]
  %108 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %109 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %108, %109
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %Flow45, label %for.body31

Flow45:                                           ; preds = %for.body31
  br label %Flow46

Flow46:                                           ; preds = %Flow45, %for.cond29.preheader
  %107 = phi float [ %add46, %Flow45 ], [ %temp.0.lcssa, %for.cond29.preheader ]
  br label %for.end48

for.end48:                                        ; preds = %Flow46
  %temp.1.lcssa = phi float [ %107, %Flow46 ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %110 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %110
  %111 = xor i1 %cmp50, true
  br i1 %111, label %if.else, label %Flow

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %Flow

Flow:                                             ; preds = %if.else, %for.end48
  %112 = phi i1 [ false, %if.else ], [ true, %for.end48 ]
  br i1 %112, label %if.then51, label %Flow44

if.then51:                                        ; preds = %Flow
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %Flow44

Flow44:                                           ; preds = %if.then51, %Flow
  br label %if.end58
*** IR Dump Before Structurize control flow ***
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %Flow48

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %Flow47

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.body:                                         ; preds = %for.body.lr.ph, %for.body
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ %add27, %for.body ], [ 0.000000e+00, %for.body.lr.ph ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %26 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %27 = insertelement <8 x float> undef, float %26, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %28 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %30 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %32 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %33 = insertelement <8 x float> %31, float %32, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %34 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %35 = insertelement <8 x float> undef, float %34, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %36 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %38 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %40 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %41 = insertelement <8 x float> %39, float %40, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %33, <8 x float> %41, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %42 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %43 = insertelement <8 x float> undef, float %42, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %44 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %46 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %48 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %49 = insertelement <8 x float> %47, float %48, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %50 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %51 = insertelement <8 x float> undef, float %50, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %52 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %54 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %56 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %57 = insertelement <8 x float> %55, float %56, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %49, <8 x float> %57, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %58 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %59 = insertelement <8 x float> undef, float %58, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %60 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %62 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %64 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %65 = insertelement <8 x float> %63, float %64, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %66 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %67 = insertelement <8 x float> undef, float %66, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %68 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %70 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %72 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %73 = insertelement <8 x float> %71, float %72, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %65, <8 x float> %73, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %74 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %75 = insertelement <8 x float> undef, float %74, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %76 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %78 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %80 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %81 = insertelement <8 x float> %79, float %80, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %82 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %83 = insertelement <8 x float> undef, float %82, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %84 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %86 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %88 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %89 = insertelement <8 x float> %87, float %88, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %81, <8 x float> %89, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %90 = extractelement <16 x float> %mul12, i32 0
  %91 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %90, %91
  %92 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %92, %add
  %93 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %93, %add13
  %94 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %94, %add14
  %95 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %95, %add15
  %96 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %96, %add16
  %97 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %97, %add17
  %98 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %98, %add18
  %99 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %99, %add19
  %100 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %100, %add20
  %101 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %101, %add21
  %102 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %102, %add22
  %103 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %103, %add23
  %104 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %104, %add24
  %105 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %105, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  %106 = xor i1 %cmp3, true
  br i1 %106, label %for.cond.for.cond29.preheader_crit_edge, label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %Flow47

Flow47:                                           ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %24 = phi float [ %add27, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %25 = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  br label %for.cond29.preheader

for.cond29.preheader:                             ; preds = %Flow47
  %t.0.lcssa = phi i32 [ %25, %Flow47 ]
  %temp.0.lcssa = phi float [ %24, %Flow47 ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %Flow46

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

for.body31:                                       ; preds = %for.body31.lr.ph, %for.body31
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %add46, %for.body31 ], [ %temp.0.lcssa, %for.body31.lr.ph ]
  %108 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %109 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %108, %109
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %Flow45, label %for.body31

Flow45:                                           ; preds = %for.body31
  br label %Flow46

Flow46:                                           ; preds = %Flow45, %for.cond29.preheader
  %107 = phi float [ %add46, %Flow45 ], [ %temp.0.lcssa, %for.cond29.preheader ]
  br label %for.end48

for.end48:                                        ; preds = %Flow46
  %temp.1.lcssa = phi float [ %107, %Flow46 ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %110 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %110
  %111 = xor i1 %cmp50, true
  br i1 %111, label %if.else, label %Flow

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %Flow

Flow:                                             ; preds = %if.else, %for.end48
  %112 = phi i1 [ false, %if.else ], [ true, %for.end48 ]
  br i1 %112, label %if.then51, label %Flow44

if.then51:                                        ; preds = %Flow
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %Flow44

Flow44:                                           ; preds = %if.then51, %Flow
  br label %Flow48

Flow48:                                           ; preds = %Flow44, %entry
  br label %if.end58

if.end58:                                         ; preds = %Flow48
  ret void
*** IR Dump Before Code sinking ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  br i1 %or.cond, label %for.cond.preheader, label %Flow48

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  br i1 %cmp3164, label %for.body.lr.ph, label %Flow47

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %0 = mul i32 %x.i12.i, %x.i.i
  %1 = add i32 %x.i4.i, %0
  %2 = mul i32 %src2_step, %1
  %3 = sext i32 %2 to i64
  %4 = add i64 %3, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %4
  %5 = mul i32 %y.i14.i, %y.i.i
  %6 = add i32 %y.i6.i, %5
  %7 = mul i32 %src_step, %6
  %8 = sext i32 %7 to i64
  %9 = add i64 %8, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %9
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  %10 = add i32 %width, -1
  %11 = and i32 %10, -16
  br label %Flow47

Flow48:                                           ; preds = %Flow44, %entry
  br label %if.end58

for.cond29.preheader:                             ; preds = %Flow47
  %t.0.lcssa = phi i32 [ %25, %Flow47 ]
  %temp.0.lcssa = phi float [ %24, %Flow47 ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  br i1 %cmp30161, label %for.body31.lr.ph, label %Flow46

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %12 = sub i32 %width, %t.0.lcssa
  %13 = sext i32 %t.0.lcssa to i64
  %14 = mul i32 %x.i12.i, %x.i.i
  %15 = add i32 %x.i4.i, %14
  %16 = mul i32 %src2_step, %15
  %17 = sext i32 %16 to i64
  %18 = add i64 %13, %17
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %18
  %19 = mul i32 %y.i14.i, %y.i.i
  %20 = add i32 %y.i6.i, %19
  %21 = mul i32 %src_step, %20
  %22 = sext i32 %21 to i64
  %23 = add i64 %13, %22
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %23
  br label %for.body31

Flow47:                                           ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %24 = phi float [ %add27, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %25 = phi i32 [ %11, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  br label %for.cond29.preheader

for.body:                                         ; preds = %for.body.lr.ph, %for.body
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ %add27, %for.body ], [ 0.000000e+00, %for.body.lr.ph ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %26 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %27 = insertelement <8 x float> undef, float %26, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %28 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %29 = insertelement <8 x float> %27, float %28, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %30 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %31 = insertelement <8 x float> %29, float %30, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %32 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %33 = insertelement <8 x float> %31, float %32, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %34 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %35 = insertelement <8 x float> undef, float %34, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %36 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %37 = insertelement <8 x float> %35, float %36, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %38 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %40 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %41 = insertelement <8 x float> %39, float %40, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %33, <8 x float> %41, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %42 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %43 = insertelement <8 x float> undef, float %42, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %44 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %45 = insertelement <8 x float> %43, float %44, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %46 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %48 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %49 = insertelement <8 x float> %47, float %48, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %50 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %51 = insertelement <8 x float> undef, float %50, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %52 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %53 = insertelement <8 x float> %51, float %52, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %54 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %56 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %57 = insertelement <8 x float> %55, float %56, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %49, <8 x float> %57, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %58 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %59 = insertelement <8 x float> undef, float %58, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %60 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %61 = insertelement <8 x float> %59, float %60, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %62 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %64 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %65 = insertelement <8 x float> %63, float %64, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %66 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %67 = insertelement <8 x float> undef, float %66, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %68 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %69 = insertelement <8 x float> %67, float %68, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %70 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %72 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %73 = insertelement <8 x float> %71, float %72, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %65, <8 x float> %73, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %74 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %75 = insertelement <8 x float> undef, float %74, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %76 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %77 = insertelement <8 x float> %75, float %76, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %78 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %80 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %81 = insertelement <8 x float> %79, float %80, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %82 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %83 = insertelement <8 x float> undef, float %82, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %84 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %85 = insertelement <8 x float> %83, float %84, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %86 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %88 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %89 = insertelement <8 x float> %87, float %88, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %81, <8 x float> %89, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %90 = extractelement <16 x float> %mul12, i32 0
  %91 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %90, %91
  %92 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %92, %add
  %93 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %93, %add13
  %94 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %94, %add14
  %95 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %95, %add15
  %96 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %96, %add16
  %97 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %97, %add17
  %98 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %98, %add18
  %99 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %99, %add19
  %100 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %100, %add20
  %101 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %101, %add21
  %102 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %102, %add22
  %103 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %103, %add23
  %104 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %104, %add24
  %105 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %105, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  %106 = xor i1 %cmp3, true
  br i1 %106, label %for.cond.for.cond29.preheader_crit_edge, label %for.body

Flow46:                                           ; preds = %Flow45, %for.cond29.preheader
  %107 = phi float [ %add46, %Flow45 ], [ %temp.0.lcssa, %for.cond29.preheader ]
  br label %for.end48

for.body31:                                       ; preds = %for.body31.lr.ph, %for.body31
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %12, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %add46, %for.body31 ], [ %temp.0.lcssa, %for.body31.lr.ph ]
  %108 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %109 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %108, %109
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  br i1 %exitcond, label %Flow45, label %for.body31

Flow45:                                           ; preds = %for.body31
  br label %Flow46

for.end48:                                        ; preds = %Flow46
  %temp.1.lcssa = phi float [ %107, %Flow46 ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %110 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %110
  %111 = xor i1 %cmp50, true
  br i1 %111, label %if.else, label %Flow

Flow:                                             ; preds = %if.else, %for.end48
  %112 = phi i1 [ false, %if.else ], [ true, %for.end48 ]
  br i1 %112, label %if.then51, label %Flow44

if.then51:                                        ; preds = %Flow
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %Flow44

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %Flow

Flow44:                                           ; preds = %if.then51, %Flow
  br label %Flow48

if.end58:                                         ; preds = %Flow48
  ret void
}
*** IR Dump Before Module Verifier ***
; Function Attrs: nounwind
define void @svm_rbf(float addrspace(1)* nocapture readonly %src, i32 %src_step, float addrspace(1)* nocapture readonly %src2, i32 %src2_step, float addrspace(1)* nocapture %dst, i32 %dst_step, i32 %src_rows, i32 %src2_cols, i32 %width, float %gamma) #0 {
entry:
  %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
  %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
  %mul26.i = mul i32 %x.i12.i, %x.i.i
  %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
  %add.i = add i32 %x.i4.i, %mul26.i
  %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
  %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
  %mul30.i = mul i32 %y.i14.i, %y.i.i
  %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
  %add.i132 = add i32 %y.i6.i, %mul30.i
  %cmp = icmp slt i32 %add.i132, %src_rows
  %cmp2 = icmp slt i32 %add.i, %src2_cols
  %or.cond = and i1 %cmp, %cmp2
  %0 = call { i1, i64 } @llvm.SI.if(i1 %or.cond)
  %1 = extractvalue { i1, i64 } %0, 0
  %2 = extractvalue { i1, i64 } %0, 1
  br i1 %1, label %for.cond.preheader, label %Flow48

for.cond.preheader:                               ; preds = %entry
  %sub = add nsw i32 %width, -16
  %cmp3164 = icmp sgt i32 %sub, 0
  %3 = call { i1, i64 } @llvm.SI.if(i1 %cmp3164)
  %4 = extractvalue { i1, i64 } %3, 0
  %5 = extractvalue { i1, i64 } %3, 1
  br i1 %4, label %for.body.lr.ph, label %Flow47

for.body.lr.ph:                                   ; preds = %for.cond.preheader
  %6 = mul i32 %x.i12.i, %x.i.i
  %7 = add i32 %x.i4.i, %6
  %8 = mul i32 %src2_step, %7
  %9 = sext i32 %8 to i64
  %10 = add i64 %9, 8
  %scevgep8 = getelementptr float addrspace(1)* %src2, i64 %10
  %11 = mul i32 %y.i14.i, %y.i.i
  %12 = add i32 %y.i6.i, %11
  %13 = mul i32 %src_step, %12
  %14 = sext i32 %13 to i64
  %15 = add i64 %14, 8
  %scevgep26 = getelementptr float addrspace(1)* %src, i64 %15
  br label %for.body

for.cond.for.cond29.preheader_crit_edge:          ; preds = %for.body
  call void @llvm.SI.end.cf(i64 %117)
  %16 = add i32 %width, -1
  %17 = and i32 %16, -16
  br label %Flow47

Flow48:                                           ; preds = %Flow44, %entry
  call void @llvm.SI.end.cf(i64 %2)
  br label %if.end58

for.cond29.preheader:                             ; preds = %Flow47
  %t.0.lcssa = phi i32 [ %34, %Flow47 ]
  %temp.0.lcssa = phi float [ %33, %Flow47 ]
  %cmp30161 = icmp slt i32 %t.0.lcssa, %width
  %18 = call { i1, i64 } @llvm.SI.if(i1 %cmp30161)
  %19 = extractvalue { i1, i64 } %18, 0
  %20 = extractvalue { i1, i64 } %18, 1
  br i1 %19, label %for.body31.lr.ph, label %Flow46

for.body31.lr.ph:                                 ; preds = %for.cond29.preheader
  %21 = sub i32 %width, %t.0.lcssa
  %22 = sext i32 %t.0.lcssa to i64
  %23 = mul i32 %x.i12.i, %x.i.i
  %24 = add i32 %x.i4.i, %23
  %25 = mul i32 %src2_step, %24
  %26 = sext i32 %25 to i64
  %27 = add i64 %22, %26
  %scevgep = getelementptr float addrspace(1)* %src2, i64 %27
  %28 = mul i32 %y.i14.i, %y.i.i
  %29 = add i32 %y.i6.i, %28
  %30 = mul i32 %src_step, %29
  %31 = sext i32 %30 to i64
  %32 = add i64 %22, %31
  %scevgep3 = getelementptr float addrspace(1)* %src, i64 %32
  br label %for.body31

Flow47:                                           ; preds = %for.cond.for.cond29.preheader_crit_edge, %for.cond.preheader
  %33 = phi float [ %add27, %for.cond.for.cond29.preheader_crit_edge ], [ 0.000000e+00, %for.cond.preheader ]
  %34 = phi i32 [ %17, %for.cond.for.cond29.preheader_crit_edge ], [ 0, %for.cond.preheader ]
  call void @llvm.SI.end.cf(i64 %5)
  br label %for.cond29.preheader

for.body:                                         ; preds = %for.body.lr.ph, %for.body
  %35 = phi i64 [ 0, %for.body.lr.ph ], [ %117, %for.body ]
  %lsr.iv27 = phi float addrspace(1)* [ %scevgep28, %for.body ], [ %scevgep26, %for.body.lr.ph ]
  %lsr.iv9 = phi float addrspace(1)* [ %scevgep10, %for.body ], [ %scevgep8, %for.body.lr.ph ]
  %lsr.iv6 = phi i32 [ %lsr.iv.next7, %for.body ], [ 0, %for.body.lr.ph ]
  %temp.0165 = phi float [ %add27, %for.body ], [ 0.000000e+00, %for.body.lr.ph ]
  %scevgep43 = getelementptr float addrspace(1)* %lsr.iv27, i64 -8
  %36 = load float addrspace(1)* %scevgep43, align 4, !tbaa !4
  %37 = insertelement <8 x float> undef, float %36, i32 0
  %scevgep42 = getelementptr float addrspace(1)* %lsr.iv27, i64 -7
  %38 = load float addrspace(1)* %scevgep42, align 4, !tbaa !4
  %39 = insertelement <8 x float> %37, float %38, i32 1
  %scevgep41 = getelementptr float addrspace(1)* %lsr.iv27, i64 -6
  %40 = load float addrspace(1)* %scevgep41, align 4, !tbaa !4
  %41 = insertelement <8 x float> %39, float %40, i32 2
  %scevgep40 = getelementptr float addrspace(1)* %lsr.iv27, i64 -5
  %42 = load float addrspace(1)* %scevgep40, align 4, !tbaa !4
  %43 = insertelement <8 x float> %41, float %42, i32 3
  %scevgep39 = getelementptr float addrspace(1)* %lsr.iv27, i64 -4
  %44 = load float addrspace(1)* %scevgep39, align 4, !tbaa !4
  %45 = insertelement <8 x float> undef, float %44, i32 0
  %scevgep38 = getelementptr float addrspace(1)* %lsr.iv27, i64 -3
  %46 = load float addrspace(1)* %scevgep38, align 4, !tbaa !4
  %47 = insertelement <8 x float> %45, float %46, i32 1
  %scevgep37 = getelementptr float addrspace(1)* %lsr.iv27, i64 -2
  %48 = load float addrspace(1)* %scevgep37, align 4, !tbaa !4
  %49 = insertelement <8 x float> %47, float %48, i32 2
  %scevgep36 = getelementptr float addrspace(1)* %lsr.iv27, i64 -1
  %50 = load float addrspace(1)* %scevgep36, align 4, !tbaa !4
  %51 = insertelement <8 x float> %49, float %50, i32 3
  %vecinit5.i.i119 = shufflevector <8 x float> %43, <8 x float> %51, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i120 = shufflevector <8 x float> %vecinit5.i.i119, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %52 = load float addrspace(1)* %lsr.iv27, align 4, !tbaa !4
  %53 = insertelement <8 x float> undef, float %52, i32 0
  %scevgep35 = getelementptr float addrspace(1)* %lsr.iv27, i64 1
  %54 = load float addrspace(1)* %scevgep35, align 4, !tbaa !4
  %55 = insertelement <8 x float> %53, float %54, i32 1
  %scevgep34 = getelementptr float addrspace(1)* %lsr.iv27, i64 2
  %56 = load float addrspace(1)* %scevgep34, align 4, !tbaa !4
  %57 = insertelement <8 x float> %55, float %56, i32 2
  %scevgep33 = getelementptr float addrspace(1)* %lsr.iv27, i64 3
  %58 = load float addrspace(1)* %scevgep33, align 4, !tbaa !4
  %59 = insertelement <8 x float> %57, float %58, i32 3
  %scevgep32 = getelementptr float addrspace(1)* %lsr.iv27, i64 4
  %60 = load float addrspace(1)* %scevgep32, align 4, !tbaa !4
  %61 = insertelement <8 x float> undef, float %60, i32 0
  %scevgep31 = getelementptr float addrspace(1)* %lsr.iv27, i64 5
  %62 = load float addrspace(1)* %scevgep31, align 4, !tbaa !4
  %63 = insertelement <8 x float> %61, float %62, i32 1
  %scevgep30 = getelementptr float addrspace(1)* %lsr.iv27, i64 6
  %64 = load float addrspace(1)* %scevgep30, align 4, !tbaa !4
  %65 = insertelement <8 x float> %63, float %64, i32 2
  %scevgep29 = getelementptr float addrspace(1)* %lsr.iv27, i64 7
  %66 = load float addrspace(1)* %scevgep29, align 4, !tbaa !4
  %67 = insertelement <8 x float> %65, float %66, i32 3
  %vecinit5.i15.i129 = shufflevector <8 x float> %59, <8 x float> %67, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i130 = shufflevector <8 x float> %vecinit5.i15.i129, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i131 = shufflevector <16 x float> %vext.i120, <16 x float> %vext4.i130, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %scevgep25 = getelementptr float addrspace(1)* %lsr.iv9, i64 -8
  %68 = load float addrspace(1)* %scevgep25, align 4, !tbaa !4
  %69 = insertelement <8 x float> undef, float %68, i32 0
  %scevgep24 = getelementptr float addrspace(1)* %lsr.iv9, i64 -7
  %70 = load float addrspace(1)* %scevgep24, align 4, !tbaa !4
  %71 = insertelement <8 x float> %69, float %70, i32 1
  %scevgep23 = getelementptr float addrspace(1)* %lsr.iv9, i64 -6
  %72 = load float addrspace(1)* %scevgep23, align 4, !tbaa !4
  %73 = insertelement <8 x float> %71, float %72, i32 2
  %scevgep22 = getelementptr float addrspace(1)* %lsr.iv9, i64 -5
  %74 = load float addrspace(1)* %scevgep22, align 4, !tbaa !4
  %75 = insertelement <8 x float> %73, float %74, i32 3
  %scevgep21 = getelementptr float addrspace(1)* %lsr.iv9, i64 -4
  %76 = load float addrspace(1)* %scevgep21, align 4, !tbaa !4
  %77 = insertelement <8 x float> undef, float %76, i32 0
  %scevgep20 = getelementptr float addrspace(1)* %lsr.iv9, i64 -3
  %78 = load float addrspace(1)* %scevgep20, align 4, !tbaa !4
  %79 = insertelement <8 x float> %77, float %78, i32 1
  %scevgep19 = getelementptr float addrspace(1)* %lsr.iv9, i64 -2
  %80 = load float addrspace(1)* %scevgep19, align 4, !tbaa !4
  %81 = insertelement <8 x float> %79, float %80, i32 2
  %scevgep18 = getelementptr float addrspace(1)* %lsr.iv9, i64 -1
  %82 = load float addrspace(1)* %scevgep18, align 4, !tbaa !4
  %83 = insertelement <8 x float> %81, float %82, i32 3
  %vecinit5.i.i = shufflevector <8 x float> %75, <8 x float> %83, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext.i = shufflevector <8 x float> %vecinit5.i.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %84 = load float addrspace(1)* %lsr.iv9, align 4, !tbaa !4
  %85 = insertelement <8 x float> undef, float %84, i32 0
  %scevgep17 = getelementptr float addrspace(1)* %lsr.iv9, i64 1
  %86 = load float addrspace(1)* %scevgep17, align 4, !tbaa !4
  %87 = insertelement <8 x float> %85, float %86, i32 1
  %scevgep16 = getelementptr float addrspace(1)* %lsr.iv9, i64 2
  %88 = load float addrspace(1)* %scevgep16, align 4, !tbaa !4
  %89 = insertelement <8 x float> %87, float %88, i32 2
  %scevgep15 = getelementptr float addrspace(1)* %lsr.iv9, i64 3
  %90 = load float addrspace(1)* %scevgep15, align 4, !tbaa !4
  %91 = insertelement <8 x float> %89, float %90, i32 3
  %scevgep14 = getelementptr float addrspace(1)* %lsr.iv9, i64 4
  %92 = load float addrspace(1)* %scevgep14, align 4, !tbaa !4
  %93 = insertelement <8 x float> undef, float %92, i32 0
  %scevgep13 = getelementptr float addrspace(1)* %lsr.iv9, i64 5
  %94 = load float addrspace(1)* %scevgep13, align 4, !tbaa !4
  %95 = insertelement <8 x float> %93, float %94, i32 1
  %scevgep12 = getelementptr float addrspace(1)* %lsr.iv9, i64 6
  %96 = load float addrspace(1)* %scevgep12, align 4, !tbaa !4
  %97 = insertelement <8 x float> %95, float %96, i32 2
  %scevgep11 = getelementptr float addrspace(1)* %lsr.iv9, i64 7
  %98 = load float addrspace(1)* %scevgep11, align 4, !tbaa !4
  %99 = insertelement <8 x float> %97, float %98, i32 3
  %vecinit5.i15.i = shufflevector <8 x float> %91, <8 x float> %99, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
  %vext4.i = shufflevector <8 x float> %vecinit5.i15.i, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %vecinit5.i = shufflevector <16 x float> %vext.i, <16 x float> %vext4.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
  %sub10 = fsub <16 x float> %vecinit5.i131, %vecinit5.i
  %mul12 = fmul <16 x float> %sub10, %sub10
  %100 = extractelement <16 x float> %mul12, i32 0
  %101 = extractelement <16 x float> %mul12, i32 1
  %add = fadd float %100, %101
  %102 = extractelement <16 x float> %mul12, i32 2
  %add13 = fadd float %102, %add
  %103 = extractelement <16 x float> %mul12, i32 3
  %add14 = fadd float %103, %add13
  %104 = extractelement <16 x float> %mul12, i32 4
  %add15 = fadd float %104, %add14
  %105 = extractelement <16 x float> %mul12, i32 5
  %add16 = fadd float %105, %add15
  %106 = extractelement <16 x float> %mul12, i32 6
  %add17 = fadd float %106, %add16
  %107 = extractelement <16 x float> %mul12, i32 7
  %add18 = fadd float %107, %add17
  %108 = extractelement <16 x float> %mul12, i32 8
  %add19 = fadd float %108, %add18
  %109 = extractelement <16 x float> %mul12, i32 9
  %add20 = fadd float %109, %add19
  %110 = extractelement <16 x float> %mul12, i32 10
  %add21 = fadd float %110, %add20
  %111 = extractelement <16 x float> %mul12, i32 11
  %add22 = fadd float %111, %add21
  %112 = extractelement <16 x float> %mul12, i32 12
  %add23 = fadd float %112, %add22
  %113 = extractelement <16 x float> %mul12, i32 13
  %add24 = fadd float %113, %add23
  %114 = extractelement <16 x float> %mul12, i32 14
  %add25 = fadd float %114, %add24
  %115 = extractelement <16 x float> %mul12, i32 15
  %add26 = fadd float %115, %add25
  %add27 = fadd float %temp.0165, %add26
  %lsr.iv.next7 = add i32 %lsr.iv6, 16
  %scevgep10 = getelementptr float addrspace(1)* %lsr.iv9, i64 16
  %scevgep28 = getelementptr float addrspace(1)* %lsr.iv27, i64 16
  %cmp3 = icmp slt i32 %lsr.iv.next7, %sub
  %116 = xor i1 %cmp3, true
  %117 = call i64 @llvm.SI.if.break(i1 %116, i64 %35)
  %118 = call i1 @llvm.SI.loop(i64 %117)
  br i1 %118, label %for.cond.for.cond29.preheader_crit_edge, label %for.body

Flow46:                                           ; preds = %Flow45, %for.cond29.preheader
  %119 = phi float [ %add46, %Flow45 ], [ %temp.0.lcssa, %for.cond29.preheader ]
  call void @llvm.SI.end.cf(i64 %20)
  br label %for.end48

for.body31:                                       ; preds = %for.body31.lr.ph, %for.body31
  %120 = phi i64 [ 0, %for.body31.lr.ph ], [ %123, %for.body31 ]
  %lsr.iv4 = phi float addrspace(1)* [ %scevgep5, %for.body31 ], [ %scevgep3, %for.body31.lr.ph ]
  %lsr.iv1 = phi float addrspace(1)* [ %scevgep2, %for.body31 ], [ %scevgep, %for.body31.lr.ph ]
  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body31 ], [ %21, %for.body31.lr.ph ]
  %temp.1162 = phi float [ %add46, %for.body31 ], [ %temp.0.lcssa, %for.body31.lr.ph ]
  %121 = load float addrspace(1)* %lsr.iv4, align 4, !tbaa !4
  %122 = load float addrspace(1)* %lsr.iv1, align 4, !tbaa !4
  %sub37 = fsub float %121, %122
  %mul45 = fmul float %sub37, %sub37
  %add46 = fadd float %temp.1162, %mul45
  %lsr.iv.next = add i32 %lsr.iv, -1
  %scevgep2 = getelementptr float addrspace(1)* %lsr.iv1, i64 1
  %scevgep5 = getelementptr float addrspace(1)* %lsr.iv4, i64 1
  %exitcond = icmp eq i32 %lsr.iv.next, 0
  %123 = call i64 @llvm.SI.if.break(i1 %exitcond, i64 %120)
  %124 = call i1 @llvm.SI.loop(i64 %123)
  br i1 %124, label %Flow45, label %for.body31

Flow45:                                           ; preds = %for.body31
  call void @llvm.SI.end.cf(i64 %123)
  br label %Flow46

for.end48:                                        ; preds = %Flow46
  %temp.1.lcssa = phi float [ %119, %Flow46 ]
  %mul49 = fmul float %temp.1.lcssa, %gamma
  %cmp50 = fcmp ogt float %mul49, 0x4750624DC0000000
  %mul52 = mul nsw i32 %add.i132, %dst_step
  %add53 = add nsw i32 %mul52, %add.i
  %125 = sext i32 %add53 to i64
  %arrayidx54 = getelementptr inbounds float addrspace(1)* %dst, i64 %125
  %126 = xor i1 %cmp50, true
  %127 = call { i1, i64 } @llvm.SI.if(i1 %126)
  %128 = extractvalue { i1, i64 } %127, 0
  %129 = extractvalue { i1, i64 } %127, 1
  br i1 %128, label %if.else, label %Flow

Flow:                                             ; preds = %if.else, %for.end48
  %130 = call { i1, i64 } @llvm.SI.else(i64 %129)
  %131 = extractvalue { i1, i64 } %130, 0
  %132 = extractvalue { i1, i64 } %130, 1
  br i1 %131, label %if.then51, label %Flow44

if.then51:                                        ; preds = %Flow
  store float 0x4750624DC0000000, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %Flow44

if.else:                                          ; preds = %for.end48
  store float %mul49, float addrspace(1)* %arrayidx54, align 4, !tbaa !4
  br label %Flow

Flow44:                                           ; preds = %if.then51, %Flow
  call void @llvm.SI.end.cf(i64 %132)
  br label %Flow48

if.end58:                                         ; preds = %Flow48
  ret void
}
# *** IR Dump Before Expand ISel Pseudo-instructions ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg56<def> = COPY %vreg78; VSrc_32:%vreg56 SGPR_32:%vreg78
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SReg_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SReg_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SReg_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SReg_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg148<def> = SI_ADDR64_RSRC 0; SReg_128:%vreg148
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg183<def> = REG_SEQUENCE %vreg182<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg184<def> = SI_ADDR64_RSRC %vreg185; SReg_128:%vreg184 SReg_64:%vreg185
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg188<def> = SI_ADDR64_RSRC %vreg189; SReg_128:%vreg188 SReg_64:%vreg189
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg195<def> = REG_SEQUENCE %vreg194<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg203<def> = REG_SEQUENCE %vreg202<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg211<def> = REG_SEQUENCE %vreg210<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg219<def> = REG_SEQUENCE %vreg218<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg227<def> = REG_SEQUENCE %vreg226<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg235<def> = REG_SEQUENCE %vreg234<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg243<def> = REG_SEQUENCE %vreg242<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg366<def> = SI_ADDR64_RSRC 0; SReg_128:%vreg366
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg387<def> = COPY %vreg56; VGPR_32:%vreg387 VSrc_32:%vreg56
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg387<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg387 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
	%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg396<def> = SI_ADDR64_RSRC 0; SReg_128:%vreg396
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg394<def> = SI_ADDR64_RSRC 0; SReg_128:%vreg394
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Tail Duplication ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg56<def> = COPY %vreg78; VSrc_32:%vreg56 SGPR_32:%vreg78
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SReg_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SReg_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SReg_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SReg_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg398<def> = S_MOV_B64 0; SGPR_64:%vreg398
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg398, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg398,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg183<def> = REG_SEQUENCE %vreg182<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
	%vreg405<def> = S_MOV_B32 0; SGPR_32:%vreg405
	%vreg404<def> = S_MOV_B32 61440; SGPR_32:%vreg404
	%vreg403<def> = REG_SEQUENCE %vreg405, sub0, %vreg404, sub1; SGPR_64:%vreg403 SGPR_32:%vreg405,%vreg404
	%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg403, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg403
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
	%vreg409<def> = S_MOV_B32 0; SGPR_32:%vreg409
	%vreg408<def> = S_MOV_B32 61440; SGPR_32:%vreg408
	%vreg407<def> = REG_SEQUENCE %vreg409, sub0, %vreg408, sub1; SGPR_64:%vreg407 SGPR_32:%vreg409,%vreg408
	%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg407, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg407
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg195<def> = REG_SEQUENCE %vreg194<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg203<def> = REG_SEQUENCE %vreg202<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg211<def> = REG_SEQUENCE %vreg210<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg219<def> = REG_SEQUENCE %vreg218<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg227<def> = REG_SEQUENCE %vreg226<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg235<def> = REG_SEQUENCE %vreg234<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg243<def> = REG_SEQUENCE %vreg242<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg410<def> = S_MOV_B64 0; SGPR_64:%vreg410
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg410, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg410,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg387<def> = COPY %vreg56; VGPR_32:%vreg387 VSrc_32:%vreg56
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg387<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg387 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
	%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Optimize machine instruction PHIs ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg56<def> = COPY %vreg78; VSrc_32:%vreg56 SGPR_32:%vreg78
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SReg_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SReg_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SReg_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SReg_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg398<def> = S_MOV_B64 0; SGPR_64:%vreg398
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg398, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg398,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg183<def> = REG_SEQUENCE %vreg182<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
	%vreg405<def> = S_MOV_B32 0; SGPR_32:%vreg405
	%vreg404<def> = S_MOV_B32 61440; SGPR_32:%vreg404
	%vreg403<def> = REG_SEQUENCE %vreg405, sub0, %vreg404, sub1; SGPR_64:%vreg403 SGPR_32:%vreg405,%vreg404
	%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg403, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg403
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
	%vreg409<def> = S_MOV_B32 0; SGPR_32:%vreg409
	%vreg408<def> = S_MOV_B32 61440; SGPR_32:%vreg408
	%vreg407<def> = REG_SEQUENCE %vreg409, sub0, %vreg408, sub1; SGPR_64:%vreg407 SGPR_32:%vreg409,%vreg408
	%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg407, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg407
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg195<def> = REG_SEQUENCE %vreg194<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg203<def> = REG_SEQUENCE %vreg202<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg211<def> = REG_SEQUENCE %vreg210<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg219<def> = REG_SEQUENCE %vreg218<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg227<def> = REG_SEQUENCE %vreg226<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg235<def> = REG_SEQUENCE %vreg234<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg243<def> = REG_SEQUENCE %vreg242<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg410<def> = S_MOV_B64 0; SGPR_64:%vreg410
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg410, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg410,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg387<def> = COPY %vreg56; VGPR_32:%vreg387 VSrc_32:%vreg56
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg387<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg387 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
	%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Slot index numbering ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg56<def> = COPY %vreg78; VSrc_32:%vreg56 SGPR_32:%vreg78
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SReg_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SReg_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SReg_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SReg_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg398<def> = S_MOV_B64 0; SGPR_64:%vreg398
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg398, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg398,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg183<def> = REG_SEQUENCE %vreg182<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
	%vreg405<def> = S_MOV_B32 0; SGPR_32:%vreg405
	%vreg404<def> = S_MOV_B32 61440; SGPR_32:%vreg404
	%vreg403<def> = REG_SEQUENCE %vreg405, sub0, %vreg404, sub1; SGPR_64:%vreg403 SGPR_32:%vreg405,%vreg404
	%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg403, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg403
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
	%vreg409<def> = S_MOV_B32 0; SGPR_32:%vreg409
	%vreg408<def> = S_MOV_B32 61440; SGPR_32:%vreg408
	%vreg407<def> = REG_SEQUENCE %vreg409, sub0, %vreg408, sub1; SGPR_64:%vreg407 SGPR_32:%vreg409,%vreg408
	%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg407, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg407
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg195<def> = REG_SEQUENCE %vreg194<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg203<def> = REG_SEQUENCE %vreg202<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg211<def> = REG_SEQUENCE %vreg210<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg219<def> = REG_SEQUENCE %vreg218<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg227<def> = REG_SEQUENCE %vreg226<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg235<def> = REG_SEQUENCE %vreg234<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg243<def> = REG_SEQUENCE %vreg242<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg410<def> = S_MOV_B64 0; SGPR_64:%vreg410
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg410, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg410,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg387<def> = COPY %vreg56; VGPR_32:%vreg387 VSrc_32:%vreg56
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg387<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg387 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
	%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Merge disjoint stack slots ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
32B		%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
48B		%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
64B		%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
112B		%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
144B		%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
160B		%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
176B		%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
192B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
208B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
224B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
240B		%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
256B		%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
272B		%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
288B		%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
304B		%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
320B		%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
336B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
352B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
368B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
384B		%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
400B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
416B		%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
432B		%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
448B		%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
464B		%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
480B		%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
496B		%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
512B		%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
528B		%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
544B		%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
560B		%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
576B		%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
592B		%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
608B		%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
624B		%vreg56<def> = COPY %vreg78; VSrc_32:%vreg56 SGPR_32:%vreg78
640B		%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
656B		%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
672B		%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
688B		%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
704B		%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
720B		%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
736B		%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
752B		%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
768B		%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
784B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

800B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
816B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
832B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
848B		%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
864B		%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
880B		%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
896B		%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
912B		%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
928B		%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
944B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

960B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
976B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
992B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
1008B		%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
1024B		%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
1040B		%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
1056B		%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
1072B		%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
1088B		%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
1104B		%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
1120B		%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
1136B		%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
1152B		%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
1168B		%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
1184B		%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
1200B		%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
1216B		%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
1232B		%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
1248B		%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
1264B		%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
1280B		%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
1296B		%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
1312B		%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
1328B		%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
1344B		%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
1360B		%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
1376B		%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
1392B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1408B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
1424B		%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
1440B		%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
1456B		%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
1472B		%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
1488B		%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
1504B		%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
1520B		%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
1536B		%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
1552B		%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
1568B		%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
1584B		%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
1600B		%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
1616B		%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
1632B		%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
1648B		%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
1664B		%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
1680B		%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
1696B		%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
1712B		%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
1728B		%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
1744B		%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
1760B		%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
1776B		%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
1792B		%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
1808B		%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
1824B		%vreg147<def> = S_MOV_B64 0; SReg_64:%vreg147
1840B		%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SReg_64:%vreg147
1856B		%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
1872B		%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
1888B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

1904B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
1920B		SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
1936B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
1952B		%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
1968B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

1984B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2000B		SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
2016B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2032B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2048B		%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
2064B		%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
2080B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
2096B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
2112B		%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2128B		%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
2144B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2160B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2176B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2192B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
2208B		%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
2224B		%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
2240B		%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
2256B		%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
2272B		%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
2288B		%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
2304B		%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
2320B		%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
2336B		%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
2352B		%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
2368B		%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
2384B		%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
2400B		%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
2416B		%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
2432B		%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
2448B		%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
2464B		%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
2480B		%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
2496B		%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
2512B		%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
2528B		%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
2544B		%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
2560B		%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
2576B		%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
2592B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2608B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
2624B		%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
2640B		%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
2656B		%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
2672B		%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
2688B		%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
2704B		%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
2720B		%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
2736B		%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
2752B		%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
2768B		%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
2784B		%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
2800B		%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
2816B		%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
2832B		%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
2848B		%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
2864B		%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
2880B		%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
2896B		%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
2912B		%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
2928B		%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
2944B		%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
2960B		%vreg352<def> = S_MOV_B64 0; SReg_64:%vreg352
2976B		%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SReg_64:%vreg352
2992B		%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
3008B		%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
3024B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3040B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3056B		%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
3072B		%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
3088B		SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
3104B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3120B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3136B		%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
3152B		%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
3168B		%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
3184B		%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
3200B		%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
3216B		%vreg398<def> = S_MOV_B64 0; SGPR_64:%vreg398
3232B		%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
3248B		%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
3264B		%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
3280B		%vreg148<def> = REG_SEQUENCE %vreg398, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg398,%vreg399
3296B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
3312B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
3328B		%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3344B		%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
3360B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
3376B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
3392B		%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3408B		%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
3424B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
3440B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
3456B		%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3472B		%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
3488B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
3504B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
3520B		%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3536B		%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
3552B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
3568B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
3584B		%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
3600B		%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
3616B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
3632B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
3648B		%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
3664B		%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
3680B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
3696B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
3712B		%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
3728B		%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
3744B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
3760B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
3776B		%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
3792B		%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
3808B		%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
3824B		%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
3840B		%vreg183<def> = REG_SEQUENCE %vreg182<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
3856B		%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
3872B		%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
3888B		%vreg405<def> = S_MOV_B32 0; SGPR_32:%vreg405
3904B		%vreg404<def> = S_MOV_B32 61440; SGPR_32:%vreg404
3920B		%vreg403<def> = REG_SEQUENCE %vreg405, sub0, %vreg404, sub1; SGPR_64:%vreg403 SGPR_32:%vreg405,%vreg404
3936B		%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg403, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg403
3952B		%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
3968B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
3984B		%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
4000B		%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
4016B		%vreg409<def> = S_MOV_B32 0; SGPR_32:%vreg409
4032B		%vreg408<def> = S_MOV_B32 61440; SGPR_32:%vreg408
4048B		%vreg407<def> = REG_SEQUENCE %vreg409, sub0, %vreg408, sub1; SGPR_64:%vreg407 SGPR_32:%vreg409,%vreg408
4064B		%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg407, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg407
4080B		%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
4096B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
4112B		%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4128B		%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
4144B		%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
4160B		%vreg195<def> = REG_SEQUENCE %vreg194<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
4176B		%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
4192B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
4208B		%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
4224B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
4240B		%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
4256B		%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
4272B		%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
4288B		%vreg203<def> = REG_SEQUENCE %vreg202<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
4304B		%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
4320B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
4336B		%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
4352B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
4368B		%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
4384B		%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
4400B		%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
4416B		%vreg211<def> = REG_SEQUENCE %vreg210<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
4432B		%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
4448B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
4464B		%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
4480B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
4496B		%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
4512B		%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
4528B		%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
4544B		%vreg219<def> = REG_SEQUENCE %vreg218<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
4560B		%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
4576B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
4592B		%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
4608B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
4624B		%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
4640B		%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
4656B		%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
4672B		%vreg227<def> = REG_SEQUENCE %vreg226<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
4688B		%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
4704B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
4720B		%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
4736B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
4752B		%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
4768B		%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
4784B		%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
4800B		%vreg235<def> = REG_SEQUENCE %vreg234<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
4816B		%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
4832B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
4848B		%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
4864B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
4880B		%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
4896B		%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
4912B		%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
4928B		%vreg243<def> = REG_SEQUENCE %vreg242<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
4944B		%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
4960B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
4976B		%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
4992B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
5008B		%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
5024B		%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
5040B		%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
5056B		%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
5072B		%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
5088B		%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
5104B		%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
5120B		%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
5136B		%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
5152B		%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
5168B		%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
5184B		%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
5200B		%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
5216B		%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
5232B		%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
5248B		%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
5264B		%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
5280B		%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
5296B		%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
5312B		%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
5328B		%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
5344B		%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
5360B		%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
5376B		%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
5392B		%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
5408B		%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
5424B		%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
5440B		%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
5456B		%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
5472B		%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
5488B		%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
5504B		%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
5520B		%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
5536B		%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
5552B		%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
5568B		%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
5584B		%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
5600B		%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
5616B		%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
5632B		%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
5648B		%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
5664B		%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
5680B		%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
5696B		%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
5712B		%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
5728B		%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
5744B		%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
5760B		%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
5776B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
5792B		%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
5808B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
5824B		%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
5840B		%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
5856B		%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
5872B		%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
5888B		%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
5904B		SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
5920B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

5936B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
5952B		%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
5968B		SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
5984B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

6000B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
6016B		%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
6032B		%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
6048B		%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
6064B		%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
6080B		%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
6096B		%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
6112B		%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
6128B		%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
6144B		%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
6160B		%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
6176B		%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
6192B		%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
6208B		%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
6224B		%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
6240B		%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
6256B		%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
6272B		%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
6288B		%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
6304B		%vreg410<def> = S_MOV_B64 0; SGPR_64:%vreg410
6320B		%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
6336B		%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
6352B		%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
6368B		%vreg366<def> = REG_SEQUENCE %vreg410, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg410,%vreg411
6384B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
6400B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
6416B		%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
6432B		%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
6448B		%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
6464B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
6480B		%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
6496B		%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
6512B		%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
6528B		%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
6544B		%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
6560B		SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
6576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

6592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
6608B		SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
6624B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

6640B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
6656B		%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
6672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
6688B		%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
6704B		%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
6720B		%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
6736B		%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
6752B		%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
6768B		%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
6784B		%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
6800B		%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
6816B		%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
6832B		%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
6848B		%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
6864B		%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
6880B		%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
6896B		%vreg387<def> = COPY %vreg56; VGPR_32:%vreg387 VSrc_32:%vreg56
6912B		%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg387<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg387 VSrc_32:%vreg43
6928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
6944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
6960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
6976B		%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
6992B		%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
7008B		%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
7024B		%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
7040B		%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
7056B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

7072B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
7088B		%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
7104B		%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
7120B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

7136B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
7152B		%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
7168B		%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
7184B		%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
7200B		%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
7216B		%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
7232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
7248B		BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
7264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

7280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
7296B		%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
7312B		%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
7328B		%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
7344B		%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
7360B		%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
7376B		BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
7392B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

7408B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
7424B		SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
7440B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

7456B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
7472B		S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Local Stack Slot Allocation ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg56<def> = COPY %vreg78; VSrc_32:%vreg56 SGPR_32:%vreg78
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SReg_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SReg_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SReg_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SReg_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg398<def> = S_MOV_B64 0; SGPR_64:%vreg398
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg398, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg398,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg183<def> = REG_SEQUENCE %vreg182<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
	%vreg405<def> = S_MOV_B32 0; SGPR_32:%vreg405
	%vreg404<def> = S_MOV_B32 61440; SGPR_32:%vreg404
	%vreg403<def> = REG_SEQUENCE %vreg405, sub0, %vreg404, sub1; SGPR_64:%vreg403 SGPR_32:%vreg405,%vreg404
	%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg403, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg403
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
	%vreg409<def> = S_MOV_B32 0; SGPR_32:%vreg409
	%vreg408<def> = S_MOV_B32 61440; SGPR_32:%vreg408
	%vreg407<def> = REG_SEQUENCE %vreg409, sub0, %vreg408, sub1; SGPR_64:%vreg407 SGPR_32:%vreg409,%vreg408
	%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg407, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg407
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg195<def> = REG_SEQUENCE %vreg194<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg203<def> = REG_SEQUENCE %vreg202<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg211<def> = REG_SEQUENCE %vreg210<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg219<def> = REG_SEQUENCE %vreg218<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg227<def> = REG_SEQUENCE %vreg226<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg235<def> = REG_SEQUENCE %vreg234<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg243<def> = REG_SEQUENCE %vreg242<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg410<def> = S_MOV_B64 0; SGPR_64:%vreg410
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg410, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg410,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg387<def> = COPY %vreg56; VGPR_32:%vreg387 VSrc_32:%vreg56
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg387<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg387 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
	%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Remove dead machine instructions ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg56<def> = COPY %vreg78; VSrc_32:%vreg56 SGPR_32:%vreg78
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SReg_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SReg_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SReg_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SReg_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg398<def> = S_MOV_B64 0; SGPR_64:%vreg398
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg398, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg398,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg183<def> = REG_SEQUENCE %vreg182<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
	%vreg405<def> = S_MOV_B32 0; SGPR_32:%vreg405
	%vreg404<def> = S_MOV_B32 61440; SGPR_32:%vreg404
	%vreg403<def> = REG_SEQUENCE %vreg405, sub0, %vreg404, sub1; SGPR_64:%vreg403 SGPR_32:%vreg405,%vreg404
	%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg403, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg403
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
	%vreg409<def> = S_MOV_B32 0; SGPR_32:%vreg409
	%vreg408<def> = S_MOV_B32 61440; SGPR_32:%vreg408
	%vreg407<def> = REG_SEQUENCE %vreg409, sub0, %vreg408, sub1; SGPR_64:%vreg407 SGPR_32:%vreg409,%vreg408
	%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg407, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg407
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg195<def> = REG_SEQUENCE %vreg194<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg203<def> = REG_SEQUENCE %vreg202<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg211<def> = REG_SEQUENCE %vreg210<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg219<def> = REG_SEQUENCE %vreg218<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg227<def> = REG_SEQUENCE %vreg226<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg235<def> = REG_SEQUENCE %vreg234<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg243<def> = REG_SEQUENCE %vreg242<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg410<def> = S_MOV_B64 0; SGPR_64:%vreg410
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg410, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg410,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg387<def> = COPY %vreg56; VGPR_32:%vreg387 VSrc_32:%vreg56
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg387<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg387 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
	%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Machine Loop Invariant Code Motion ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg56<def> = COPY %vreg78; VSrc_32:%vreg56 SGPR_32:%vreg78
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SReg_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SReg_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SReg_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SReg_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg398<def> = S_MOV_B64 0; SGPR_64:%vreg398
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg398, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg398,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg183<def> = REG_SEQUENCE %vreg182<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
	%vreg405<def> = S_MOV_B32 0; SGPR_32:%vreg405
	%vreg404<def> = S_MOV_B32 61440; SGPR_32:%vreg404
	%vreg403<def> = REG_SEQUENCE %vreg405, sub0, %vreg404, sub1; SGPR_64:%vreg403 SGPR_32:%vreg405,%vreg404
	%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg403, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg403
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
	%vreg409<def> = S_MOV_B32 0; SGPR_32:%vreg409
	%vreg408<def> = S_MOV_B32 61440; SGPR_32:%vreg408
	%vreg407<def> = REG_SEQUENCE %vreg409, sub0, %vreg408, sub1; SGPR_64:%vreg407 SGPR_32:%vreg409,%vreg408
	%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg407, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg407
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg195<def> = REG_SEQUENCE %vreg194<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg203<def> = REG_SEQUENCE %vreg202<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg211<def> = REG_SEQUENCE %vreg210<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg219<def> = REG_SEQUENCE %vreg218<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg227<def> = REG_SEQUENCE %vreg226<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg235<def> = REG_SEQUENCE %vreg234<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg243<def> = REG_SEQUENCE %vreg242<kill>, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg410<def> = S_MOV_B64 0; SGPR_64:%vreg410
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg410, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg410,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg387<def> = COPY %vreg56; VGPR_32:%vreg387 VSrc_32:%vreg56
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg387<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg387 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
	%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Machine Common Subexpression Elimination ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg56<def> = COPY %vreg78; VSrc_32:%vreg56 SGPR_32:%vreg78
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SGPR_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SGPR_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg147,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183<def> = REG_SEQUENCE %vreg182, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
	%vreg403<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg403 SGPR_32:%vreg401,%vreg400
	%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg403, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg403
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
	%vreg407<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg407 SGPR_32:%vreg401,%vreg400
	%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg407, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg407
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195<def> = REG_SEQUENCE %vreg194, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203<def> = REG_SEQUENCE %vreg202, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211<def> = REG_SEQUENCE %vreg210, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219<def> = REG_SEQUENCE %vreg218, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227<def> = REG_SEQUENCE %vreg226, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235<def> = REG_SEQUENCE %vreg234, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243<def> = REG_SEQUENCE %vreg242, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg352, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg352,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg387<def> = COPY %vreg56; VGPR_32:%vreg387 VSrc_32:%vreg56
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg387<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg387 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
	%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Machine code sinking ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	%vreg8<def> = COPY %vreg86; SReg_64:%vreg8,%vreg86
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	%vreg10<def> = COPY %vreg92; SReg_64:%vreg10,%vreg92
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SGPR_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg8, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg8
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	%vreg16<def> = COPY %vreg302; SReg_64:%vreg16,%vreg302
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SGPR_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	SI_END_CF %vreg10, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg10
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg147,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183<def> = REG_SEQUENCE %vreg182, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
	%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg399
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
	%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg399
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195<def> = REG_SEQUENCE %vreg194, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203<def> = REG_SEQUENCE %vreg202, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211<def> = REG_SEQUENCE %vreg210, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219<def> = REG_SEQUENCE %vreg218, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227<def> = REG_SEQUENCE %vreg226, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235<def> = REG_SEQUENCE %vreg234, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243<def> = REG_SEQUENCE %vreg242, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg16, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg16
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg352, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg352,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg56 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	%vreg46<def> = COPY %vreg393; SReg_64:%vreg46,%vreg393
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg46<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg46
	%vreg47<def> = COPY %vreg395; SReg_64:%vreg47,%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg47, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg47
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Peephole Optimizations ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg64<def> = COPY %vreg59; SSrc_32:%vreg64 VReg_32:%vreg59
	%vreg65<def> = COPY %vreg63; SSrc_32:%vreg65 VReg_32:%vreg63
	%vreg3<def> = S_ADD_I32 %vreg64, %vreg65<kill>, %SCC<imp-def,dead>; SReg_32:%vreg3 SSrc_32:%vreg64,%vreg65
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg3, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 SReg_32:%vreg3 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg72<def> = COPY %vreg57; SSrc_32:%vreg72 VReg_32:%vreg57
	%vreg73<def> = COPY %vreg71; SSrc_32:%vreg73 VReg_32:%vreg71
	%vreg7<def> = S_ADD_I32 %vreg72, %vreg73<kill>, %SCC<imp-def,dead>; SReg_32:%vreg7 SSrc_32:%vreg72,%vreg73
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg7, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 SReg_32:%vreg7 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg6<def> = COPY %vreg57; SReg_32:%vreg6 VReg_32:%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg2<def> = COPY %vreg59; SReg_32:%vreg2 VReg_32:%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg88<def> = COPY %vreg90; SReg_32:%vreg88 VReg_32:%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VSrc_32:%vreg87 VGPR_32:%vreg91
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg99<def> = COPY %vreg97; SSrc_32:%vreg99 VReg_32:%vreg97
	%vreg98<def> = S_ADD_I32 %vreg6, %vreg99<kill>, %SCC<imp-def,dead>; SReg_32:%vreg98,%vreg6 SSrc_32:%vreg99
	%vreg100<def> = COPY %vreg98; VGPR_32:%vreg100 SReg_32:%vreg98
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg103<def> = COPY %vreg101; SSrc_32:%vreg103 VReg_32:%vreg101
	%vreg102<def> = S_ASHR_I32 %vreg103, 31; SReg_32:%vreg102 SSrc_32:%vreg103
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg102<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101 SReg_32:%vreg102
	%vreg106<def> = COPY %vreg104; SSrc_64:%vreg106 VReg_64:%vreg104
	%vreg105<def> = S_LSHL_B64 %vreg106<kill>, 2; SReg_64_with_sub0:%vreg105 SSrc_64:%vreg106
	%vreg107<def> = COPY %vreg105:sub0; SReg_32:%vreg107 SReg_64_with_sub0:%vreg105
	%vreg108<def> = COPY %vreg105:sub1; SReg_32:%vreg108 SReg_64_with_sub0:%vreg105
	%vreg109<def> = COPY %vreg49:sub0; SReg_32:%vreg109 VSrc_64_with_sub0:%vreg49
	%vreg110<def> = COPY %vreg49:sub1; SReg_32:%vreg110 VSrc_64_with_sub0:%vreg49
	%vreg111<def> = S_ADD_I32 %vreg107<kill>, %vreg109<kill>, %SCC<imp-def>; SReg_32:%vreg111,%vreg107,%vreg109
	%vreg112<def> = S_ADDC_U32 %vreg108<kill>, %vreg110<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg112,%vreg108,%vreg110
	%vreg113<def> = REG_SEQUENCE %vreg111<kill>, sub0, %vreg112<kill>, sub1; SGPR_64:%vreg113 SReg_32:%vreg111,%vreg112
	%vreg114<def> = COPY %vreg113:sub0; SReg_32:%vreg114 SGPR_64:%vreg113
	%vreg115<def> = COPY %vreg113:sub1; SReg_32:%vreg115 SGPR_64:%vreg113
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg119<def> = S_ADD_I32 %vreg114<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg119,%vreg114,%vreg117
	%vreg120<def> = S_ADDC_U32 %vreg115<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg120,%vreg115,%vreg118
	%vreg121<def> = REG_SEQUENCE %vreg119<kill>, sub0, %vreg120<kill>, sub1; SGPR_64:%vreg121 SReg_32:%vreg119,%vreg120
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg125<def> = COPY %vreg123; SSrc_32:%vreg125 VReg_32:%vreg123
	%vreg124<def> = S_ADD_I32 %vreg2, %vreg125<kill>, %SCC<imp-def,dead>; SReg_32:%vreg124,%vreg2 SSrc_32:%vreg125
	%vreg126<def> = COPY %vreg124; VGPR_32:%vreg126 SReg_32:%vreg124
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg129<def> = COPY %vreg127; SSrc_32:%vreg129 VReg_32:%vreg127
	%vreg128<def> = S_ASHR_I32 %vreg129, 31; SReg_32:%vreg128 SSrc_32:%vreg129
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg128<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127 SReg_32:%vreg128
	%vreg132<def> = COPY %vreg130; SSrc_64:%vreg132 VReg_64:%vreg130
	%vreg131<def> = S_LSHL_B64 %vreg132<kill>, 2; SReg_64_with_sub0:%vreg131 SSrc_64:%vreg132
	%vreg133<def> = COPY %vreg131:sub0; SReg_32:%vreg133 SReg_64_with_sub0:%vreg131
	%vreg134<def> = COPY %vreg131:sub1; SReg_32:%vreg134 SReg_64_with_sub0:%vreg131
	%vreg135<def> = COPY %vreg51:sub0; SReg_32:%vreg135 VSrc_64_with_sub0:%vreg51
	%vreg136<def> = COPY %vreg51:sub1; SReg_32:%vreg136 VSrc_64_with_sub0:%vreg51
	%vreg137<def> = S_ADD_I32 %vreg133<kill>, %vreg135<kill>, %SCC<imp-def>; SReg_32:%vreg137,%vreg133,%vreg135
	%vreg138<def> = S_ADDC_U32 %vreg134<kill>, %vreg136<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg138,%vreg134,%vreg136
	%vreg139<def> = REG_SEQUENCE %vreg137<kill>, sub0, %vreg138<kill>, sub1; SGPR_64:%vreg139 SReg_32:%vreg137,%vreg138
	%vreg140<def> = COPY %vreg139:sub0; SReg_32:%vreg140 SGPR_64:%vreg139
	%vreg141<def> = COPY %vreg139:sub1; SReg_32:%vreg141 SGPR_64:%vreg139
	%vreg142<def> = S_ADD_I32 %vreg140<kill>, %vreg117, %SCC<imp-def>; SReg_32:%vreg142,%vreg140,%vreg117
	%vreg143<def> = S_ADDC_U32 %vreg141<kill>, %vreg118, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg143,%vreg141,%vreg118
	%vreg144<def> = REG_SEQUENCE %vreg142<kill>, sub0, %vreg143<kill>, sub1; SGPR_64:%vreg144 SReg_32:%vreg142,%vreg143
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VSrc_32:%vreg95 VGPR_32:%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg94<def> = COPY %vreg146; SReg_32:%vreg94 VReg_32:%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; VSrc_64:%vreg93 SGPR_64:%vreg147
	%vreg12<def> = COPY %vreg121; VSrc_64:%vreg12 SGPR_64:%vreg121
	%vreg11<def> = COPY %vreg144; VSrc_64:%vreg11 SGPR_64:%vreg144
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg86, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg14<def> = PHI %vreg21, <BB#7>; SReg_32:%vreg14,%vreg21
	%vreg15<def> = PHI %vreg20, <BB#7>; VSrc_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg14, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 SReg_32:%vreg14 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg307<def> = COPY %vreg305; SSrc_32:%vreg307 VReg_32:%vreg305
	%vreg306<def> = S_ADD_I32 %vreg6, %vreg307<kill>, %SCC<imp-def,dead>; SReg_32:%vreg306,%vreg6 SSrc_32:%vreg307
	%vreg308<def> = COPY %vreg306; VGPR_32:%vreg308 SReg_32:%vreg306
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg311<def> = COPY %vreg309; SSrc_32:%vreg311 VReg_32:%vreg309
	%vreg310<def> = S_ASHR_I32 %vreg311, 31; SReg_32:%vreg310 SSrc_32:%vreg311
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg310<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309 SReg_32:%vreg310
	%vreg313<def> = COPY %vreg312:sub0; SReg_32:%vreg313 VReg_64:%vreg312
	%vreg314<def> = COPY %vreg312:sub1; SReg_32:%vreg314 VReg_64:%vreg312
	%vreg315<def> = S_ASHR_I32 %vreg14, 31; SReg_32:%vreg315,%vreg14
	%vreg316<def> = REG_SEQUENCE %vreg14, sub0, %vreg315<kill>, sub1; SGPR_64:%vreg316 SReg_32:%vreg14,%vreg315
	%vreg317<def> = COPY %vreg316:sub0; SReg_32:%vreg317 SGPR_64:%vreg316
	%vreg318<def> = COPY %vreg316:sub1; SReg_32:%vreg318 SGPR_64:%vreg316
	%vreg319<def> = S_ADD_I32 %vreg317, %vreg313<kill>, %SCC<imp-def>; SReg_32:%vreg319,%vreg317,%vreg313
	%vreg320<def> = S_ADDC_U32 %vreg318, %vreg314<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg320,%vreg318,%vreg314
	%vreg321<def> = REG_SEQUENCE %vreg319<kill>, sub0, %vreg320<kill>, sub1; SGPR_64:%vreg321 SReg_32:%vreg319,%vreg320
	%vreg322<def> = S_LSHL_B64 %vreg321<kill>, 2; SReg_64_with_sub0:%vreg322 SGPR_64:%vreg321
	%vreg323<def> = COPY %vreg322:sub0; SReg_32:%vreg323 SReg_64_with_sub0:%vreg322
	%vreg324<def> = COPY %vreg322:sub1; SReg_32:%vreg324 SReg_64_with_sub0:%vreg322
	%vreg325<def> = COPY %vreg49:sub0; SReg_32:%vreg325 VSrc_64_with_sub0:%vreg49
	%vreg326<def> = COPY %vreg49:sub1; SReg_32:%vreg326 VSrc_64_with_sub0:%vreg49
	%vreg327<def> = S_ADD_I32 %vreg325<kill>, %vreg323<kill>, %SCC<imp-def>; SReg_32:%vreg327,%vreg325,%vreg323
	%vreg328<def> = S_ADDC_U32 %vreg326<kill>, %vreg324<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg328,%vreg326,%vreg324
	%vreg329<def> = REG_SEQUENCE %vreg327<kill>, sub0, %vreg328<kill>, sub1; SGPR_64:%vreg329 SReg_32:%vreg327,%vreg328
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg333<def> = COPY %vreg331; SSrc_32:%vreg333 VReg_32:%vreg331
	%vreg332<def> = S_ADD_I32 %vreg2, %vreg333<kill>, %SCC<imp-def,dead>; SReg_32:%vreg332,%vreg2 SSrc_32:%vreg333
	%vreg334<def> = COPY %vreg332; VGPR_32:%vreg334 SReg_32:%vreg332
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg337<def> = COPY %vreg335; SSrc_32:%vreg337 VReg_32:%vreg335
	%vreg336<def> = S_ASHR_I32 %vreg337, 31; SReg_32:%vreg336 SSrc_32:%vreg337
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg336<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335 SReg_32:%vreg336
	%vreg339<def> = COPY %vreg338:sub0; SReg_32:%vreg339 VReg_64:%vreg338
	%vreg340<def> = COPY %vreg338:sub1; SReg_32:%vreg340 VReg_64:%vreg338
	%vreg341<def> = S_ADD_I32 %vreg317, %vreg339<kill>, %SCC<imp-def>; SReg_32:%vreg341,%vreg317,%vreg339
	%vreg342<def> = S_ADDC_U32 %vreg318, %vreg340<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg342,%vreg318,%vreg340
	%vreg343<def> = REG_SEQUENCE %vreg341<kill>, sub0, %vreg342<kill>, sub1; SGPR_64:%vreg343 SReg_32:%vreg341,%vreg342
	%vreg344<def> = S_LSHL_B64 %vreg343<kill>, 2; SReg_64_with_sub0:%vreg344 SGPR_64:%vreg343
	%vreg345<def> = COPY %vreg344:sub0; SReg_32:%vreg345 SReg_64_with_sub0:%vreg344
	%vreg346<def> = COPY %vreg344:sub1; SReg_32:%vreg346 SReg_64_with_sub0:%vreg344
	%vreg347<def> = COPY %vreg51:sub0; SReg_32:%vreg347 VSrc_64_with_sub0:%vreg51
	%vreg348<def> = COPY %vreg51:sub1; SReg_32:%vreg348 VSrc_64_with_sub0:%vreg51
	%vreg349<def> = S_ADD_I32 %vreg347<kill>, %vreg345<kill>, %SCC<imp-def>; SReg_32:%vreg349,%vreg347,%vreg345
	%vreg350<def> = S_ADDC_U32 %vreg348<kill>, %vreg346<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg350,%vreg348,%vreg346
	%vreg351<def> = REG_SEQUENCE %vreg349<kill>, sub0, %vreg350<kill>, sub1; SGPR_64:%vreg351 SReg_32:%vreg349,%vreg350
	%vreg17<def> = S_SUB_I32 %vreg55, %vreg14, %SCC<imp-def,dead>; SReg_32:%vreg17,%vreg55,%vreg14
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; VSrc_64:%vreg303 SGPR_64:%vreg352
	%vreg19<def> = COPY %vreg329; VSrc_64:%vreg19 SGPR_64:%vreg329
	%vreg18<def> = COPY %vreg351; VSrc_64:%vreg18 SGPR_64:%vreg351
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VSrc_32:%vreg20,%vreg87,%vreg27
	%vreg21<def> = PHI %vreg88, <BB#1>, %vreg13, <BB#3>; SReg_32:%vreg21,%vreg88,%vreg13
	%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	SI_END_CF %vreg92, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 VSrc_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg30, <BB#8>; VReg_64:%vreg23 VSrc_64:%vreg12,%vreg30
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg29, <BB#8>; VReg_64:%vreg24 VSrc_64:%vreg11,%vreg29
	%vreg25<def> = PHI %vreg94, <BB#2>, %vreg28, <BB#8>; SReg_32:%vreg25,%vreg94,%vreg28
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VSrc_32:%vreg26,%vreg95,%vreg27
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg147,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183<def> = REG_SEQUENCE %vreg182, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg185<def> = COPY %vreg24; SReg_64:%vreg185 VReg_64:%vreg24
	%vreg402<def> = S_MOV_B64 %vreg185; SGPR_64:%vreg402 SReg_64:%vreg185
	%vreg184<def> = REG_SEQUENCE %vreg402, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg184 SGPR_64:%vreg402,%vreg399
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg187, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg184 VReg_64:%vreg187
	%vreg189<def> = COPY %vreg23; SReg_64:%vreg189 VReg_64:%vreg23
	%vreg406<def> = S_MOV_B64 %vreg189; SGPR_64:%vreg406 SReg_64:%vreg189
	%vreg188<def> = REG_SEQUENCE %vreg406, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg188 SGPR_64:%vreg406,%vreg399
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg191, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg188 VReg_64:%vreg191
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195<def> = REG_SEQUENCE %vreg194, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg197, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg184 VReg_64:%vreg197
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg199, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg188 VReg_64:%vreg199
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203<def> = REG_SEQUENCE %vreg202, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg205, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg184 VReg_64:%vreg205
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg207, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg188 VReg_64:%vreg207
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211<def> = REG_SEQUENCE %vreg210, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg213, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg184 VReg_64:%vreg213
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg215, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg188 VReg_64:%vreg215
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219<def> = REG_SEQUENCE %vreg218, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg221, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg184 VReg_64:%vreg221
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg223, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg188 VReg_64:%vreg223
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227<def> = REG_SEQUENCE %vreg226, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg229, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg184 VReg_64:%vreg229
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg231, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg188 VReg_64:%vreg231
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235<def> = REG_SEQUENCE %vreg234, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg237, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg184 VReg_64:%vreg237
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg239, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg188 VReg_64:%vreg239
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243<def> = REG_SEQUENCE %vreg242, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg184, %vreg245, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg184 VReg_64:%vreg245
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg188, %vreg247, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg188 VReg_64:%vreg247
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg281 VSrc_32:%vreg26
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg285<def> = COPY %vreg23:sub0; SReg_32:%vreg285 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg287<def> = COPY %vreg23:sub1; SReg_32:%vreg287 VReg_64:%vreg23
	%vreg288<def> = S_ADD_I32 %vreg285<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg288,%vreg285,%vreg284
	%vreg289<def> = S_ADDC_U32 %vreg287<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg289,%vreg287,%vreg286
	%vreg290<def> = REG_SEQUENCE %vreg288<kill>, sub0, %vreg289<kill>, sub1; SGPR_64:%vreg290 SReg_32:%vreg288,%vreg289
	%vreg291<def> = COPY %vreg24:sub0; SReg_32:%vreg291 VReg_64:%vreg24
	%vreg292<def> = COPY %vreg24:sub1; SReg_32:%vreg292 VReg_64:%vreg24
	%vreg293<def> = S_ADD_I32 %vreg291<kill>, %vreg284, %SCC<imp-def>; SReg_32:%vreg293,%vreg291,%vreg284
	%vreg294<def> = S_ADDC_U32 %vreg292<kill>, %vreg286, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg294,%vreg292,%vreg286
	%vreg295<def> = REG_SEQUENCE %vreg293<kill>, sub0, %vreg294<kill>, sub1; SGPR_64:%vreg295 SReg_32:%vreg293,%vreg294
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg28<def> = S_ADD_I32 %vreg25, 16, %SCC<imp-def,dead>; SReg_32:%vreg28,%vreg25
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg28, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 SReg_32:%vreg28 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg30<def> = COPY %vreg290; VSrc_64:%vreg30 SGPR_64:%vreg290
	%vreg29<def> = COPY %vreg295; VSrc_64:%vreg29 SGPR_64:%vreg295
	%vreg27<def> = COPY %vreg282; VSrc_32:%vreg27 VGPR_32:%vreg282
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VSrc_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg302, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 VSrc_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg41, <BB#10>; VReg_64:%vreg34 VSrc_64:%vreg19,%vreg41
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg40, <BB#10>; VReg_64:%vreg35 VSrc_64:%vreg18,%vreg40
	%vreg36<def> = PHI %vreg17, <BB#6>, %vreg39, <BB#10>; SReg_32:%vreg36,%vreg17,%vreg39
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VSrc_32:%vreg37,%vreg15,%vreg38
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg355<def> = COPY %vreg34:sub0; SReg_32:%vreg355 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg357<def> = COPY %vreg34:sub1; SReg_32:%vreg357 VReg_64:%vreg34
	%vreg358<def> = S_ADD_I32 %vreg355<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg358,%vreg355,%vreg354
	%vreg359<def> = S_ADDC_U32 %vreg357<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg359,%vreg357,%vreg356
	%vreg360<def> = REG_SEQUENCE %vreg358<kill>, sub0, %vreg359<kill>, sub1; SGPR_64:%vreg360 SReg_32:%vreg358,%vreg359
	%vreg361<def> = COPY %vreg35:sub0; SReg_32:%vreg361 VReg_64:%vreg35
	%vreg362<def> = COPY %vreg35:sub1; SReg_32:%vreg362 VReg_64:%vreg35
	%vreg363<def> = S_ADD_I32 %vreg361<kill>, %vreg354, %SCC<imp-def>; SReg_32:%vreg363,%vreg361,%vreg354
	%vreg364<def> = S_ADDC_U32 %vreg362<kill>, %vreg356, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg364,%vreg362,%vreg356
	%vreg365<def> = REG_SEQUENCE %vreg363<kill>, sub0, %vreg364<kill>, sub1; SGPR_64:%vreg365 SReg_32:%vreg363,%vreg364
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg352, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg352,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369 VSrc_32:%vreg37
	%vreg39<def> = S_ADD_I32 %vreg36, -1, %SCC<imp-def,dead>; SReg_32:%vreg39,%vreg36
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg39, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 SReg_32:%vreg39
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg41<def> = COPY %vreg360; VSrc_64:%vreg41 SGPR_64:%vreg360
	%vreg40<def> = COPY %vreg365; VSrc_64:%vreg40 SGPR_64:%vreg365
	%vreg38<def> = COPY %vreg370; VSrc_32:%vreg38 VGPR_32:%vreg370
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VSrc_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg7, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374 SReg_32:%vreg7 VGPR_32:%vreg373
	%vreg376<def> = COPY %vreg374; SSrc_32:%vreg376 VReg_32:%vreg374
	%vreg375<def> = S_ADD_I32 %vreg376<kill>, %vreg3, %SCC<imp-def,dead>; SReg_32:%vreg375,%vreg3 SSrc_32:%vreg376
	%vreg377<def> = S_ASHR_I32 %vreg375, 31; SReg_32:%vreg377,%vreg375
	%vreg378<def> = REG_SEQUENCE %vreg375, sub0, %vreg377<kill>, sub1; SGPR_64:%vreg378 SReg_32:%vreg375,%vreg377
	%vreg379<def> = S_LSHL_B64 %vreg378<kill>, 2; SReg_64_with_sub0:%vreg379 SGPR_64:%vreg378
	%vreg380<def> = COPY %vreg379:sub0; SReg_32:%vreg380 SReg_64_with_sub0:%vreg379
	%vreg381<def> = COPY %vreg379:sub1; SReg_32:%vreg381 SReg_64_with_sub0:%vreg379
	%vreg382<def> = COPY %vreg53:sub0; SReg_32:%vreg382 VSrc_64_with_sub0:%vreg53
	%vreg383<def> = COPY %vreg53:sub1; SReg_32:%vreg383 VSrc_64_with_sub0:%vreg53
	%vreg384<def> = S_ADD_I32 %vreg382<kill>, %vreg380<kill>, %SCC<imp-def>; SReg_32:%vreg384,%vreg382,%vreg380
	%vreg385<def> = S_ADDC_U32 %vreg383<kill>, %vreg381<kill>, %SCC<imp-def,dead>, %SCC<imp-use>; SReg_32:%vreg385,%vreg383,%vreg381
	%vreg386<def> = REG_SEQUENCE %vreg384<kill>, sub0, %vreg385<kill>, sub1; SGPR_64:%vreg386 SReg_32:%vreg384,%vreg385
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg56 VSrc_32:%vreg43
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg45<def> = COPY %vreg386; VReg_64:%vreg45 SGPR_64:%vreg386
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg393<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg393
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg395, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Machine Common Subexpression Elimination ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg422<def> = COPY %vreg59; VReg_32:%vreg422,%vreg59
	%vreg438<def> = COPY %vreg63; VReg_32:%vreg438,%vreg63
	%vreg423<def> = V_ADD_I32_e32 %vreg438<kill>, %vreg422, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg423,%vreg438,%vreg422
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg439<def> = COPY %vreg57; VReg_32:%vreg439,%vreg57
	%vreg441<def> = COPY %vreg71; VReg_32:%vreg441,%vreg71
	%vreg440<def> = V_ADD_I32_e32 %vreg441<kill>, %vreg439, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg440,%vreg441,%vreg439
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg442<def> = COPY %vreg57; VReg_32:%vreg442,%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg445<def> = COPY %vreg59; VReg_32:%vreg445,%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg448<def> = COPY %vreg90; VReg_32:%vreg448,%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VGPR_32:%vreg87,%vreg91
	%vreg450<def> = COPY %vreg448; VReg_32:%vreg450,%vreg448
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg495<def> = COPY %vreg97; VReg_32:%vreg495,%vreg97
	%vreg443<def> = V_ADD_I32_e32 %vreg495<kill>, %vreg442, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg443,%vreg495,%vreg442
	%vreg100<def> = COPY %vreg443; VGPR_32:%vreg100 VReg_32:%vreg443
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg100<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg100
	%vreg496<def> = COPY %vreg101; VReg_32:%vreg496,%vreg101
	%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg496, %EXEC<imp-use>; VReg_32:%vreg497,%vreg496
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg497<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101,%vreg497
	%vreg498<def> = COPY %vreg104; VReg_64:%vreg498,%vreg104
	%vreg499<def> = V_LSHL_B64 %vreg498<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg498
	%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
	%vreg500<def> = COPY %vreg499:sub1; VReg_32:%vreg500 VReg_64:%vreg499
	%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
	%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
	%vreg515<def> = V_ADD_I32_e32 %vreg516<kill>, %vreg514<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
	%vreg502<def> = COPY %vreg517<kill>; VReg_32:%vreg502,%vreg517
	%vreg501<def> = V_ADDC_U32_e32 %vreg500<kill>, %vreg502, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg501,%vreg500,%vreg502
	%vreg504<def> = COPY %vreg515<kill>; VReg_32:%vreg504,%vreg515
	%vreg505<def> = COPY %vreg501<kill>; VReg_32:%vreg505,%vreg501
	%vreg503<def> = REG_SEQUENCE %vreg504<kill>, sub0, %vreg505<kill>, sub1; VReg_64:%vreg503 VReg_32:%vreg504,%vreg505
	%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
	%vreg506<def> = COPY %vreg503:sub1; VReg_32:%vreg506 VReg_64:%vreg503
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
	%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
	%vreg507<def> = V_ADDC_U32_e32 %vreg506<kill>, %vreg508, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg507,%vreg506,%vreg508
	%vreg510<def> = COPY %vreg513<kill>; VReg_32:%vreg510,%vreg513
	%vreg511<def> = COPY %vreg507<kill>; VReg_32:%vreg511,%vreg507
	%vreg509<def> = REG_SEQUENCE %vreg510<kill>, sub0, %vreg511<kill>, sub1; VReg_64:%vreg509 VReg_32:%vreg510,%vreg511
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg518<def> = COPY %vreg123; VReg_32:%vreg518,%vreg123
	%vreg446<def> = V_ADD_I32_e32 %vreg518<kill>, %vreg445, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg446,%vreg518,%vreg445
	%vreg126<def> = COPY %vreg446; VGPR_32:%vreg126 VReg_32:%vreg446
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg126<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg126
	%vreg519<def> = COPY %vreg127; VReg_32:%vreg519,%vreg127
	%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg519, %EXEC<imp-use>; VReg_32:%vreg520,%vreg519
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg520<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127,%vreg520
	%vreg521<def> = COPY %vreg130; VReg_64:%vreg521,%vreg130
	%vreg522<def> = V_LSHL_B64 %vreg521<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg521
	%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
	%vreg523<def> = COPY %vreg522:sub1; VReg_32:%vreg523 VReg_64:%vreg522
	%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
	%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
	%vreg538<def> = V_ADD_I32_e32 %vreg539<kill>, %vreg537<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
	%vreg525<def> = COPY %vreg540<kill>; VReg_32:%vreg525,%vreg540
	%vreg524<def> = V_ADDC_U32_e32 %vreg523<kill>, %vreg525, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg524,%vreg523,%vreg525
	%vreg527<def> = COPY %vreg538<kill>; VReg_32:%vreg527,%vreg538
	%vreg528<def> = COPY %vreg524<kill>; VReg_32:%vreg528,%vreg524
	%vreg526<def> = REG_SEQUENCE %vreg527<kill>, sub0, %vreg528<kill>, sub1; VReg_64:%vreg526 VReg_32:%vreg527,%vreg528
	%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
	%vreg529<def> = COPY %vreg526:sub1; VReg_32:%vreg529 VReg_64:%vreg526
	%vreg536<def> = V_ADD_I32_e32 %vreg117, %vreg535<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
	%vreg531<def> = COPY %vreg118; VReg_32:%vreg531 SReg_32:%vreg118
	%vreg530<def> = V_ADDC_U32_e32 %vreg529<kill>, %vreg531, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg530,%vreg529,%vreg531
	%vreg533<def> = COPY %vreg536<kill>; VReg_32:%vreg533,%vreg536
	%vreg534<def> = COPY %vreg530<kill>; VReg_32:%vreg534,%vreg530
	%vreg532<def> = REG_SEQUENCE %vreg533<kill>, sub0, %vreg534<kill>, sub1; VReg_64:%vreg532 VReg_32:%vreg533,%vreg534
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VGPR_32:%vreg95,%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg541<def> = COPY %vreg146; VReg_32:%vreg541,%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
	%vreg12<def> = COPY %vreg509; VReg_64:%vreg12,%vreg509
	%vreg11<def> = COPY %vreg532; VReg_64:%vreg11,%vreg532
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg543<def> = COPY %vreg541; VReg_32:%vreg543,%vreg541
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	%vreg451<def> = COPY %vreg13; VReg_32:%vreg451 SReg_32:%vreg13
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg86, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg452<def> = PHI %vreg453, <BB#7>; VReg_32:%vreg452,%vreg453
	%vreg15<def> = PHI %vreg20, <BB#7>; VGPR_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg452, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg452 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg546<def> = COPY %vreg305; VReg_32:%vreg546,%vreg305
	%vreg444<def> = V_ADD_I32_e32 %vreg546<kill>, %vreg442, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg444,%vreg546,%vreg442
	%vreg308<def> = COPY %vreg444; VGPR_32:%vreg308 VReg_32:%vreg444
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg308<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg308
	%vreg547<def> = COPY %vreg309; VReg_32:%vreg547,%vreg309
	%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg547, %EXEC<imp-use>; VReg_32:%vreg548,%vreg547
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg548<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309,%vreg548
	%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
	%vreg550<def> = COPY %vreg312:sub1; VReg_32:%vreg550 VReg_64:%vreg312
	%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg452, %EXEC<imp-use>; VReg_32:%vreg494,%vreg452
	%vreg460<def> = COPY %vreg452; VReg_32:%vreg460,%vreg452
	%vreg461<def> = COPY %vreg494<kill>; VReg_32:%vreg461,%vreg494
	%vreg459<def> = REG_SEQUENCE %vreg460, sub0, %vreg461<kill>, sub1; VReg_64:%vreg459 VReg_32:%vreg460,%vreg461
	%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
	%vreg462<def> = COPY %vreg459:sub1; VReg_32:%vreg462 VReg_64:%vreg459
	%vreg493<def> = V_ADD_I32_e32 %vreg549<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
	%vreg478<def> = COPY %vreg550<kill>; VReg_32:%vreg478,%vreg550
	%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg478, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg477,%vreg462,%vreg478
	%vreg480<def> = COPY %vreg493<kill>; VReg_32:%vreg480,%vreg493
	%vreg481<def> = COPY %vreg477<kill>; VReg_32:%vreg481,%vreg477
	%vreg479<def> = REG_SEQUENCE %vreg480<kill>, sub0, %vreg481<kill>, sub1; VReg_64:%vreg479 VReg_32:%vreg480,%vreg481
	%vreg482<def> = V_LSHL_B64 %vreg479<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
	%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
	%vreg483<def> = COPY %vreg482:sub1; VReg_32:%vreg483 VReg_64:%vreg482
	%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
	%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
	%vreg490<def> = V_ADD_I32_e32 %vreg551<kill>, %vreg489<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
	%vreg485<def> = COPY %vreg552<kill>; VReg_32:%vreg485,%vreg552
	%vreg484<def> = V_ADDC_U32_e32 %vreg485, %vreg483<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg484,%vreg485,%vreg483
	%vreg487<def> = COPY %vreg490<kill>; VReg_32:%vreg487,%vreg490
	%vreg488<def> = COPY %vreg484<kill>; VReg_32:%vreg488,%vreg484
	%vreg486<def> = REG_SEQUENCE %vreg487<kill>, sub0, %vreg488<kill>, sub1; VReg_64:%vreg486 VReg_32:%vreg487,%vreg488
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg553<def> = COPY %vreg331; VReg_32:%vreg553,%vreg331
	%vreg447<def> = V_ADD_I32_e32 %vreg553<kill>, %vreg445, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg447,%vreg553,%vreg445
	%vreg334<def> = COPY %vreg447; VGPR_32:%vreg334 VReg_32:%vreg447
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg334<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg334
	%vreg554<def> = COPY %vreg335; VReg_32:%vreg554,%vreg335
	%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg554, %EXEC<imp-use>; VReg_32:%vreg555,%vreg554
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg555<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335,%vreg555
	%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
	%vreg557<def> = COPY %vreg338:sub1; VReg_32:%vreg557 VReg_64:%vreg338
	%vreg492<def> = V_ADD_I32_e32 %vreg556<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
	%vreg464<def> = COPY %vreg557<kill>; VReg_32:%vreg464,%vreg557
	%vreg463<def> = V_ADDC_U32_e32 %vreg462, %vreg464, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg463,%vreg462,%vreg464
	%vreg466<def> = COPY %vreg492<kill>; VReg_32:%vreg466,%vreg492
	%vreg467<def> = COPY %vreg463<kill>; VReg_32:%vreg467,%vreg463
	%vreg465<def> = REG_SEQUENCE %vreg466<kill>, sub0, %vreg467<kill>, sub1; VReg_64:%vreg465 VReg_32:%vreg466,%vreg467
	%vreg468<def> = V_LSHL_B64 %vreg465<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
	%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
	%vreg469<def> = COPY %vreg468:sub1; VReg_32:%vreg469 VReg_64:%vreg468
	%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
	%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
	%vreg476<def> = V_ADD_I32_e32 %vreg558<kill>, %vreg475<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
	%vreg471<def> = COPY %vreg559<kill>; VReg_32:%vreg471,%vreg559
	%vreg470<def> = V_ADDC_U32_e32 %vreg471, %vreg469<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg470,%vreg471,%vreg469
	%vreg473<def> = COPY %vreg476<kill>; VReg_32:%vreg473,%vreg476
	%vreg474<def> = COPY %vreg470<kill>; VReg_32:%vreg474,%vreg470
	%vreg472<def> = REG_SEQUENCE %vreg473<kill>, sub0, %vreg474<kill>, sub1; VReg_64:%vreg472 VReg_32:%vreg473,%vreg474
	%vreg454<def> = V_SUB_I32_e32 %vreg55, %vreg452, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg454,%vreg452 SReg_32:%vreg55
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
	%vreg19<def> = COPY %vreg486; VReg_64:%vreg19,%vreg486
	%vreg18<def> = COPY %vreg472; VReg_64:%vreg18,%vreg472
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg456<def> = COPY %vreg454; VReg_32:%vreg456,%vreg454
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VGPR_32:%vreg20,%vreg87,%vreg27
	%vreg449<def> = PHI %vreg450, <BB#1>, %vreg451, <BB#3>; VReg_32:%vreg449,%vreg450,%vreg451
	%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	SI_END_CF %vreg92, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92
	%vreg453<def> = COPY %vreg449; VReg_32:%vreg453,%vreg449
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 SGPR_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg815, <BB#8>; VReg_64:%vreg23,%vreg12,%vreg815
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg824, <BB#8>; VReg_64:%vreg24,%vreg11,%vreg824
	%vreg542<def> = PHI %vreg543, <BB#2>, %vreg544, <BB#8>; VReg_32:%vreg542,%vreg543,%vreg544
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VGPR_32:%vreg26,%vreg95,%vreg27
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg147,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183<def> = REG_SEQUENCE %vreg182, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
	%vreg561<def> = COPY %vreg560; VReg_64:%vreg561,%vreg560
	%vreg563<def> = COPY %vreg561; VReg_64:%vreg563,%vreg561
	%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
	%vreg562<def> = REG_SEQUENCE %vreg563, sub0_sub1, %vreg564, sub2_sub3; VReg_128:%vreg562 VReg_64:%vreg563,%vreg564
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
	%vreg678<def> = COPY %vreg677:sub0; VReg_32:%vreg678 VReg_128:%vreg677
	%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
	%vreg680<def> = COPY %vreg679:sub1; VReg_32:%vreg680 VReg_128:%vreg679
	%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
	%vreg682<def> = COPY %vreg681:sub0; VReg_32:%vreg682 VReg_64:%vreg681
	%vreg683<def> = COPY %vreg187; VReg_64:%vreg683,%vreg187
	%vreg684<def> = COPY %vreg683:sub1; VReg_32:%vreg684 VReg_64:%vreg683
	%vreg670<def> = V_ADD_I32_e32 %vreg678, %vreg682, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
	%vreg671<def> = V_ADDC_U32_e32 %vreg680, %vreg684, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
	%vreg672<def> = REG_SEQUENCE %vreg670, sub0, %vreg671, sub1; VReg_64:%vreg672 VReg_32:%vreg670,%vreg671
	%vreg673<def> = S_MOV_B64 0; SReg_64:%vreg673
	%vreg674<def> = S_MOV_B32 0; SGPR_32:%vreg674
	%vreg675<def> = S_MOV_B32 61440; SGPR_32:%vreg675
	%vreg676<def> = REG_SEQUENCE %vreg673, sub0_sub1, %vreg674, sub2, %vreg675, sub3; SReg_128:%vreg676 SReg_64:%vreg673 SGPR_32:%vreg674,%vreg675
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
	%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
	%vreg686<def> = COPY %vreg685; VReg_64:%vreg686,%vreg685
	%vreg688<def> = COPY %vreg686; VReg_64:%vreg688,%vreg686
	%vreg689<def> = COPY %vreg399; VReg_64:%vreg689 SGPR_64:%vreg399
	%vreg687<def> = REG_SEQUENCE %vreg688, sub0_sub1, %vreg689, sub2_sub3; VReg_128:%vreg687 VReg_64:%vreg688,%vreg689
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
	%vreg803<def> = COPY %vreg802:sub0; VReg_32:%vreg803 VReg_128:%vreg802
	%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
	%vreg805<def> = COPY %vreg804:sub1; VReg_32:%vreg805 VReg_128:%vreg804
	%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
	%vreg807<def> = COPY %vreg806:sub0; VReg_32:%vreg807 VReg_64:%vreg806
	%vreg808<def> = COPY %vreg191; VReg_64:%vreg808,%vreg191
	%vreg809<def> = COPY %vreg808:sub1; VReg_32:%vreg809 VReg_64:%vreg808
	%vreg795<def> = V_ADD_I32_e32 %vreg803, %vreg807, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
	%vreg796<def> = V_ADDC_U32_e32 %vreg805, %vreg809, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
	%vreg797<def> = REG_SEQUENCE %vreg795, sub0, %vreg796, sub1; VReg_64:%vreg797 VReg_32:%vreg795,%vreg796
	%vreg798<def> = S_MOV_B64 0; SReg_64:%vreg798
	%vreg799<def> = S_MOV_B32 0; SGPR_32:%vreg799
	%vreg800<def> = S_MOV_B32 61440; SGPR_32:%vreg800
	%vreg801<def> = REG_SEQUENCE %vreg798, sub0_sub1, %vreg799, sub2, %vreg800, sub3; SReg_128:%vreg801 SReg_64:%vreg798 SGPR_32:%vreg799,%vreg800
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg801, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg801 VReg_64:%vreg797
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195<def> = REG_SEQUENCE %vreg194, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
	%vreg663<def> = COPY %vreg662:sub0; VReg_32:%vreg663 VReg_128:%vreg662
	%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
	%vreg665<def> = COPY %vreg664:sub1; VReg_32:%vreg665 VReg_128:%vreg664
	%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
	%vreg667<def> = COPY %vreg666:sub0; VReg_32:%vreg667 VReg_64:%vreg666
	%vreg668<def> = COPY %vreg197; VReg_64:%vreg668,%vreg197
	%vreg669<def> = COPY %vreg668:sub1; VReg_32:%vreg669 VReg_64:%vreg668
	%vreg655<def> = V_ADD_I32_e32 %vreg663, %vreg667, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
	%vreg656<def> = V_ADDC_U32_e32 %vreg665, %vreg669, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
	%vreg657<def> = REG_SEQUENCE %vreg655, sub0, %vreg656, sub1; VReg_64:%vreg657 VReg_32:%vreg655,%vreg656
	%vreg658<def> = S_MOV_B64 0; SReg_64:%vreg658
	%vreg659<def> = S_MOV_B32 0; SGPR_32:%vreg659
	%vreg660<def> = S_MOV_B32 61440; SGPR_32:%vreg660
	%vreg661<def> = REG_SEQUENCE %vreg658, sub0_sub1, %vreg659, sub2, %vreg660, sub3; SReg_128:%vreg661 SReg_64:%vreg658 SGPR_32:%vreg659,%vreg660
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg661, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg661 VReg_64:%vreg657
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
	%vreg788<def> = COPY %vreg787:sub0; VReg_32:%vreg788 VReg_128:%vreg787
	%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
	%vreg790<def> = COPY %vreg789:sub1; VReg_32:%vreg790 VReg_128:%vreg789
	%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
	%vreg792<def> = COPY %vreg791:sub0; VReg_32:%vreg792 VReg_64:%vreg791
	%vreg793<def> = COPY %vreg199; VReg_64:%vreg793,%vreg199
	%vreg794<def> = COPY %vreg793:sub1; VReg_32:%vreg794 VReg_64:%vreg793
	%vreg780<def> = V_ADD_I32_e32 %vreg788, %vreg792, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
	%vreg781<def> = V_ADDC_U32_e32 %vreg790, %vreg794, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
	%vreg782<def> = REG_SEQUENCE %vreg780, sub0, %vreg781, sub1; VReg_64:%vreg782 VReg_32:%vreg780,%vreg781
	%vreg783<def> = S_MOV_B64 0; SReg_64:%vreg783
	%vreg784<def> = S_MOV_B32 0; SGPR_32:%vreg784
	%vreg785<def> = S_MOV_B32 61440; SGPR_32:%vreg785
	%vreg786<def> = REG_SEQUENCE %vreg783, sub0_sub1, %vreg784, sub2, %vreg785, sub3; SReg_128:%vreg786 SReg_64:%vreg783 SGPR_32:%vreg784,%vreg785
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg786, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg786 VReg_64:%vreg782
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203<def> = REG_SEQUENCE %vreg202, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
	%vreg648<def> = COPY %vreg647:sub0; VReg_32:%vreg648 VReg_128:%vreg647
	%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
	%vreg650<def> = COPY %vreg649:sub1; VReg_32:%vreg650 VReg_128:%vreg649
	%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
	%vreg652<def> = COPY %vreg651:sub0; VReg_32:%vreg652 VReg_64:%vreg651
	%vreg653<def> = COPY %vreg205; VReg_64:%vreg653,%vreg205
	%vreg654<def> = COPY %vreg653:sub1; VReg_32:%vreg654 VReg_64:%vreg653
	%vreg640<def> = V_ADD_I32_e32 %vreg648, %vreg652, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
	%vreg641<def> = V_ADDC_U32_e32 %vreg650, %vreg654, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
	%vreg642<def> = REG_SEQUENCE %vreg640, sub0, %vreg641, sub1; VReg_64:%vreg642 VReg_32:%vreg640,%vreg641
	%vreg643<def> = S_MOV_B64 0; SReg_64:%vreg643
	%vreg644<def> = S_MOV_B32 0; SGPR_32:%vreg644
	%vreg645<def> = S_MOV_B32 61440; SGPR_32:%vreg645
	%vreg646<def> = REG_SEQUENCE %vreg643, sub0_sub1, %vreg644, sub2, %vreg645, sub3; SReg_128:%vreg646 SReg_64:%vreg643 SGPR_32:%vreg644,%vreg645
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg646, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg646 VReg_64:%vreg642
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
	%vreg773<def> = COPY %vreg772:sub0; VReg_32:%vreg773 VReg_128:%vreg772
	%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
	%vreg775<def> = COPY %vreg774:sub1; VReg_32:%vreg775 VReg_128:%vreg774
	%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
	%vreg777<def> = COPY %vreg776:sub0; VReg_32:%vreg777 VReg_64:%vreg776
	%vreg778<def> = COPY %vreg207; VReg_64:%vreg778,%vreg207
	%vreg779<def> = COPY %vreg778:sub1; VReg_32:%vreg779 VReg_64:%vreg778
	%vreg765<def> = V_ADD_I32_e32 %vreg773, %vreg777, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
	%vreg766<def> = V_ADDC_U32_e32 %vreg775, %vreg779, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
	%vreg767<def> = REG_SEQUENCE %vreg765, sub0, %vreg766, sub1; VReg_64:%vreg767 VReg_32:%vreg765,%vreg766
	%vreg768<def> = S_MOV_B64 0; SReg_64:%vreg768
	%vreg769<def> = S_MOV_B32 0; SGPR_32:%vreg769
	%vreg770<def> = S_MOV_B32 61440; SGPR_32:%vreg770
	%vreg771<def> = REG_SEQUENCE %vreg768, sub0_sub1, %vreg769, sub2, %vreg770, sub3; SReg_128:%vreg771 SReg_64:%vreg768 SGPR_32:%vreg769,%vreg770
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg771, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg771 VReg_64:%vreg767
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211<def> = REG_SEQUENCE %vreg210, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
	%vreg633<def> = COPY %vreg632:sub0; VReg_32:%vreg633 VReg_128:%vreg632
	%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
	%vreg635<def> = COPY %vreg634:sub1; VReg_32:%vreg635 VReg_128:%vreg634
	%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
	%vreg637<def> = COPY %vreg636:sub0; VReg_32:%vreg637 VReg_64:%vreg636
	%vreg638<def> = COPY %vreg213; VReg_64:%vreg638,%vreg213
	%vreg639<def> = COPY %vreg638:sub1; VReg_32:%vreg639 VReg_64:%vreg638
	%vreg625<def> = V_ADD_I32_e32 %vreg633, %vreg637, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
	%vreg626<def> = V_ADDC_U32_e32 %vreg635, %vreg639, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
	%vreg627<def> = REG_SEQUENCE %vreg625, sub0, %vreg626, sub1; VReg_64:%vreg627 VReg_32:%vreg625,%vreg626
	%vreg628<def> = S_MOV_B64 0; SReg_64:%vreg628
	%vreg629<def> = S_MOV_B32 0; SGPR_32:%vreg629
	%vreg630<def> = S_MOV_B32 61440; SGPR_32:%vreg630
	%vreg631<def> = REG_SEQUENCE %vreg628, sub0_sub1, %vreg629, sub2, %vreg630, sub3; SReg_128:%vreg631 SReg_64:%vreg628 SGPR_32:%vreg629,%vreg630
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg631, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg631 VReg_64:%vreg627
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
	%vreg758<def> = COPY %vreg757:sub0; VReg_32:%vreg758 VReg_128:%vreg757
	%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
	%vreg760<def> = COPY %vreg759:sub1; VReg_32:%vreg760 VReg_128:%vreg759
	%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
	%vreg762<def> = COPY %vreg761:sub0; VReg_32:%vreg762 VReg_64:%vreg761
	%vreg763<def> = COPY %vreg215; VReg_64:%vreg763,%vreg215
	%vreg764<def> = COPY %vreg763:sub1; VReg_32:%vreg764 VReg_64:%vreg763
	%vreg750<def> = V_ADD_I32_e32 %vreg758, %vreg762, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
	%vreg751<def> = V_ADDC_U32_e32 %vreg760, %vreg764, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
	%vreg752<def> = REG_SEQUENCE %vreg750, sub0, %vreg751, sub1; VReg_64:%vreg752 VReg_32:%vreg750,%vreg751
	%vreg753<def> = S_MOV_B64 0; SReg_64:%vreg753
	%vreg754<def> = S_MOV_B32 0; SGPR_32:%vreg754
	%vreg755<def> = S_MOV_B32 61440; SGPR_32:%vreg755
	%vreg756<def> = REG_SEQUENCE %vreg753, sub0_sub1, %vreg754, sub2, %vreg755, sub3; SReg_128:%vreg756 SReg_64:%vreg753 SGPR_32:%vreg754,%vreg755
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg756, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg756 VReg_64:%vreg752
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219<def> = REG_SEQUENCE %vreg218, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
	%vreg618<def> = COPY %vreg617:sub0; VReg_32:%vreg618 VReg_128:%vreg617
	%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
	%vreg620<def> = COPY %vreg619:sub1; VReg_32:%vreg620 VReg_128:%vreg619
	%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
	%vreg622<def> = COPY %vreg621:sub0; VReg_32:%vreg622 VReg_64:%vreg621
	%vreg623<def> = COPY %vreg221; VReg_64:%vreg623,%vreg221
	%vreg624<def> = COPY %vreg623:sub1; VReg_32:%vreg624 VReg_64:%vreg623
	%vreg610<def> = V_ADD_I32_e32 %vreg618, %vreg622, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
	%vreg611<def> = V_ADDC_U32_e32 %vreg620, %vreg624, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
	%vreg612<def> = REG_SEQUENCE %vreg610, sub0, %vreg611, sub1; VReg_64:%vreg612 VReg_32:%vreg610,%vreg611
	%vreg613<def> = S_MOV_B64 0; SReg_64:%vreg613
	%vreg614<def> = S_MOV_B32 0; SGPR_32:%vreg614
	%vreg615<def> = S_MOV_B32 61440; SGPR_32:%vreg615
	%vreg616<def> = REG_SEQUENCE %vreg613, sub0_sub1, %vreg614, sub2, %vreg615, sub3; SReg_128:%vreg616 SReg_64:%vreg613 SGPR_32:%vreg614,%vreg615
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg616, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg616 VReg_64:%vreg612
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
	%vreg743<def> = COPY %vreg742:sub0; VReg_32:%vreg743 VReg_128:%vreg742
	%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
	%vreg745<def> = COPY %vreg744:sub1; VReg_32:%vreg745 VReg_128:%vreg744
	%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
	%vreg747<def> = COPY %vreg746:sub0; VReg_32:%vreg747 VReg_64:%vreg746
	%vreg748<def> = COPY %vreg223; VReg_64:%vreg748,%vreg223
	%vreg749<def> = COPY %vreg748:sub1; VReg_32:%vreg749 VReg_64:%vreg748
	%vreg735<def> = V_ADD_I32_e32 %vreg743, %vreg747, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
	%vreg736<def> = V_ADDC_U32_e32 %vreg745, %vreg749, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
	%vreg737<def> = REG_SEQUENCE %vreg735, sub0, %vreg736, sub1; VReg_64:%vreg737 VReg_32:%vreg735,%vreg736
	%vreg738<def> = S_MOV_B64 0; SReg_64:%vreg738
	%vreg739<def> = S_MOV_B32 0; SGPR_32:%vreg739
	%vreg740<def> = S_MOV_B32 61440; SGPR_32:%vreg740
	%vreg741<def> = REG_SEQUENCE %vreg738, sub0_sub1, %vreg739, sub2, %vreg740, sub3; SReg_128:%vreg741 SReg_64:%vreg738 SGPR_32:%vreg739,%vreg740
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg741, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg741 VReg_64:%vreg737
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227<def> = REG_SEQUENCE %vreg226, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
	%vreg603<def> = COPY %vreg602:sub0; VReg_32:%vreg603 VReg_128:%vreg602
	%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
	%vreg605<def> = COPY %vreg604:sub1; VReg_32:%vreg605 VReg_128:%vreg604
	%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
	%vreg607<def> = COPY %vreg606:sub0; VReg_32:%vreg607 VReg_64:%vreg606
	%vreg608<def> = COPY %vreg229; VReg_64:%vreg608,%vreg229
	%vreg609<def> = COPY %vreg608:sub1; VReg_32:%vreg609 VReg_64:%vreg608
	%vreg595<def> = V_ADD_I32_e32 %vreg603, %vreg607, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
	%vreg596<def> = V_ADDC_U32_e32 %vreg605, %vreg609, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
	%vreg597<def> = REG_SEQUENCE %vreg595, sub0, %vreg596, sub1; VReg_64:%vreg597 VReg_32:%vreg595,%vreg596
	%vreg598<def> = S_MOV_B64 0; SReg_64:%vreg598
	%vreg599<def> = S_MOV_B32 0; SGPR_32:%vreg599
	%vreg600<def> = S_MOV_B32 61440; SGPR_32:%vreg600
	%vreg601<def> = REG_SEQUENCE %vreg598, sub0_sub1, %vreg599, sub2, %vreg600, sub3; SReg_128:%vreg601 SReg_64:%vreg598 SGPR_32:%vreg599,%vreg600
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg601, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg601 VReg_64:%vreg597
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
	%vreg728<def> = COPY %vreg727:sub0; VReg_32:%vreg728 VReg_128:%vreg727
	%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
	%vreg730<def> = COPY %vreg729:sub1; VReg_32:%vreg730 VReg_128:%vreg729
	%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
	%vreg732<def> = COPY %vreg731:sub0; VReg_32:%vreg732 VReg_64:%vreg731
	%vreg733<def> = COPY %vreg231; VReg_64:%vreg733,%vreg231
	%vreg734<def> = COPY %vreg733:sub1; VReg_32:%vreg734 VReg_64:%vreg733
	%vreg720<def> = V_ADD_I32_e32 %vreg728, %vreg732, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
	%vreg721<def> = V_ADDC_U32_e32 %vreg730, %vreg734, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
	%vreg722<def> = REG_SEQUENCE %vreg720, sub0, %vreg721, sub1; VReg_64:%vreg722 VReg_32:%vreg720,%vreg721
	%vreg723<def> = S_MOV_B64 0; SReg_64:%vreg723
	%vreg724<def> = S_MOV_B32 0; SGPR_32:%vreg724
	%vreg725<def> = S_MOV_B32 61440; SGPR_32:%vreg725
	%vreg726<def> = REG_SEQUENCE %vreg723, sub0_sub1, %vreg724, sub2, %vreg725, sub3; SReg_128:%vreg726 SReg_64:%vreg723 SGPR_32:%vreg724,%vreg725
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg726, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg726 VReg_64:%vreg722
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235<def> = REG_SEQUENCE %vreg234, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
	%vreg588<def> = COPY %vreg587:sub0; VReg_32:%vreg588 VReg_128:%vreg587
	%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
	%vreg590<def> = COPY %vreg589:sub1; VReg_32:%vreg590 VReg_128:%vreg589
	%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
	%vreg592<def> = COPY %vreg591:sub0; VReg_32:%vreg592 VReg_64:%vreg591
	%vreg593<def> = COPY %vreg237; VReg_64:%vreg593,%vreg237
	%vreg594<def> = COPY %vreg593:sub1; VReg_32:%vreg594 VReg_64:%vreg593
	%vreg580<def> = V_ADD_I32_e32 %vreg588, %vreg592, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
	%vreg581<def> = V_ADDC_U32_e32 %vreg590, %vreg594, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
	%vreg582<def> = REG_SEQUENCE %vreg580, sub0, %vreg581, sub1; VReg_64:%vreg582 VReg_32:%vreg580,%vreg581
	%vreg583<def> = S_MOV_B64 0; SReg_64:%vreg583
	%vreg584<def> = S_MOV_B32 0; SGPR_32:%vreg584
	%vreg585<def> = S_MOV_B32 61440; SGPR_32:%vreg585
	%vreg586<def> = REG_SEQUENCE %vreg583, sub0_sub1, %vreg584, sub2, %vreg585, sub3; SReg_128:%vreg586 SReg_64:%vreg583 SGPR_32:%vreg584,%vreg585
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg586, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg586 VReg_64:%vreg582
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
	%vreg713<def> = COPY %vreg712:sub0; VReg_32:%vreg713 VReg_128:%vreg712
	%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
	%vreg715<def> = COPY %vreg714:sub1; VReg_32:%vreg715 VReg_128:%vreg714
	%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
	%vreg717<def> = COPY %vreg716:sub0; VReg_32:%vreg717 VReg_64:%vreg716
	%vreg718<def> = COPY %vreg239; VReg_64:%vreg718,%vreg239
	%vreg719<def> = COPY %vreg718:sub1; VReg_32:%vreg719 VReg_64:%vreg718
	%vreg705<def> = V_ADD_I32_e32 %vreg713, %vreg717, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
	%vreg706<def> = V_ADDC_U32_e32 %vreg715, %vreg719, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
	%vreg707<def> = REG_SEQUENCE %vreg705, sub0, %vreg706, sub1; VReg_64:%vreg707 VReg_32:%vreg705,%vreg706
	%vreg708<def> = S_MOV_B64 0; SReg_64:%vreg708
	%vreg709<def> = S_MOV_B32 0; SGPR_32:%vreg709
	%vreg710<def> = S_MOV_B32 61440; SGPR_32:%vreg710
	%vreg711<def> = REG_SEQUENCE %vreg708, sub0_sub1, %vreg709, sub2, %vreg710, sub3; SReg_128:%vreg711 SReg_64:%vreg708 SGPR_32:%vreg709,%vreg710
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg711, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg711 VReg_64:%vreg707
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243<def> = REG_SEQUENCE %vreg242, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
	%vreg573<def> = COPY %vreg572:sub0; VReg_32:%vreg573 VReg_128:%vreg572
	%vreg574<def> = COPY %vreg562; VReg_128:%vreg574,%vreg562
	%vreg575<def> = COPY %vreg574:sub1; VReg_32:%vreg575 VReg_128:%vreg574
	%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
	%vreg577<def> = COPY %vreg576:sub0; VReg_32:%vreg577 VReg_64:%vreg576
	%vreg578<def> = COPY %vreg245; VReg_64:%vreg578,%vreg245
	%vreg579<def> = COPY %vreg578:sub1; VReg_32:%vreg579 VReg_64:%vreg578
	%vreg565<def> = V_ADD_I32_e32 %vreg573, %vreg577, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
	%vreg566<def> = V_ADDC_U32_e32 %vreg575, %vreg579, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
	%vreg567<def> = REG_SEQUENCE %vreg565, sub0, %vreg566, sub1; VReg_64:%vreg567 VReg_32:%vreg565,%vreg566
	%vreg568<def> = S_MOV_B64 0; SReg_64:%vreg568
	%vreg569<def> = S_MOV_B32 0; SGPR_32:%vreg569
	%vreg570<def> = S_MOV_B32 61440; SGPR_32:%vreg570
	%vreg571<def> = REG_SEQUENCE %vreg568, sub0_sub1, %vreg569, sub2, %vreg570, sub3; SReg_128:%vreg571 SReg_64:%vreg568 SGPR_32:%vreg569,%vreg570
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg571, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg571 VReg_64:%vreg567
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
	%vreg698<def> = COPY %vreg697:sub0; VReg_32:%vreg698 VReg_128:%vreg697
	%vreg699<def> = COPY %vreg687; VReg_128:%vreg699,%vreg687
	%vreg700<def> = COPY %vreg699:sub1; VReg_32:%vreg700 VReg_128:%vreg699
	%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
	%vreg702<def> = COPY %vreg701:sub0; VReg_32:%vreg702 VReg_64:%vreg701
	%vreg703<def> = COPY %vreg247; VReg_64:%vreg703,%vreg247
	%vreg704<def> = COPY %vreg703:sub1; VReg_32:%vreg704 VReg_64:%vreg703
	%vreg690<def> = V_ADD_I32_e32 %vreg698, %vreg702, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
	%vreg691<def> = V_ADDC_U32_e32 %vreg700, %vreg704, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
	%vreg692<def> = REG_SEQUENCE %vreg690, sub0, %vreg691, sub1; VReg_64:%vreg692 VReg_32:%vreg690,%vreg691
	%vreg693<def> = S_MOV_B64 0; SReg_64:%vreg693
	%vreg694<def> = S_MOV_B32 0; SGPR_32:%vreg694
	%vreg695<def> = S_MOV_B32 61440; SGPR_32:%vreg695
	%vreg696<def> = REG_SEQUENCE %vreg693, sub0_sub1, %vreg694, sub2, %vreg695, sub3; SReg_128:%vreg696 SReg_64:%vreg693 SGPR_32:%vreg694,%vreg695
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg696, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg696 VReg_64:%vreg692
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg816<def> = COPY %vreg23:sub1; VReg_32:%vreg816 VReg_64:%vreg23
	%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
	%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
	%vreg817<def> = V_ADDC_U32_e32 %vreg816<kill>, %vreg818, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg817,%vreg816,%vreg818
	%vreg813<def> = COPY %vreg811<kill>; VReg_32:%vreg813,%vreg811
	%vreg814<def> = COPY %vreg817<kill>; VReg_32:%vreg814,%vreg817
	%vreg812<def> = REG_SEQUENCE %vreg813<kill>, sub0, %vreg814<kill>, sub1; VReg_64:%vreg812 VReg_32:%vreg813,%vreg814
	%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
	%vreg825<def> = COPY %vreg24:sub1; VReg_32:%vreg825 VReg_64:%vreg24
	%vreg820<def> = V_ADD_I32_e32 %vreg284, %vreg819<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
	%vreg827<def> = COPY %vreg286; VReg_32:%vreg827 SReg_32:%vreg286
	%vreg826<def> = V_ADDC_U32_e32 %vreg825<kill>, %vreg827, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg826,%vreg825,%vreg827
	%vreg822<def> = COPY %vreg820<kill>; VReg_32:%vreg822,%vreg820
	%vreg823<def> = COPY %vreg826<kill>; VReg_32:%vreg823,%vreg826
	%vreg821<def> = REG_SEQUENCE %vreg822<kill>, sub0, %vreg823<kill>, sub1; VReg_64:%vreg821 VReg_32:%vreg822,%vreg823
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg545<def> = V_ADD_I32_e32 16, %vreg542, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg545,%vreg542
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg815<def> = COPY %vreg812; VReg_64:%vreg815,%vreg812
	%vreg824<def> = COPY %vreg821; VReg_64:%vreg824,%vreg821
	%vreg27<def> = COPY %vreg282; VGPR_32:%vreg27,%vreg282
	%vreg544<def> = COPY %vreg545; VReg_32:%vreg544,%vreg545
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VGPR_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg302, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 SGPR_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg833, <BB#10>; VReg_64:%vreg34,%vreg19,%vreg833
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg842, <BB#10>; VReg_64:%vreg35,%vreg18,%vreg842
	%vreg455<def> = PHI %vreg456, <BB#6>, %vreg457, <BB#10>; VReg_32:%vreg455,%vreg456,%vreg457
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VGPR_32:%vreg37,%vreg15,%vreg38
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
	%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
	%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
	%vreg835<def> = V_ADDC_U32_e32 %vreg834<kill>, %vreg836, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg835,%vreg834,%vreg836
	%vreg831<def> = COPY %vreg829<kill>; VReg_32:%vreg831,%vreg829
	%vreg832<def> = COPY %vreg835<kill>; VReg_32:%vreg832,%vreg835
	%vreg830<def> = REG_SEQUENCE %vreg831<kill>, sub0, %vreg832<kill>, sub1; VReg_64:%vreg830 VReg_32:%vreg831,%vreg832
	%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
	%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
	%vreg838<def> = V_ADD_I32_e32 %vreg354, %vreg837<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
	%vreg845<def> = COPY %vreg356; VReg_32:%vreg845 SReg_32:%vreg356
	%vreg844<def> = V_ADDC_U32_e32 %vreg843<kill>, %vreg845, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg844,%vreg843,%vreg845
	%vreg840<def> = COPY %vreg838<kill>; VReg_32:%vreg840,%vreg838
	%vreg841<def> = COPY %vreg844<kill>; VReg_32:%vreg841,%vreg844
	%vreg839<def> = REG_SEQUENCE %vreg840<kill>, sub0, %vreg841<kill>, sub1; VReg_64:%vreg839 VReg_32:%vreg840,%vreg841
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg352, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg352,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
	%vreg458<def> = V_ADD_I32_e32 -1, %vreg455, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg458,%vreg455
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg833<def> = COPY %vreg830; VReg_64:%vreg833,%vreg830
	%vreg842<def> = COPY %vreg839; VReg_64:%vreg842,%vreg839
	%vreg38<def> = COPY %vreg370; VGPR_32:%vreg38,%vreg370
	%vreg457<def> = COPY %vreg458; VReg_32:%vreg457,%vreg458
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VGPR_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
	%vreg846<def> = COPY %vreg374; VReg_32:%vreg846,%vreg374
	%vreg424<def> = V_ADD_I32_e32 %vreg846<kill>, %vreg423, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg424,%vreg846,%vreg423
	%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
	%vreg426<def> = COPY %vreg424; VReg_32:%vreg426,%vreg424
	%vreg427<def> = COPY %vreg437<kill>; VReg_32:%vreg427,%vreg437
	%vreg425<def> = REG_SEQUENCE %vreg426, sub0, %vreg427<kill>, sub1; VReg_64:%vreg425 VReg_32:%vreg426,%vreg427
	%vreg428<def> = V_LSHL_B64 %vreg425<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
	%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
	%vreg429<def> = COPY %vreg428:sub1; VReg_32:%vreg429 VReg_64:%vreg428
	%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
	%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
	%vreg436<def> = V_ADD_I32_e32 %vreg847<kill>, %vreg435<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
	%vreg431<def> = COPY %vreg848<kill>; VReg_32:%vreg431,%vreg848
	%vreg430<def> = V_ADDC_U32_e32 %vreg431, %vreg429<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg430,%vreg431,%vreg429
	%vreg433<def> = COPY %vreg436<kill>; VReg_32:%vreg433,%vreg436
	%vreg434<def> = COPY %vreg430<kill>; VReg_32:%vreg434,%vreg430
	%vreg432<def> = REG_SEQUENCE %vreg433<kill>, sub0, %vreg434<kill>, sub1; VReg_64:%vreg432 VReg_32:%vreg433,%vreg434
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg43,%vreg56
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg45<def> = COPY %vreg432; VReg_64:%vreg45,%vreg432
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg393<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg393
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg395, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Process Implicit Definitions ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg59, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg423,%vreg63,%vreg59
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg57, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg440,%vreg71,%vreg57
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg442<def> = COPY %vreg57; VReg_32:%vreg442,%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg445<def> = COPY %vreg59; VReg_32:%vreg445,%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg448<def> = COPY %vreg90; VReg_32:%vreg448,%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VGPR_32:%vreg87,%vreg91
	%vreg450<def> = COPY %vreg448; VReg_32:%vreg450,%vreg448
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg443
	%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg101, %EXEC<imp-use>; VReg_32:%vreg497,%vreg101
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg497<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101,%vreg497
	%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
	%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
	%vreg500<def> = COPY %vreg499:sub1; VReg_32:%vreg500 VReg_64:%vreg499
	%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
	%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
	%vreg515<def> = V_ADD_I32_e32 %vreg516<kill>, %vreg514<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
	%vreg501<def> = V_ADDC_U32_e32 %vreg500<kill>, %vreg517, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg501,%vreg500,%vreg517
	%vreg503<def> = REG_SEQUENCE %vreg515, sub0, %vreg501, sub1; VReg_64:%vreg503 VReg_32:%vreg515,%vreg501
	%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
	%vreg506<def> = COPY %vreg503:sub1; VReg_32:%vreg506 VReg_64:%vreg503
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
	%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
	%vreg507<def> = V_ADDC_U32_e32 %vreg506<kill>, %vreg508, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg507,%vreg506,%vreg508
	%vreg509<def> = REG_SEQUENCE %vreg513, sub0, %vreg507, sub1; VReg_64:%vreg509 VReg_32:%vreg513,%vreg507
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg446
	%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg127, %EXEC<imp-use>; VReg_32:%vreg520,%vreg127
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg520<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127,%vreg520
	%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
	%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
	%vreg523<def> = COPY %vreg522:sub1; VReg_32:%vreg523 VReg_64:%vreg522
	%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
	%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
	%vreg538<def> = V_ADD_I32_e32 %vreg539<kill>, %vreg537<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
	%vreg524<def> = V_ADDC_U32_e32 %vreg523<kill>, %vreg540, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg524,%vreg523,%vreg540
	%vreg526<def> = REG_SEQUENCE %vreg538, sub0, %vreg524, sub1; VReg_64:%vreg526 VReg_32:%vreg538,%vreg524
	%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
	%vreg529<def> = COPY %vreg526:sub1; VReg_32:%vreg529 VReg_64:%vreg526
	%vreg536<def> = V_ADD_I32_e32 %vreg117, %vreg535<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
	%vreg531<def> = COPY %vreg118; VReg_32:%vreg531 SReg_32:%vreg118
	%vreg530<def> = V_ADDC_U32_e32 %vreg529<kill>, %vreg531, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg530,%vreg529,%vreg531
	%vreg532<def> = REG_SEQUENCE %vreg536, sub0, %vreg530, sub1; VReg_64:%vreg532 VReg_32:%vreg536,%vreg530
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VGPR_32:%vreg95,%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg541<def> = COPY %vreg146; VReg_32:%vreg541,%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
	%vreg12<def> = COPY %vreg509; VReg_64:%vreg12,%vreg509
	%vreg11<def> = COPY %vreg532; VReg_64:%vreg11,%vreg532
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg543<def> = COPY %vreg541; VReg_32:%vreg543,%vreg541
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	%vreg451<def> = COPY %vreg13; VReg_32:%vreg451 SReg_32:%vreg13
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg86, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg452<def> = PHI %vreg453, <BB#7>; VReg_32:%vreg452,%vreg453
	%vreg15<def> = PHI %vreg20, <BB#7>; VGPR_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg452, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg452 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg444
	%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg309, %EXEC<imp-use>; VReg_32:%vreg548,%vreg309
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg548<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309,%vreg548
	%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
	%vreg550<def> = COPY %vreg312:sub1; VReg_32:%vreg550 VReg_64:%vreg312
	%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg452, %EXEC<imp-use>; VReg_32:%vreg494,%vreg452
	%vreg459<def> = REG_SEQUENCE %vreg452, sub0, %vreg494, sub1; VReg_64:%vreg459 VReg_32:%vreg452,%vreg494
	%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
	%vreg462<def> = COPY %vreg459:sub1; VReg_32:%vreg462 VReg_64:%vreg459
	%vreg493<def> = V_ADD_I32_e32 %vreg549<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
	%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg550, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg477,%vreg462,%vreg550
	%vreg479<def> = REG_SEQUENCE %vreg493, sub0, %vreg477, sub1; VReg_64:%vreg479 VReg_32:%vreg493,%vreg477
	%vreg482<def> = V_LSHL_B64 %vreg479<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
	%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
	%vreg483<def> = COPY %vreg482:sub1; VReg_32:%vreg483 VReg_64:%vreg482
	%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
	%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
	%vreg490<def> = V_ADD_I32_e32 %vreg551<kill>, %vreg489<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
	%vreg484<def> = V_ADDC_U32_e32 %vreg552, %vreg483<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg484,%vreg552,%vreg483
	%vreg486<def> = REG_SEQUENCE %vreg490, sub0, %vreg484, sub1; VReg_64:%vreg486 VReg_32:%vreg490,%vreg484
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg447
	%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg335, %EXEC<imp-use>; VReg_32:%vreg555,%vreg335
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg555<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335,%vreg555
	%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
	%vreg557<def> = COPY %vreg338:sub1; VReg_32:%vreg557 VReg_64:%vreg338
	%vreg492<def> = V_ADD_I32_e32 %vreg556<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
	%vreg463<def> = V_ADDC_U32_e32 %vreg462, %vreg557, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg463,%vreg462,%vreg557
	%vreg465<def> = REG_SEQUENCE %vreg492, sub0, %vreg463, sub1; VReg_64:%vreg465 VReg_32:%vreg492,%vreg463
	%vreg468<def> = V_LSHL_B64 %vreg465<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
	%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
	%vreg469<def> = COPY %vreg468:sub1; VReg_32:%vreg469 VReg_64:%vreg468
	%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
	%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
	%vreg476<def> = V_ADD_I32_e32 %vreg558<kill>, %vreg475<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
	%vreg470<def> = V_ADDC_U32_e32 %vreg559, %vreg469<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg470,%vreg559,%vreg469
	%vreg472<def> = REG_SEQUENCE %vreg476, sub0, %vreg470, sub1; VReg_64:%vreg472 VReg_32:%vreg476,%vreg470
	%vreg454<def> = V_SUB_I32_e32 %vreg55, %vreg452, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg454,%vreg452 SReg_32:%vreg55
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
	%vreg19<def> = COPY %vreg486; VReg_64:%vreg19,%vreg486
	%vreg18<def> = COPY %vreg472; VReg_64:%vreg18,%vreg472
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg456<def> = COPY %vreg454; VReg_32:%vreg456,%vreg454
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VGPR_32:%vreg20,%vreg87,%vreg27
	%vreg449<def> = PHI %vreg450, <BB#1>, %vreg451, <BB#3>; VReg_32:%vreg449,%vreg450,%vreg451
	%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	SI_END_CF %vreg92, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92
	%vreg453<def> = COPY %vreg449; VReg_32:%vreg453,%vreg449
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 SGPR_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg815, <BB#8>; VReg_64:%vreg23,%vreg12,%vreg815
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg824, <BB#8>; VReg_64:%vreg24,%vreg11,%vreg824
	%vreg542<def> = PHI %vreg543, <BB#2>, %vreg544, <BB#8>; VReg_32:%vreg542,%vreg543,%vreg544
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VGPR_32:%vreg26,%vreg95,%vreg27
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg147,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183<def> = REG_SEQUENCE %vreg182, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
	%vreg561<def> = COPY %vreg560; VReg_64:%vreg561,%vreg560
	%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
	%vreg562<def> = REG_SEQUENCE %vreg561, sub0_sub1, %vreg564, sub2_sub3; VReg_128:%vreg562 VReg_64:%vreg561,%vreg564
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
	%vreg678<def> = COPY %vreg677:sub0; VReg_32:%vreg678 VReg_128:%vreg677
	%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
	%vreg680<def> = COPY %vreg679:sub1; VReg_32:%vreg680 VReg_128:%vreg679
	%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
	%vreg682<def> = COPY %vreg681:sub0; VReg_32:%vreg682 VReg_64:%vreg681
	%vreg683<def> = COPY %vreg187; VReg_64:%vreg683,%vreg187
	%vreg684<def> = COPY %vreg683:sub1; VReg_32:%vreg684 VReg_64:%vreg683
	%vreg670<def> = V_ADD_I32_e32 %vreg678, %vreg682, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
	%vreg671<def> = V_ADDC_U32_e32 %vreg680, %vreg684, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
	%vreg672<def> = REG_SEQUENCE %vreg670, sub0, %vreg671, sub1; VReg_64:%vreg672 VReg_32:%vreg670,%vreg671
	%vreg676<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg401, sub2, %vreg400, sub3; SReg_128:%vreg676 SGPR_64:%vreg147 SGPR_32:%vreg401,%vreg400
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
	%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
	%vreg686<def> = COPY %vreg685; VReg_64:%vreg686,%vreg685
	%vreg689<def> = COPY %vreg399; VReg_64:%vreg689 SGPR_64:%vreg399
	%vreg687<def> = REG_SEQUENCE %vreg686, sub0_sub1, %vreg689, sub2_sub3; VReg_128:%vreg687 VReg_64:%vreg686,%vreg689
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
	%vreg803<def> = COPY %vreg802:sub0; VReg_32:%vreg803 VReg_128:%vreg802
	%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
	%vreg805<def> = COPY %vreg804:sub1; VReg_32:%vreg805 VReg_128:%vreg804
	%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
	%vreg807<def> = COPY %vreg806:sub0; VReg_32:%vreg807 VReg_64:%vreg806
	%vreg808<def> = COPY %vreg191; VReg_64:%vreg808,%vreg191
	%vreg809<def> = COPY %vreg808:sub1; VReg_32:%vreg809 VReg_64:%vreg808
	%vreg795<def> = V_ADD_I32_e32 %vreg803, %vreg807, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
	%vreg796<def> = V_ADDC_U32_e32 %vreg805, %vreg809, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
	%vreg797<def> = REG_SEQUENCE %vreg795, sub0, %vreg796, sub1; VReg_64:%vreg797 VReg_32:%vreg795,%vreg796
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195<def> = REG_SEQUENCE %vreg194, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
	%vreg663<def> = COPY %vreg662:sub0; VReg_32:%vreg663 VReg_128:%vreg662
	%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
	%vreg665<def> = COPY %vreg664:sub1; VReg_32:%vreg665 VReg_128:%vreg664
	%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
	%vreg667<def> = COPY %vreg666:sub0; VReg_32:%vreg667 VReg_64:%vreg666
	%vreg668<def> = COPY %vreg197; VReg_64:%vreg668,%vreg197
	%vreg669<def> = COPY %vreg668:sub1; VReg_32:%vreg669 VReg_64:%vreg668
	%vreg655<def> = V_ADD_I32_e32 %vreg663, %vreg667, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
	%vreg656<def> = V_ADDC_U32_e32 %vreg665, %vreg669, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
	%vreg657<def> = REG_SEQUENCE %vreg655, sub0, %vreg656, sub1; VReg_64:%vreg657 VReg_32:%vreg655,%vreg656
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
	%vreg788<def> = COPY %vreg787:sub0; VReg_32:%vreg788 VReg_128:%vreg787
	%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
	%vreg790<def> = COPY %vreg789:sub1; VReg_32:%vreg790 VReg_128:%vreg789
	%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
	%vreg792<def> = COPY %vreg791:sub0; VReg_32:%vreg792 VReg_64:%vreg791
	%vreg793<def> = COPY %vreg199; VReg_64:%vreg793,%vreg199
	%vreg794<def> = COPY %vreg793:sub1; VReg_32:%vreg794 VReg_64:%vreg793
	%vreg780<def> = V_ADD_I32_e32 %vreg788, %vreg792, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
	%vreg781<def> = V_ADDC_U32_e32 %vreg790, %vreg794, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
	%vreg782<def> = REG_SEQUENCE %vreg780, sub0, %vreg781, sub1; VReg_64:%vreg782 VReg_32:%vreg780,%vreg781
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203<def> = REG_SEQUENCE %vreg202, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
	%vreg648<def> = COPY %vreg647:sub0; VReg_32:%vreg648 VReg_128:%vreg647
	%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
	%vreg650<def> = COPY %vreg649:sub1; VReg_32:%vreg650 VReg_128:%vreg649
	%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
	%vreg652<def> = COPY %vreg651:sub0; VReg_32:%vreg652 VReg_64:%vreg651
	%vreg653<def> = COPY %vreg205; VReg_64:%vreg653,%vreg205
	%vreg654<def> = COPY %vreg653:sub1; VReg_32:%vreg654 VReg_64:%vreg653
	%vreg640<def> = V_ADD_I32_e32 %vreg648, %vreg652, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
	%vreg641<def> = V_ADDC_U32_e32 %vreg650, %vreg654, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
	%vreg642<def> = REG_SEQUENCE %vreg640, sub0, %vreg641, sub1; VReg_64:%vreg642 VReg_32:%vreg640,%vreg641
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
	%vreg773<def> = COPY %vreg772:sub0; VReg_32:%vreg773 VReg_128:%vreg772
	%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
	%vreg775<def> = COPY %vreg774:sub1; VReg_32:%vreg775 VReg_128:%vreg774
	%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
	%vreg777<def> = COPY %vreg776:sub0; VReg_32:%vreg777 VReg_64:%vreg776
	%vreg778<def> = COPY %vreg207; VReg_64:%vreg778,%vreg207
	%vreg779<def> = COPY %vreg778:sub1; VReg_32:%vreg779 VReg_64:%vreg778
	%vreg765<def> = V_ADD_I32_e32 %vreg773, %vreg777, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
	%vreg766<def> = V_ADDC_U32_e32 %vreg775, %vreg779, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
	%vreg767<def> = REG_SEQUENCE %vreg765, sub0, %vreg766, sub1; VReg_64:%vreg767 VReg_32:%vreg765,%vreg766
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211<def> = REG_SEQUENCE %vreg210, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
	%vreg633<def> = COPY %vreg632:sub0; VReg_32:%vreg633 VReg_128:%vreg632
	%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
	%vreg635<def> = COPY %vreg634:sub1; VReg_32:%vreg635 VReg_128:%vreg634
	%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
	%vreg637<def> = COPY %vreg636:sub0; VReg_32:%vreg637 VReg_64:%vreg636
	%vreg638<def> = COPY %vreg213; VReg_64:%vreg638,%vreg213
	%vreg639<def> = COPY %vreg638:sub1; VReg_32:%vreg639 VReg_64:%vreg638
	%vreg625<def> = V_ADD_I32_e32 %vreg633, %vreg637, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
	%vreg626<def> = V_ADDC_U32_e32 %vreg635, %vreg639, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
	%vreg627<def> = REG_SEQUENCE %vreg625, sub0, %vreg626, sub1; VReg_64:%vreg627 VReg_32:%vreg625,%vreg626
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
	%vreg758<def> = COPY %vreg757:sub0; VReg_32:%vreg758 VReg_128:%vreg757
	%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
	%vreg760<def> = COPY %vreg759:sub1; VReg_32:%vreg760 VReg_128:%vreg759
	%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
	%vreg762<def> = COPY %vreg761:sub0; VReg_32:%vreg762 VReg_64:%vreg761
	%vreg763<def> = COPY %vreg215; VReg_64:%vreg763,%vreg215
	%vreg764<def> = COPY %vreg763:sub1; VReg_32:%vreg764 VReg_64:%vreg763
	%vreg750<def> = V_ADD_I32_e32 %vreg758, %vreg762, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
	%vreg751<def> = V_ADDC_U32_e32 %vreg760, %vreg764, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
	%vreg752<def> = REG_SEQUENCE %vreg750, sub0, %vreg751, sub1; VReg_64:%vreg752 VReg_32:%vreg750,%vreg751
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219<def> = REG_SEQUENCE %vreg218, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
	%vreg618<def> = COPY %vreg617:sub0; VReg_32:%vreg618 VReg_128:%vreg617
	%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
	%vreg620<def> = COPY %vreg619:sub1; VReg_32:%vreg620 VReg_128:%vreg619
	%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
	%vreg622<def> = COPY %vreg621:sub0; VReg_32:%vreg622 VReg_64:%vreg621
	%vreg623<def> = COPY %vreg221; VReg_64:%vreg623,%vreg221
	%vreg624<def> = COPY %vreg623:sub1; VReg_32:%vreg624 VReg_64:%vreg623
	%vreg610<def> = V_ADD_I32_e32 %vreg618, %vreg622, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
	%vreg611<def> = V_ADDC_U32_e32 %vreg620, %vreg624, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
	%vreg612<def> = REG_SEQUENCE %vreg610, sub0, %vreg611, sub1; VReg_64:%vreg612 VReg_32:%vreg610,%vreg611
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
	%vreg743<def> = COPY %vreg742:sub0; VReg_32:%vreg743 VReg_128:%vreg742
	%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
	%vreg745<def> = COPY %vreg744:sub1; VReg_32:%vreg745 VReg_128:%vreg744
	%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
	%vreg747<def> = COPY %vreg746:sub0; VReg_32:%vreg747 VReg_64:%vreg746
	%vreg748<def> = COPY %vreg223; VReg_64:%vreg748,%vreg223
	%vreg749<def> = COPY %vreg748:sub1; VReg_32:%vreg749 VReg_64:%vreg748
	%vreg735<def> = V_ADD_I32_e32 %vreg743, %vreg747, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
	%vreg736<def> = V_ADDC_U32_e32 %vreg745, %vreg749, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
	%vreg737<def> = REG_SEQUENCE %vreg735, sub0, %vreg736, sub1; VReg_64:%vreg737 VReg_32:%vreg735,%vreg736
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227<def> = REG_SEQUENCE %vreg226, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
	%vreg603<def> = COPY %vreg602:sub0; VReg_32:%vreg603 VReg_128:%vreg602
	%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
	%vreg605<def> = COPY %vreg604:sub1; VReg_32:%vreg605 VReg_128:%vreg604
	%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
	%vreg607<def> = COPY %vreg606:sub0; VReg_32:%vreg607 VReg_64:%vreg606
	%vreg608<def> = COPY %vreg229; VReg_64:%vreg608,%vreg229
	%vreg609<def> = COPY %vreg608:sub1; VReg_32:%vreg609 VReg_64:%vreg608
	%vreg595<def> = V_ADD_I32_e32 %vreg603, %vreg607, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
	%vreg596<def> = V_ADDC_U32_e32 %vreg605, %vreg609, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
	%vreg597<def> = REG_SEQUENCE %vreg595, sub0, %vreg596, sub1; VReg_64:%vreg597 VReg_32:%vreg595,%vreg596
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
	%vreg728<def> = COPY %vreg727:sub0; VReg_32:%vreg728 VReg_128:%vreg727
	%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
	%vreg730<def> = COPY %vreg729:sub1; VReg_32:%vreg730 VReg_128:%vreg729
	%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
	%vreg732<def> = COPY %vreg731:sub0; VReg_32:%vreg732 VReg_64:%vreg731
	%vreg733<def> = COPY %vreg231; VReg_64:%vreg733,%vreg231
	%vreg734<def> = COPY %vreg733:sub1; VReg_32:%vreg734 VReg_64:%vreg733
	%vreg720<def> = V_ADD_I32_e32 %vreg728, %vreg732, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
	%vreg721<def> = V_ADDC_U32_e32 %vreg730, %vreg734, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
	%vreg722<def> = REG_SEQUENCE %vreg720, sub0, %vreg721, sub1; VReg_64:%vreg722 VReg_32:%vreg720,%vreg721
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235<def> = REG_SEQUENCE %vreg234, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
	%vreg588<def> = COPY %vreg587:sub0; VReg_32:%vreg588 VReg_128:%vreg587
	%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
	%vreg590<def> = COPY %vreg589:sub1; VReg_32:%vreg590 VReg_128:%vreg589
	%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
	%vreg592<def> = COPY %vreg591:sub0; VReg_32:%vreg592 VReg_64:%vreg591
	%vreg593<def> = COPY %vreg237; VReg_64:%vreg593,%vreg237
	%vreg594<def> = COPY %vreg593:sub1; VReg_32:%vreg594 VReg_64:%vreg593
	%vreg580<def> = V_ADD_I32_e32 %vreg588, %vreg592, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
	%vreg581<def> = V_ADDC_U32_e32 %vreg590, %vreg594, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
	%vreg582<def> = REG_SEQUENCE %vreg580, sub0, %vreg581, sub1; VReg_64:%vreg582 VReg_32:%vreg580,%vreg581
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
	%vreg713<def> = COPY %vreg712:sub0; VReg_32:%vreg713 VReg_128:%vreg712
	%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
	%vreg715<def> = COPY %vreg714:sub1; VReg_32:%vreg715 VReg_128:%vreg714
	%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
	%vreg717<def> = COPY %vreg716:sub0; VReg_32:%vreg717 VReg_64:%vreg716
	%vreg718<def> = COPY %vreg239; VReg_64:%vreg718,%vreg239
	%vreg719<def> = COPY %vreg718:sub1; VReg_32:%vreg719 VReg_64:%vreg718
	%vreg705<def> = V_ADD_I32_e32 %vreg713, %vreg717, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
	%vreg706<def> = V_ADDC_U32_e32 %vreg715, %vreg719, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
	%vreg707<def> = REG_SEQUENCE %vreg705, sub0, %vreg706, sub1; VReg_64:%vreg707 VReg_32:%vreg705,%vreg706
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243<def> = REG_SEQUENCE %vreg242, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
	%vreg573<def> = COPY %vreg572:sub0; VReg_32:%vreg573 VReg_128:%vreg572
	%vreg574<def> = COPY %vreg562; VReg_128:%vreg574,%vreg562
	%vreg575<def> = COPY %vreg574:sub1; VReg_32:%vreg575 VReg_128:%vreg574
	%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
	%vreg577<def> = COPY %vreg576:sub0; VReg_32:%vreg577 VReg_64:%vreg576
	%vreg578<def> = COPY %vreg245; VReg_64:%vreg578,%vreg245
	%vreg579<def> = COPY %vreg578:sub1; VReg_32:%vreg579 VReg_64:%vreg578
	%vreg565<def> = V_ADD_I32_e32 %vreg573, %vreg577, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
	%vreg566<def> = V_ADDC_U32_e32 %vreg575, %vreg579, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
	%vreg567<def> = REG_SEQUENCE %vreg565, sub0, %vreg566, sub1; VReg_64:%vreg567 VReg_32:%vreg565,%vreg566
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
	%vreg698<def> = COPY %vreg697:sub0; VReg_32:%vreg698 VReg_128:%vreg697
	%vreg699<def> = COPY %vreg687; VReg_128:%vreg699,%vreg687
	%vreg700<def> = COPY %vreg699:sub1; VReg_32:%vreg700 VReg_128:%vreg699
	%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
	%vreg702<def> = COPY %vreg701:sub0; VReg_32:%vreg702 VReg_64:%vreg701
	%vreg703<def> = COPY %vreg247; VReg_64:%vreg703,%vreg247
	%vreg704<def> = COPY %vreg703:sub1; VReg_32:%vreg704 VReg_64:%vreg703
	%vreg690<def> = V_ADD_I32_e32 %vreg698, %vreg702, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
	%vreg691<def> = V_ADDC_U32_e32 %vreg700, %vreg704, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
	%vreg692<def> = REG_SEQUENCE %vreg690, sub0, %vreg691, sub1; VReg_64:%vreg692 VReg_32:%vreg690,%vreg691
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg816<def> = COPY %vreg23:sub1; VReg_32:%vreg816 VReg_64:%vreg23
	%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
	%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
	%vreg817<def> = V_ADDC_U32_e32 %vreg816<kill>, %vreg818, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg817,%vreg816,%vreg818
	%vreg812<def> = REG_SEQUENCE %vreg811, sub0, %vreg817, sub1; VReg_64:%vreg812 VReg_32:%vreg811,%vreg817
	%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
	%vreg825<def> = COPY %vreg24:sub1; VReg_32:%vreg825 VReg_64:%vreg24
	%vreg820<def> = V_ADD_I32_e32 %vreg284, %vreg819<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
	%vreg827<def> = COPY %vreg286; VReg_32:%vreg827 SReg_32:%vreg286
	%vreg826<def> = V_ADDC_U32_e32 %vreg825<kill>, %vreg827, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg826,%vreg825,%vreg827
	%vreg821<def> = REG_SEQUENCE %vreg820, sub0, %vreg826, sub1; VReg_64:%vreg821 VReg_32:%vreg820,%vreg826
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg545<def> = V_ADD_I32_e32 16, %vreg542, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg545,%vreg542
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg815<def> = COPY %vreg812; VReg_64:%vreg815,%vreg812
	%vreg824<def> = COPY %vreg821; VReg_64:%vreg824,%vreg821
	%vreg27<def> = COPY %vreg282; VGPR_32:%vreg27,%vreg282
	%vreg544<def> = COPY %vreg545; VReg_32:%vreg544,%vreg545
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VGPR_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg302, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 SGPR_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg833, <BB#10>; VReg_64:%vreg34,%vreg19,%vreg833
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg842, <BB#10>; VReg_64:%vreg35,%vreg18,%vreg842
	%vreg455<def> = PHI %vreg456, <BB#6>, %vreg457, <BB#10>; VReg_32:%vreg455,%vreg456,%vreg457
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VGPR_32:%vreg37,%vreg15,%vreg38
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
	%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
	%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
	%vreg835<def> = V_ADDC_U32_e32 %vreg834<kill>, %vreg836, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg835,%vreg834,%vreg836
	%vreg830<def> = REG_SEQUENCE %vreg829, sub0, %vreg835, sub1; VReg_64:%vreg830 VReg_32:%vreg829,%vreg835
	%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
	%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
	%vreg838<def> = V_ADD_I32_e32 %vreg354, %vreg837<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
	%vreg845<def> = COPY %vreg356; VReg_32:%vreg845 SReg_32:%vreg356
	%vreg844<def> = V_ADDC_U32_e32 %vreg843<kill>, %vreg845, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg844,%vreg843,%vreg845
	%vreg839<def> = REG_SEQUENCE %vreg838, sub0, %vreg844, sub1; VReg_64:%vreg839 VReg_32:%vreg838,%vreg844
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg352, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg352,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
	%vreg458<def> = V_ADD_I32_e32 -1, %vreg455, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg458,%vreg455
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg833<def> = COPY %vreg830; VReg_64:%vreg833,%vreg830
	%vreg842<def> = COPY %vreg839; VReg_64:%vreg842,%vreg839
	%vreg38<def> = COPY %vreg370; VGPR_32:%vreg38,%vreg370
	%vreg457<def> = COPY %vreg458; VReg_32:%vreg457,%vreg458
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VGPR_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
	%vreg424<def> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg424,%vreg374,%vreg423
	%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
	%vreg425<def> = REG_SEQUENCE %vreg424, sub0, %vreg437, sub1; VReg_64:%vreg425 VReg_32:%vreg424,%vreg437
	%vreg428<def> = V_LSHL_B64 %vreg425<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
	%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
	%vreg429<def> = COPY %vreg428:sub1; VReg_32:%vreg429 VReg_64:%vreg428
	%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
	%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
	%vreg436<def> = V_ADD_I32_e32 %vreg847<kill>, %vreg435<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
	%vreg430<def> = V_ADDC_U32_e32 %vreg848, %vreg429<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg430,%vreg848,%vreg429
	%vreg432<def> = REG_SEQUENCE %vreg436, sub0, %vreg430, sub1; VReg_64:%vreg432 VReg_32:%vreg436,%vreg430
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg43,%vreg56
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg45<def> = COPY %vreg432; VReg_64:%vreg45,%vreg432
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg393<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg393
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg395, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Remove unreachable machine basic blocks ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg59, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg423,%vreg63,%vreg59
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg57, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg440,%vreg71,%vreg57
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg442<def> = COPY %vreg57; VReg_32:%vreg442,%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg445<def> = COPY %vreg59; VReg_32:%vreg445,%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg448<def> = COPY %vreg90; VReg_32:%vreg448,%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VGPR_32:%vreg87,%vreg91
	%vreg450<def> = COPY %vreg448; VReg_32:%vreg450,%vreg448
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg443
	%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg101, %EXEC<imp-use>; VReg_32:%vreg497,%vreg101
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg497<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101,%vreg497
	%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
	%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
	%vreg500<def> = COPY %vreg499:sub1; VReg_32:%vreg500 VReg_64:%vreg499
	%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
	%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
	%vreg515<def> = V_ADD_I32_e32 %vreg516<kill>, %vreg514<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
	%vreg501<def> = V_ADDC_U32_e32 %vreg500<kill>, %vreg517, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg501,%vreg500,%vreg517
	%vreg503<def> = REG_SEQUENCE %vreg515, sub0, %vreg501, sub1; VReg_64:%vreg503 VReg_32:%vreg515,%vreg501
	%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
	%vreg506<def> = COPY %vreg503:sub1; VReg_32:%vreg506 VReg_64:%vreg503
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
	%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
	%vreg507<def> = V_ADDC_U32_e32 %vreg506<kill>, %vreg508, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg507,%vreg506,%vreg508
	%vreg509<def> = REG_SEQUENCE %vreg513, sub0, %vreg507, sub1; VReg_64:%vreg509 VReg_32:%vreg513,%vreg507
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg446
	%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg127, %EXEC<imp-use>; VReg_32:%vreg520,%vreg127
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg520<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127,%vreg520
	%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
	%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
	%vreg523<def> = COPY %vreg522:sub1; VReg_32:%vreg523 VReg_64:%vreg522
	%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
	%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
	%vreg538<def> = V_ADD_I32_e32 %vreg539<kill>, %vreg537<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
	%vreg524<def> = V_ADDC_U32_e32 %vreg523<kill>, %vreg540, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg524,%vreg523,%vreg540
	%vreg526<def> = REG_SEQUENCE %vreg538, sub0, %vreg524, sub1; VReg_64:%vreg526 VReg_32:%vreg538,%vreg524
	%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
	%vreg529<def> = COPY %vreg526:sub1; VReg_32:%vreg529 VReg_64:%vreg526
	%vreg536<def> = V_ADD_I32_e32 %vreg117, %vreg535<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
	%vreg531<def> = COPY %vreg118; VReg_32:%vreg531 SReg_32:%vreg118
	%vreg530<def> = V_ADDC_U32_e32 %vreg529<kill>, %vreg531, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg530,%vreg529,%vreg531
	%vreg532<def> = REG_SEQUENCE %vreg536, sub0, %vreg530, sub1; VReg_64:%vreg532 VReg_32:%vreg536,%vreg530
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VGPR_32:%vreg95,%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg541<def> = COPY %vreg146; VReg_32:%vreg541,%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
	%vreg12<def> = COPY %vreg509; VReg_64:%vreg12,%vreg509
	%vreg11<def> = COPY %vreg532; VReg_64:%vreg11,%vreg532
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg543<def> = COPY %vreg541; VReg_32:%vreg543,%vreg541
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	%vreg451<def> = COPY %vreg13; VReg_32:%vreg451 SReg_32:%vreg13
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg86, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg452<def> = PHI %vreg453, <BB#7>; VReg_32:%vreg452,%vreg453
	%vreg15<def> = PHI %vreg20, <BB#7>; VGPR_32:%vreg15,%vreg20
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg452, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg452 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg444
	%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg309, %EXEC<imp-use>; VReg_32:%vreg548,%vreg309
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg548<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309,%vreg548
	%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
	%vreg550<def> = COPY %vreg312:sub1; VReg_32:%vreg550 VReg_64:%vreg312
	%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg452, %EXEC<imp-use>; VReg_32:%vreg494,%vreg452
	%vreg459<def> = REG_SEQUENCE %vreg452, sub0, %vreg494, sub1; VReg_64:%vreg459 VReg_32:%vreg452,%vreg494
	%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
	%vreg462<def> = COPY %vreg459:sub1; VReg_32:%vreg462 VReg_64:%vreg459
	%vreg493<def> = V_ADD_I32_e32 %vreg549<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
	%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg550, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg477,%vreg462,%vreg550
	%vreg479<def> = REG_SEQUENCE %vreg493, sub0, %vreg477, sub1; VReg_64:%vreg479 VReg_32:%vreg493,%vreg477
	%vreg482<def> = V_LSHL_B64 %vreg479<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
	%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
	%vreg483<def> = COPY %vreg482:sub1; VReg_32:%vreg483 VReg_64:%vreg482
	%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
	%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
	%vreg490<def> = V_ADD_I32_e32 %vreg551<kill>, %vreg489<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
	%vreg484<def> = V_ADDC_U32_e32 %vreg552, %vreg483<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg484,%vreg552,%vreg483
	%vreg486<def> = REG_SEQUENCE %vreg490, sub0, %vreg484, sub1; VReg_64:%vreg486 VReg_32:%vreg490,%vreg484
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg447
	%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg335, %EXEC<imp-use>; VReg_32:%vreg555,%vreg335
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg555<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335,%vreg555
	%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
	%vreg557<def> = COPY %vreg338:sub1; VReg_32:%vreg557 VReg_64:%vreg338
	%vreg492<def> = V_ADD_I32_e32 %vreg556<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
	%vreg463<def> = V_ADDC_U32_e32 %vreg462, %vreg557, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg463,%vreg462,%vreg557
	%vreg465<def> = REG_SEQUENCE %vreg492, sub0, %vreg463, sub1; VReg_64:%vreg465 VReg_32:%vreg492,%vreg463
	%vreg468<def> = V_LSHL_B64 %vreg465<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
	%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
	%vreg469<def> = COPY %vreg468:sub1; VReg_32:%vreg469 VReg_64:%vreg468
	%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
	%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
	%vreg476<def> = V_ADD_I32_e32 %vreg558<kill>, %vreg475<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
	%vreg470<def> = V_ADDC_U32_e32 %vreg559, %vreg469<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg470,%vreg559,%vreg469
	%vreg472<def> = REG_SEQUENCE %vreg476, sub0, %vreg470, sub1; VReg_64:%vreg472 VReg_32:%vreg476,%vreg470
	%vreg454<def> = V_SUB_I32_e32 %vreg55, %vreg452, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg454,%vreg452 SReg_32:%vreg55
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
	%vreg19<def> = COPY %vreg486; VReg_64:%vreg19,%vreg486
	%vreg18<def> = COPY %vreg472; VReg_64:%vreg18,%vreg472
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg456<def> = COPY %vreg454; VReg_32:%vreg456,%vreg454
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VGPR_32:%vreg20,%vreg87,%vreg27
	%vreg449<def> = PHI %vreg450, <BB#1>, %vreg451, <BB#3>; VReg_32:%vreg449,%vreg450,%vreg451
	%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	SI_END_CF %vreg92, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92
	%vreg453<def> = COPY %vreg449; VReg_32:%vreg453,%vreg449
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 SGPR_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg815, <BB#8>; VReg_64:%vreg23,%vreg12,%vreg815
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg824, <BB#8>; VReg_64:%vreg24,%vreg11,%vreg824
	%vreg542<def> = PHI %vreg543, <BB#2>, %vreg544, <BB#8>; VReg_32:%vreg542,%vreg543,%vreg544
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VGPR_32:%vreg26,%vreg95,%vreg27
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg147,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183<def> = REG_SEQUENCE %vreg182, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
	%vreg561<def> = COPY %vreg560; VReg_64:%vreg561,%vreg560
	%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
	%vreg562<def> = REG_SEQUENCE %vreg561, sub0_sub1, %vreg564, sub2_sub3; VReg_128:%vreg562 VReg_64:%vreg561,%vreg564
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
	%vreg678<def> = COPY %vreg677:sub0; VReg_32:%vreg678 VReg_128:%vreg677
	%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
	%vreg680<def> = COPY %vreg679:sub1; VReg_32:%vreg680 VReg_128:%vreg679
	%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
	%vreg682<def> = COPY %vreg681:sub0; VReg_32:%vreg682 VReg_64:%vreg681
	%vreg683<def> = COPY %vreg187; VReg_64:%vreg683,%vreg187
	%vreg684<def> = COPY %vreg683:sub1; VReg_32:%vreg684 VReg_64:%vreg683
	%vreg670<def> = V_ADD_I32_e32 %vreg678, %vreg682, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
	%vreg671<def> = V_ADDC_U32_e32 %vreg680, %vreg684, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
	%vreg672<def> = REG_SEQUENCE %vreg670, sub0, %vreg671, sub1; VReg_64:%vreg672 VReg_32:%vreg670,%vreg671
	%vreg676<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg401, sub2, %vreg400, sub3; SReg_128:%vreg676 SGPR_64:%vreg147 SGPR_32:%vreg401,%vreg400
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
	%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
	%vreg686<def> = COPY %vreg685; VReg_64:%vreg686,%vreg685
	%vreg689<def> = COPY %vreg399; VReg_64:%vreg689 SGPR_64:%vreg399
	%vreg687<def> = REG_SEQUENCE %vreg686, sub0_sub1, %vreg689, sub2_sub3; VReg_128:%vreg687 VReg_64:%vreg686,%vreg689
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
	%vreg803<def> = COPY %vreg802:sub0; VReg_32:%vreg803 VReg_128:%vreg802
	%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
	%vreg805<def> = COPY %vreg804:sub1; VReg_32:%vreg805 VReg_128:%vreg804
	%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
	%vreg807<def> = COPY %vreg806:sub0; VReg_32:%vreg807 VReg_64:%vreg806
	%vreg808<def> = COPY %vreg191; VReg_64:%vreg808,%vreg191
	%vreg809<def> = COPY %vreg808:sub1; VReg_32:%vreg809 VReg_64:%vreg808
	%vreg795<def> = V_ADD_I32_e32 %vreg803, %vreg807, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
	%vreg796<def> = V_ADDC_U32_e32 %vreg805, %vreg809, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
	%vreg797<def> = REG_SEQUENCE %vreg795, sub0, %vreg796, sub1; VReg_64:%vreg797 VReg_32:%vreg795,%vreg796
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195<def> = REG_SEQUENCE %vreg194, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
	%vreg663<def> = COPY %vreg662:sub0; VReg_32:%vreg663 VReg_128:%vreg662
	%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
	%vreg665<def> = COPY %vreg664:sub1; VReg_32:%vreg665 VReg_128:%vreg664
	%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
	%vreg667<def> = COPY %vreg666:sub0; VReg_32:%vreg667 VReg_64:%vreg666
	%vreg668<def> = COPY %vreg197; VReg_64:%vreg668,%vreg197
	%vreg669<def> = COPY %vreg668:sub1; VReg_32:%vreg669 VReg_64:%vreg668
	%vreg655<def> = V_ADD_I32_e32 %vreg663, %vreg667, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
	%vreg656<def> = V_ADDC_U32_e32 %vreg665, %vreg669, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
	%vreg657<def> = REG_SEQUENCE %vreg655, sub0, %vreg656, sub1; VReg_64:%vreg657 VReg_32:%vreg655,%vreg656
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
	%vreg788<def> = COPY %vreg787:sub0; VReg_32:%vreg788 VReg_128:%vreg787
	%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
	%vreg790<def> = COPY %vreg789:sub1; VReg_32:%vreg790 VReg_128:%vreg789
	%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
	%vreg792<def> = COPY %vreg791:sub0; VReg_32:%vreg792 VReg_64:%vreg791
	%vreg793<def> = COPY %vreg199; VReg_64:%vreg793,%vreg199
	%vreg794<def> = COPY %vreg793:sub1; VReg_32:%vreg794 VReg_64:%vreg793
	%vreg780<def> = V_ADD_I32_e32 %vreg788, %vreg792, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
	%vreg781<def> = V_ADDC_U32_e32 %vreg790, %vreg794, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
	%vreg782<def> = REG_SEQUENCE %vreg780, sub0, %vreg781, sub1; VReg_64:%vreg782 VReg_32:%vreg780,%vreg781
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203<def> = REG_SEQUENCE %vreg202, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
	%vreg648<def> = COPY %vreg647:sub0; VReg_32:%vreg648 VReg_128:%vreg647
	%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
	%vreg650<def> = COPY %vreg649:sub1; VReg_32:%vreg650 VReg_128:%vreg649
	%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
	%vreg652<def> = COPY %vreg651:sub0; VReg_32:%vreg652 VReg_64:%vreg651
	%vreg653<def> = COPY %vreg205; VReg_64:%vreg653,%vreg205
	%vreg654<def> = COPY %vreg653:sub1; VReg_32:%vreg654 VReg_64:%vreg653
	%vreg640<def> = V_ADD_I32_e32 %vreg648, %vreg652, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
	%vreg641<def> = V_ADDC_U32_e32 %vreg650, %vreg654, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
	%vreg642<def> = REG_SEQUENCE %vreg640, sub0, %vreg641, sub1; VReg_64:%vreg642 VReg_32:%vreg640,%vreg641
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
	%vreg773<def> = COPY %vreg772:sub0; VReg_32:%vreg773 VReg_128:%vreg772
	%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
	%vreg775<def> = COPY %vreg774:sub1; VReg_32:%vreg775 VReg_128:%vreg774
	%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
	%vreg777<def> = COPY %vreg776:sub0; VReg_32:%vreg777 VReg_64:%vreg776
	%vreg778<def> = COPY %vreg207; VReg_64:%vreg778,%vreg207
	%vreg779<def> = COPY %vreg778:sub1; VReg_32:%vreg779 VReg_64:%vreg778
	%vreg765<def> = V_ADD_I32_e32 %vreg773, %vreg777, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
	%vreg766<def> = V_ADDC_U32_e32 %vreg775, %vreg779, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
	%vreg767<def> = REG_SEQUENCE %vreg765, sub0, %vreg766, sub1; VReg_64:%vreg767 VReg_32:%vreg765,%vreg766
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211<def> = REG_SEQUENCE %vreg210, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
	%vreg633<def> = COPY %vreg632:sub0; VReg_32:%vreg633 VReg_128:%vreg632
	%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
	%vreg635<def> = COPY %vreg634:sub1; VReg_32:%vreg635 VReg_128:%vreg634
	%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
	%vreg637<def> = COPY %vreg636:sub0; VReg_32:%vreg637 VReg_64:%vreg636
	%vreg638<def> = COPY %vreg213; VReg_64:%vreg638,%vreg213
	%vreg639<def> = COPY %vreg638:sub1; VReg_32:%vreg639 VReg_64:%vreg638
	%vreg625<def> = V_ADD_I32_e32 %vreg633, %vreg637, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
	%vreg626<def> = V_ADDC_U32_e32 %vreg635, %vreg639, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
	%vreg627<def> = REG_SEQUENCE %vreg625, sub0, %vreg626, sub1; VReg_64:%vreg627 VReg_32:%vreg625,%vreg626
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
	%vreg758<def> = COPY %vreg757:sub0; VReg_32:%vreg758 VReg_128:%vreg757
	%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
	%vreg760<def> = COPY %vreg759:sub1; VReg_32:%vreg760 VReg_128:%vreg759
	%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
	%vreg762<def> = COPY %vreg761:sub0; VReg_32:%vreg762 VReg_64:%vreg761
	%vreg763<def> = COPY %vreg215; VReg_64:%vreg763,%vreg215
	%vreg764<def> = COPY %vreg763:sub1; VReg_32:%vreg764 VReg_64:%vreg763
	%vreg750<def> = V_ADD_I32_e32 %vreg758, %vreg762, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
	%vreg751<def> = V_ADDC_U32_e32 %vreg760, %vreg764, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
	%vreg752<def> = REG_SEQUENCE %vreg750, sub0, %vreg751, sub1; VReg_64:%vreg752 VReg_32:%vreg750,%vreg751
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219<def> = REG_SEQUENCE %vreg218, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
	%vreg618<def> = COPY %vreg617:sub0; VReg_32:%vreg618 VReg_128:%vreg617
	%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
	%vreg620<def> = COPY %vreg619:sub1; VReg_32:%vreg620 VReg_128:%vreg619
	%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
	%vreg622<def> = COPY %vreg621:sub0; VReg_32:%vreg622 VReg_64:%vreg621
	%vreg623<def> = COPY %vreg221; VReg_64:%vreg623,%vreg221
	%vreg624<def> = COPY %vreg623:sub1; VReg_32:%vreg624 VReg_64:%vreg623
	%vreg610<def> = V_ADD_I32_e32 %vreg618, %vreg622, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
	%vreg611<def> = V_ADDC_U32_e32 %vreg620, %vreg624, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
	%vreg612<def> = REG_SEQUENCE %vreg610, sub0, %vreg611, sub1; VReg_64:%vreg612 VReg_32:%vreg610,%vreg611
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
	%vreg743<def> = COPY %vreg742:sub0; VReg_32:%vreg743 VReg_128:%vreg742
	%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
	%vreg745<def> = COPY %vreg744:sub1; VReg_32:%vreg745 VReg_128:%vreg744
	%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
	%vreg747<def> = COPY %vreg746:sub0; VReg_32:%vreg747 VReg_64:%vreg746
	%vreg748<def> = COPY %vreg223; VReg_64:%vreg748,%vreg223
	%vreg749<def> = COPY %vreg748:sub1; VReg_32:%vreg749 VReg_64:%vreg748
	%vreg735<def> = V_ADD_I32_e32 %vreg743, %vreg747, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
	%vreg736<def> = V_ADDC_U32_e32 %vreg745, %vreg749, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
	%vreg737<def> = REG_SEQUENCE %vreg735, sub0, %vreg736, sub1; VReg_64:%vreg737 VReg_32:%vreg735,%vreg736
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227<def> = REG_SEQUENCE %vreg226, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
	%vreg603<def> = COPY %vreg602:sub0; VReg_32:%vreg603 VReg_128:%vreg602
	%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
	%vreg605<def> = COPY %vreg604:sub1; VReg_32:%vreg605 VReg_128:%vreg604
	%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
	%vreg607<def> = COPY %vreg606:sub0; VReg_32:%vreg607 VReg_64:%vreg606
	%vreg608<def> = COPY %vreg229; VReg_64:%vreg608,%vreg229
	%vreg609<def> = COPY %vreg608:sub1; VReg_32:%vreg609 VReg_64:%vreg608
	%vreg595<def> = V_ADD_I32_e32 %vreg603, %vreg607, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
	%vreg596<def> = V_ADDC_U32_e32 %vreg605, %vreg609, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
	%vreg597<def> = REG_SEQUENCE %vreg595, sub0, %vreg596, sub1; VReg_64:%vreg597 VReg_32:%vreg595,%vreg596
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
	%vreg728<def> = COPY %vreg727:sub0; VReg_32:%vreg728 VReg_128:%vreg727
	%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
	%vreg730<def> = COPY %vreg729:sub1; VReg_32:%vreg730 VReg_128:%vreg729
	%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
	%vreg732<def> = COPY %vreg731:sub0; VReg_32:%vreg732 VReg_64:%vreg731
	%vreg733<def> = COPY %vreg231; VReg_64:%vreg733,%vreg231
	%vreg734<def> = COPY %vreg733:sub1; VReg_32:%vreg734 VReg_64:%vreg733
	%vreg720<def> = V_ADD_I32_e32 %vreg728, %vreg732, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
	%vreg721<def> = V_ADDC_U32_e32 %vreg730, %vreg734, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
	%vreg722<def> = REG_SEQUENCE %vreg720, sub0, %vreg721, sub1; VReg_64:%vreg722 VReg_32:%vreg720,%vreg721
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235<def> = REG_SEQUENCE %vreg234, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
	%vreg588<def> = COPY %vreg587:sub0; VReg_32:%vreg588 VReg_128:%vreg587
	%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
	%vreg590<def> = COPY %vreg589:sub1; VReg_32:%vreg590 VReg_128:%vreg589
	%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
	%vreg592<def> = COPY %vreg591:sub0; VReg_32:%vreg592 VReg_64:%vreg591
	%vreg593<def> = COPY %vreg237; VReg_64:%vreg593,%vreg237
	%vreg594<def> = COPY %vreg593:sub1; VReg_32:%vreg594 VReg_64:%vreg593
	%vreg580<def> = V_ADD_I32_e32 %vreg588, %vreg592, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
	%vreg581<def> = V_ADDC_U32_e32 %vreg590, %vreg594, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
	%vreg582<def> = REG_SEQUENCE %vreg580, sub0, %vreg581, sub1; VReg_64:%vreg582 VReg_32:%vreg580,%vreg581
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
	%vreg713<def> = COPY %vreg712:sub0; VReg_32:%vreg713 VReg_128:%vreg712
	%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
	%vreg715<def> = COPY %vreg714:sub1; VReg_32:%vreg715 VReg_128:%vreg714
	%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
	%vreg717<def> = COPY %vreg716:sub0; VReg_32:%vreg717 VReg_64:%vreg716
	%vreg718<def> = COPY %vreg239; VReg_64:%vreg718,%vreg239
	%vreg719<def> = COPY %vreg718:sub1; VReg_32:%vreg719 VReg_64:%vreg718
	%vreg705<def> = V_ADD_I32_e32 %vreg713, %vreg717, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
	%vreg706<def> = V_ADDC_U32_e32 %vreg715, %vreg719, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
	%vreg707<def> = REG_SEQUENCE %vreg705, sub0, %vreg706, sub1; VReg_64:%vreg707 VReg_32:%vreg705,%vreg706
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243<def> = REG_SEQUENCE %vreg242, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
	%vreg573<def> = COPY %vreg572:sub0; VReg_32:%vreg573 VReg_128:%vreg572
	%vreg574<def> = COPY %vreg562; VReg_128:%vreg574,%vreg562
	%vreg575<def> = COPY %vreg574:sub1; VReg_32:%vreg575 VReg_128:%vreg574
	%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
	%vreg577<def> = COPY %vreg576:sub0; VReg_32:%vreg577 VReg_64:%vreg576
	%vreg578<def> = COPY %vreg245; VReg_64:%vreg578,%vreg245
	%vreg579<def> = COPY %vreg578:sub1; VReg_32:%vreg579 VReg_64:%vreg578
	%vreg565<def> = V_ADD_I32_e32 %vreg573, %vreg577, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
	%vreg566<def> = V_ADDC_U32_e32 %vreg575, %vreg579, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
	%vreg567<def> = REG_SEQUENCE %vreg565, sub0, %vreg566, sub1; VReg_64:%vreg567 VReg_32:%vreg565,%vreg566
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
	%vreg698<def> = COPY %vreg697:sub0; VReg_32:%vreg698 VReg_128:%vreg697
	%vreg699<def> = COPY %vreg687; VReg_128:%vreg699,%vreg687
	%vreg700<def> = COPY %vreg699:sub1; VReg_32:%vreg700 VReg_128:%vreg699
	%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
	%vreg702<def> = COPY %vreg701:sub0; VReg_32:%vreg702 VReg_64:%vreg701
	%vreg703<def> = COPY %vreg247; VReg_64:%vreg703,%vreg247
	%vreg704<def> = COPY %vreg703:sub1; VReg_32:%vreg704 VReg_64:%vreg703
	%vreg690<def> = V_ADD_I32_e32 %vreg698, %vreg702, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
	%vreg691<def> = V_ADDC_U32_e32 %vreg700, %vreg704, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
	%vreg692<def> = REG_SEQUENCE %vreg690, sub0, %vreg691, sub1; VReg_64:%vreg692 VReg_32:%vreg690,%vreg691
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg816<def> = COPY %vreg23:sub1; VReg_32:%vreg816 VReg_64:%vreg23
	%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
	%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
	%vreg817<def> = V_ADDC_U32_e32 %vreg816<kill>, %vreg818, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg817,%vreg816,%vreg818
	%vreg812<def> = REG_SEQUENCE %vreg811, sub0, %vreg817, sub1; VReg_64:%vreg812 VReg_32:%vreg811,%vreg817
	%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
	%vreg825<def> = COPY %vreg24:sub1; VReg_32:%vreg825 VReg_64:%vreg24
	%vreg820<def> = V_ADD_I32_e32 %vreg284, %vreg819<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
	%vreg827<def> = COPY %vreg286; VReg_32:%vreg827 SReg_32:%vreg286
	%vreg826<def> = V_ADDC_U32_e32 %vreg825<kill>, %vreg827, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg826,%vreg825,%vreg827
	%vreg821<def> = REG_SEQUENCE %vreg820, sub0, %vreg826, sub1; VReg_64:%vreg821 VReg_32:%vreg820,%vreg826
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg545<def> = V_ADD_I32_e32 16, %vreg542, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg545,%vreg542
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg815<def> = COPY %vreg812; VReg_64:%vreg815,%vreg812
	%vreg824<def> = COPY %vreg821; VReg_64:%vreg824,%vreg821
	%vreg27<def> = COPY %vreg282; VGPR_32:%vreg27,%vreg282
	%vreg544<def> = COPY %vreg545; VReg_32:%vreg544,%vreg545
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg15, <BB#5>, %vreg38, <BB#11>; VGPR_32:%vreg32,%vreg15,%vreg38
	SI_END_CF %vreg302, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 SGPR_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg833, <BB#10>; VReg_64:%vreg34,%vreg19,%vreg833
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg842, <BB#10>; VReg_64:%vreg35,%vreg18,%vreg842
	%vreg455<def> = PHI %vreg456, <BB#6>, %vreg457, <BB#10>; VReg_32:%vreg455,%vreg456,%vreg457
	%vreg37<def> = PHI %vreg15, <BB#6>, %vreg38, <BB#10>; VGPR_32:%vreg37,%vreg15,%vreg38
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
	%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
	%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
	%vreg835<def> = V_ADDC_U32_e32 %vreg834<kill>, %vreg836, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg835,%vreg834,%vreg836
	%vreg830<def> = REG_SEQUENCE %vreg829, sub0, %vreg835, sub1; VReg_64:%vreg830 VReg_32:%vreg829,%vreg835
	%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
	%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
	%vreg838<def> = V_ADD_I32_e32 %vreg354, %vreg837<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
	%vreg845<def> = COPY %vreg356; VReg_32:%vreg845 SReg_32:%vreg356
	%vreg844<def> = V_ADDC_U32_e32 %vreg843<kill>, %vreg845, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg844,%vreg843,%vreg845
	%vreg839<def> = REG_SEQUENCE %vreg838, sub0, %vreg844, sub1; VReg_64:%vreg839 VReg_32:%vreg838,%vreg844
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg352, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg352,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
	%vreg458<def> = V_ADD_I32_e32 -1, %vreg455, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg458,%vreg455
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg833<def> = COPY %vreg830; VReg_64:%vreg833,%vreg830
	%vreg842<def> = COPY %vreg839; VReg_64:%vreg842,%vreg839
	%vreg38<def> = COPY %vreg370; VGPR_32:%vreg38,%vreg370
	%vreg457<def> = COPY %vreg458; VReg_32:%vreg457,%vreg458
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg43<def> = PHI %vreg32, <BB#9>; VGPR_32:%vreg43,%vreg32
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
	%vreg424<def> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg424,%vreg374,%vreg423
	%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
	%vreg425<def> = REG_SEQUENCE %vreg424, sub0, %vreg437, sub1; VReg_64:%vreg425 VReg_32:%vreg424,%vreg437
	%vreg428<def> = V_LSHL_B64 %vreg425<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
	%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
	%vreg429<def> = COPY %vreg428:sub1; VReg_32:%vreg429 VReg_64:%vreg428
	%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
	%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
	%vreg436<def> = V_ADD_I32_e32 %vreg847<kill>, %vreg435<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
	%vreg430<def> = V_ADDC_U32_e32 %vreg848, %vreg429<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg430,%vreg848,%vreg429
	%vreg432<def> = REG_SEQUENCE %vreg436, sub0, %vreg430, sub1; VReg_64:%vreg432 VReg_32:%vreg436,%vreg430
	%vreg388<def> = V_MUL_F32_e64 %vreg43, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg43,%vreg56
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg45<def> = COPY %vreg432; VReg_64:%vreg45,%vreg432
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg393<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg393
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg395, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Live Variable Analysis ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg59, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg423,%vreg63,%vreg59
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg57, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg440,%vreg71,%vreg57
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg442<def> = COPY %vreg57; VReg_32:%vreg442,%vreg57
	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	%vreg445<def> = COPY %vreg59; VReg_32:%vreg445,%vreg59
	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg448<def> = COPY %vreg90; VReg_32:%vreg448,%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91; VGPR_32:%vreg87,%vreg91
	%vreg450<def> = COPY %vreg448; VReg_32:%vreg450,%vreg448
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg443
	%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg101, %EXEC<imp-use>; VReg_32:%vreg497,%vreg101
	%vreg104<def> = REG_SEQUENCE %vreg101, sub0, %vreg497<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101,%vreg497
	%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
	%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
	%vreg500<def> = COPY %vreg499:sub1; VReg_32:%vreg500 VReg_64:%vreg499
	%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
	%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
	%vreg515<def> = V_ADD_I32_e32 %vreg516<kill>, %vreg514<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
	%vreg501<def> = V_ADDC_U32_e32 %vreg500<kill>, %vreg517, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg501,%vreg500,%vreg517
	%vreg503<def> = REG_SEQUENCE %vreg515, sub0, %vreg501, sub1; VReg_64:%vreg503 VReg_32:%vreg515,%vreg501
	%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
	%vreg506<def> = COPY %vreg503:sub1; VReg_32:%vreg506 VReg_64:%vreg503
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
	%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
	%vreg507<def> = V_ADDC_U32_e32 %vreg506<kill>, %vreg508, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg507,%vreg506,%vreg508
	%vreg509<def> = REG_SEQUENCE %vreg513, sub0, %vreg507, sub1; VReg_64:%vreg509 VReg_32:%vreg513,%vreg507
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg446
	%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg127, %EXEC<imp-use>; VReg_32:%vreg520,%vreg127
	%vreg130<def> = REG_SEQUENCE %vreg127, sub0, %vreg520<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127,%vreg520
	%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
	%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
	%vreg523<def> = COPY %vreg522:sub1; VReg_32:%vreg523 VReg_64:%vreg522
	%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
	%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
	%vreg538<def> = V_ADD_I32_e32 %vreg539<kill>, %vreg537<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
	%vreg524<def> = V_ADDC_U32_e32 %vreg523<kill>, %vreg540, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg524,%vreg523,%vreg540
	%vreg526<def> = REG_SEQUENCE %vreg538, sub0, %vreg524, sub1; VReg_64:%vreg526 VReg_32:%vreg538,%vreg524
	%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
	%vreg529<def> = COPY %vreg526:sub1; VReg_32:%vreg529 VReg_64:%vreg526
	%vreg536<def> = V_ADD_I32_e32 %vreg117, %vreg535<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
	%vreg531<def> = COPY %vreg118; VReg_32:%vreg531 SReg_32:%vreg118
	%vreg530<def> = V_ADDC_U32_e32 %vreg529<kill>, %vreg531, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg530,%vreg529,%vreg531
	%vreg532<def> = REG_SEQUENCE %vreg536, sub0, %vreg530, sub1; VReg_64:%vreg532 VReg_32:%vreg536,%vreg530
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145; VGPR_32:%vreg95,%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg541<def> = COPY %vreg146; VReg_32:%vreg541,%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
	%vreg12<def> = COPY %vreg509; VReg_64:%vreg12,%vreg509
	%vreg11<def> = COPY %vreg532; VReg_64:%vreg11,%vreg532
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg543<def> = COPY %vreg541; VReg_32:%vreg543,%vreg541
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	%vreg451<def> = COPY %vreg13; VReg_32:%vreg451 SReg_32:%vreg13
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg86, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg86
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg453, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg453 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
	%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg444
	%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg309, %EXEC<imp-use>; VReg_32:%vreg548,%vreg309
	%vreg312<def> = REG_SEQUENCE %vreg309, sub0, %vreg548<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309,%vreg548
	%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
	%vreg550<def> = COPY %vreg312:sub1; VReg_32:%vreg550 VReg_64:%vreg312
	%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg453, %EXEC<imp-use>; VReg_32:%vreg494,%vreg453
	%vreg459<def> = REG_SEQUENCE %vreg453, sub0, %vreg494, sub1; VReg_64:%vreg459 VReg_32:%vreg453,%vreg494
	%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
	%vreg462<def> = COPY %vreg459:sub1; VReg_32:%vreg462 VReg_64:%vreg459
	%vreg493<def> = V_ADD_I32_e32 %vreg549<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
	%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg550, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg477,%vreg462,%vreg550
	%vreg479<def> = REG_SEQUENCE %vreg493, sub0, %vreg477, sub1; VReg_64:%vreg479 VReg_32:%vreg493,%vreg477
	%vreg482<def> = V_LSHL_B64 %vreg479<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
	%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
	%vreg483<def> = COPY %vreg482:sub1; VReg_32:%vreg483 VReg_64:%vreg482
	%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
	%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
	%vreg490<def> = V_ADD_I32_e32 %vreg551<kill>, %vreg489<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
	%vreg484<def> = V_ADDC_U32_e32 %vreg552, %vreg483<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg484,%vreg552,%vreg483
	%vreg486<def> = REG_SEQUENCE %vreg490, sub0, %vreg484, sub1; VReg_64:%vreg486 VReg_32:%vreg490,%vreg484
	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
	%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg447
	%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg335, %EXEC<imp-use>; VReg_32:%vreg555,%vreg335
	%vreg338<def> = REG_SEQUENCE %vreg335, sub0, %vreg555<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335,%vreg555
	%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
	%vreg557<def> = COPY %vreg338:sub1; VReg_32:%vreg557 VReg_64:%vreg338
	%vreg492<def> = V_ADD_I32_e32 %vreg556<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
	%vreg463<def> = V_ADDC_U32_e32 %vreg462, %vreg557, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg463,%vreg462,%vreg557
	%vreg465<def> = REG_SEQUENCE %vreg492, sub0, %vreg463, sub1; VReg_64:%vreg465 VReg_32:%vreg492,%vreg463
	%vreg468<def> = V_LSHL_B64 %vreg465<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
	%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
	%vreg469<def> = COPY %vreg468:sub1; VReg_32:%vreg469 VReg_64:%vreg468
	%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
	%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
	%vreg476<def> = V_ADD_I32_e32 %vreg558<kill>, %vreg475<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
	%vreg470<def> = V_ADDC_U32_e32 %vreg559, %vreg469<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg470,%vreg559,%vreg469
	%vreg472<def> = REG_SEQUENCE %vreg476, sub0, %vreg470, sub1; VReg_64:%vreg472 VReg_32:%vreg476,%vreg470
	%vreg454<def> = V_SUB_I32_e32 %vreg55, %vreg453, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg454,%vreg453 SReg_32:%vreg55
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
	%vreg19<def> = COPY %vreg486; VReg_64:%vreg19,%vreg486
	%vreg18<def> = COPY %vreg472; VReg_64:%vreg18,%vreg472
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg456<def> = COPY %vreg454; VReg_32:%vreg456,%vreg454
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VGPR_32:%vreg20,%vreg87,%vreg27
	%vreg449<def> = PHI %vreg450, <BB#1>, %vreg451, <BB#3>; VReg_32:%vreg449,%vreg450,%vreg451
	%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	SI_END_CF %vreg92, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg92
	%vreg453<def> = COPY %vreg449; VReg_32:%vreg453,%vreg449
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 SGPR_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg815, <BB#8>; VReg_64:%vreg23,%vreg12,%vreg815
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg824, <BB#8>; VReg_64:%vreg24,%vreg11,%vreg824
	%vreg542<def> = PHI %vreg543, <BB#2>, %vreg544, <BB#8>; VReg_32:%vreg542,%vreg543,%vreg544
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VGPR_32:%vreg26,%vreg95,%vreg27
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg147,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183<def> = REG_SEQUENCE %vreg182, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
	%vreg561<def> = COPY %vreg560; VReg_64:%vreg561,%vreg560
	%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
	%vreg562<def> = REG_SEQUENCE %vreg561, sub0_sub1, %vreg564, sub2_sub3; VReg_128:%vreg562 VReg_64:%vreg561,%vreg564
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
	%vreg678<def> = COPY %vreg677:sub0; VReg_32:%vreg678 VReg_128:%vreg677
	%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
	%vreg680<def> = COPY %vreg679:sub1; VReg_32:%vreg680 VReg_128:%vreg679
	%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
	%vreg682<def> = COPY %vreg681:sub0; VReg_32:%vreg682 VReg_64:%vreg681
	%vreg683<def> = COPY %vreg187; VReg_64:%vreg683,%vreg187
	%vreg684<def> = COPY %vreg683:sub1; VReg_32:%vreg684 VReg_64:%vreg683
	%vreg670<def> = V_ADD_I32_e32 %vreg678, %vreg682, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
	%vreg671<def> = V_ADDC_U32_e32 %vreg680, %vreg684, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
	%vreg672<def> = REG_SEQUENCE %vreg670, sub0, %vreg671, sub1; VReg_64:%vreg672 VReg_32:%vreg670,%vreg671
	%vreg676<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg401, sub2, %vreg400, sub3; SReg_128:%vreg676 SGPR_64:%vreg147 SGPR_32:%vreg401,%vreg400
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
	%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
	%vreg686<def> = COPY %vreg685; VReg_64:%vreg686,%vreg685
	%vreg689<def> = COPY %vreg399; VReg_64:%vreg689 SGPR_64:%vreg399
	%vreg687<def> = REG_SEQUENCE %vreg686, sub0_sub1, %vreg689, sub2_sub3; VReg_128:%vreg687 VReg_64:%vreg686,%vreg689
	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
	%vreg803<def> = COPY %vreg802:sub0; VReg_32:%vreg803 VReg_128:%vreg802
	%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
	%vreg805<def> = COPY %vreg804:sub1; VReg_32:%vreg805 VReg_128:%vreg804
	%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
	%vreg807<def> = COPY %vreg806:sub0; VReg_32:%vreg807 VReg_64:%vreg806
	%vreg808<def> = COPY %vreg191; VReg_64:%vreg808,%vreg191
	%vreg809<def> = COPY %vreg808:sub1; VReg_32:%vreg809 VReg_64:%vreg808
	%vreg795<def> = V_ADD_I32_e32 %vreg803, %vreg807, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
	%vreg796<def> = V_ADDC_U32_e32 %vreg805, %vreg809, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
	%vreg797<def> = REG_SEQUENCE %vreg795, sub0, %vreg796, sub1; VReg_64:%vreg797 VReg_32:%vreg795,%vreg796
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195<def> = REG_SEQUENCE %vreg194, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
	%vreg663<def> = COPY %vreg662:sub0; VReg_32:%vreg663 VReg_128:%vreg662
	%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
	%vreg665<def> = COPY %vreg664:sub1; VReg_32:%vreg665 VReg_128:%vreg664
	%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
	%vreg667<def> = COPY %vreg666:sub0; VReg_32:%vreg667 VReg_64:%vreg666
	%vreg668<def> = COPY %vreg197; VReg_64:%vreg668,%vreg197
	%vreg669<def> = COPY %vreg668:sub1; VReg_32:%vreg669 VReg_64:%vreg668
	%vreg655<def> = V_ADD_I32_e32 %vreg663, %vreg667, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
	%vreg656<def> = V_ADDC_U32_e32 %vreg665, %vreg669, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
	%vreg657<def> = REG_SEQUENCE %vreg655, sub0, %vreg656, sub1; VReg_64:%vreg657 VReg_32:%vreg655,%vreg656
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
	%vreg788<def> = COPY %vreg787:sub0; VReg_32:%vreg788 VReg_128:%vreg787
	%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
	%vreg790<def> = COPY %vreg789:sub1; VReg_32:%vreg790 VReg_128:%vreg789
	%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
	%vreg792<def> = COPY %vreg791:sub0; VReg_32:%vreg792 VReg_64:%vreg791
	%vreg793<def> = COPY %vreg199; VReg_64:%vreg793,%vreg199
	%vreg794<def> = COPY %vreg793:sub1; VReg_32:%vreg794 VReg_64:%vreg793
	%vreg780<def> = V_ADD_I32_e32 %vreg788, %vreg792, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
	%vreg781<def> = V_ADDC_U32_e32 %vreg790, %vreg794, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
	%vreg782<def> = REG_SEQUENCE %vreg780, sub0, %vreg781, sub1; VReg_64:%vreg782 VReg_32:%vreg780,%vreg781
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203<def> = REG_SEQUENCE %vreg202, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
	%vreg648<def> = COPY %vreg647:sub0; VReg_32:%vreg648 VReg_128:%vreg647
	%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
	%vreg650<def> = COPY %vreg649:sub1; VReg_32:%vreg650 VReg_128:%vreg649
	%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
	%vreg652<def> = COPY %vreg651:sub0; VReg_32:%vreg652 VReg_64:%vreg651
	%vreg653<def> = COPY %vreg205; VReg_64:%vreg653,%vreg205
	%vreg654<def> = COPY %vreg653:sub1; VReg_32:%vreg654 VReg_64:%vreg653
	%vreg640<def> = V_ADD_I32_e32 %vreg648, %vreg652, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
	%vreg641<def> = V_ADDC_U32_e32 %vreg650, %vreg654, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
	%vreg642<def> = REG_SEQUENCE %vreg640, sub0, %vreg641, sub1; VReg_64:%vreg642 VReg_32:%vreg640,%vreg641
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
	%vreg773<def> = COPY %vreg772:sub0; VReg_32:%vreg773 VReg_128:%vreg772
	%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
	%vreg775<def> = COPY %vreg774:sub1; VReg_32:%vreg775 VReg_128:%vreg774
	%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
	%vreg777<def> = COPY %vreg776:sub0; VReg_32:%vreg777 VReg_64:%vreg776
	%vreg778<def> = COPY %vreg207; VReg_64:%vreg778,%vreg207
	%vreg779<def> = COPY %vreg778:sub1; VReg_32:%vreg779 VReg_64:%vreg778
	%vreg765<def> = V_ADD_I32_e32 %vreg773, %vreg777, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
	%vreg766<def> = V_ADDC_U32_e32 %vreg775, %vreg779, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
	%vreg767<def> = REG_SEQUENCE %vreg765, sub0, %vreg766, sub1; VReg_64:%vreg767 VReg_32:%vreg765,%vreg766
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211<def> = REG_SEQUENCE %vreg210, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
	%vreg633<def> = COPY %vreg632:sub0; VReg_32:%vreg633 VReg_128:%vreg632
	%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
	%vreg635<def> = COPY %vreg634:sub1; VReg_32:%vreg635 VReg_128:%vreg634
	%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
	%vreg637<def> = COPY %vreg636:sub0; VReg_32:%vreg637 VReg_64:%vreg636
	%vreg638<def> = COPY %vreg213; VReg_64:%vreg638,%vreg213
	%vreg639<def> = COPY %vreg638:sub1; VReg_32:%vreg639 VReg_64:%vreg638
	%vreg625<def> = V_ADD_I32_e32 %vreg633, %vreg637, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
	%vreg626<def> = V_ADDC_U32_e32 %vreg635, %vreg639, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
	%vreg627<def> = REG_SEQUENCE %vreg625, sub0, %vreg626, sub1; VReg_64:%vreg627 VReg_32:%vreg625,%vreg626
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
	%vreg758<def> = COPY %vreg757:sub0; VReg_32:%vreg758 VReg_128:%vreg757
	%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
	%vreg760<def> = COPY %vreg759:sub1; VReg_32:%vreg760 VReg_128:%vreg759
	%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
	%vreg762<def> = COPY %vreg761:sub0; VReg_32:%vreg762 VReg_64:%vreg761
	%vreg763<def> = COPY %vreg215; VReg_64:%vreg763,%vreg215
	%vreg764<def> = COPY %vreg763:sub1; VReg_32:%vreg764 VReg_64:%vreg763
	%vreg750<def> = V_ADD_I32_e32 %vreg758, %vreg762, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
	%vreg751<def> = V_ADDC_U32_e32 %vreg760, %vreg764, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
	%vreg752<def> = REG_SEQUENCE %vreg750, sub0, %vreg751, sub1; VReg_64:%vreg752 VReg_32:%vreg750,%vreg751
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219<def> = REG_SEQUENCE %vreg218, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
	%vreg618<def> = COPY %vreg617:sub0; VReg_32:%vreg618 VReg_128:%vreg617
	%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
	%vreg620<def> = COPY %vreg619:sub1; VReg_32:%vreg620 VReg_128:%vreg619
	%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
	%vreg622<def> = COPY %vreg621:sub0; VReg_32:%vreg622 VReg_64:%vreg621
	%vreg623<def> = COPY %vreg221; VReg_64:%vreg623,%vreg221
	%vreg624<def> = COPY %vreg623:sub1; VReg_32:%vreg624 VReg_64:%vreg623
	%vreg610<def> = V_ADD_I32_e32 %vreg618, %vreg622, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
	%vreg611<def> = V_ADDC_U32_e32 %vreg620, %vreg624, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
	%vreg612<def> = REG_SEQUENCE %vreg610, sub0, %vreg611, sub1; VReg_64:%vreg612 VReg_32:%vreg610,%vreg611
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
	%vreg743<def> = COPY %vreg742:sub0; VReg_32:%vreg743 VReg_128:%vreg742
	%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
	%vreg745<def> = COPY %vreg744:sub1; VReg_32:%vreg745 VReg_128:%vreg744
	%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
	%vreg747<def> = COPY %vreg746:sub0; VReg_32:%vreg747 VReg_64:%vreg746
	%vreg748<def> = COPY %vreg223; VReg_64:%vreg748,%vreg223
	%vreg749<def> = COPY %vreg748:sub1; VReg_32:%vreg749 VReg_64:%vreg748
	%vreg735<def> = V_ADD_I32_e32 %vreg743, %vreg747, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
	%vreg736<def> = V_ADDC_U32_e32 %vreg745, %vreg749, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
	%vreg737<def> = REG_SEQUENCE %vreg735, sub0, %vreg736, sub1; VReg_64:%vreg737 VReg_32:%vreg735,%vreg736
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227<def> = REG_SEQUENCE %vreg226, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
	%vreg603<def> = COPY %vreg602:sub0; VReg_32:%vreg603 VReg_128:%vreg602
	%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
	%vreg605<def> = COPY %vreg604:sub1; VReg_32:%vreg605 VReg_128:%vreg604
	%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
	%vreg607<def> = COPY %vreg606:sub0; VReg_32:%vreg607 VReg_64:%vreg606
	%vreg608<def> = COPY %vreg229; VReg_64:%vreg608,%vreg229
	%vreg609<def> = COPY %vreg608:sub1; VReg_32:%vreg609 VReg_64:%vreg608
	%vreg595<def> = V_ADD_I32_e32 %vreg603, %vreg607, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
	%vreg596<def> = V_ADDC_U32_e32 %vreg605, %vreg609, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
	%vreg597<def> = REG_SEQUENCE %vreg595, sub0, %vreg596, sub1; VReg_64:%vreg597 VReg_32:%vreg595,%vreg596
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
	%vreg728<def> = COPY %vreg727:sub0; VReg_32:%vreg728 VReg_128:%vreg727
	%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
	%vreg730<def> = COPY %vreg729:sub1; VReg_32:%vreg730 VReg_128:%vreg729
	%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
	%vreg732<def> = COPY %vreg731:sub0; VReg_32:%vreg732 VReg_64:%vreg731
	%vreg733<def> = COPY %vreg231; VReg_64:%vreg733,%vreg231
	%vreg734<def> = COPY %vreg733:sub1; VReg_32:%vreg734 VReg_64:%vreg733
	%vreg720<def> = V_ADD_I32_e32 %vreg728, %vreg732, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
	%vreg721<def> = V_ADDC_U32_e32 %vreg730, %vreg734, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
	%vreg722<def> = REG_SEQUENCE %vreg720, sub0, %vreg721, sub1; VReg_64:%vreg722 VReg_32:%vreg720,%vreg721
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235<def> = REG_SEQUENCE %vreg234, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
	%vreg588<def> = COPY %vreg587:sub0; VReg_32:%vreg588 VReg_128:%vreg587
	%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
	%vreg590<def> = COPY %vreg589:sub1; VReg_32:%vreg590 VReg_128:%vreg589
	%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
	%vreg592<def> = COPY %vreg591:sub0; VReg_32:%vreg592 VReg_64:%vreg591
	%vreg593<def> = COPY %vreg237; VReg_64:%vreg593,%vreg237
	%vreg594<def> = COPY %vreg593:sub1; VReg_32:%vreg594 VReg_64:%vreg593
	%vreg580<def> = V_ADD_I32_e32 %vreg588, %vreg592, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
	%vreg581<def> = V_ADDC_U32_e32 %vreg590, %vreg594, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
	%vreg582<def> = REG_SEQUENCE %vreg580, sub0, %vreg581, sub1; VReg_64:%vreg582 VReg_32:%vreg580,%vreg581
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
	%vreg713<def> = COPY %vreg712:sub0; VReg_32:%vreg713 VReg_128:%vreg712
	%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
	%vreg715<def> = COPY %vreg714:sub1; VReg_32:%vreg715 VReg_128:%vreg714
	%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
	%vreg717<def> = COPY %vreg716:sub0; VReg_32:%vreg717 VReg_64:%vreg716
	%vreg718<def> = COPY %vreg239; VReg_64:%vreg718,%vreg239
	%vreg719<def> = COPY %vreg718:sub1; VReg_32:%vreg719 VReg_64:%vreg718
	%vreg705<def> = V_ADD_I32_e32 %vreg713, %vreg717, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
	%vreg706<def> = V_ADDC_U32_e32 %vreg715, %vreg719, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
	%vreg707<def> = REG_SEQUENCE %vreg705, sub0, %vreg706, sub1; VReg_64:%vreg707 VReg_32:%vreg705,%vreg706
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243<def> = REG_SEQUENCE %vreg242, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
	%vreg573<def> = COPY %vreg572:sub0; VReg_32:%vreg573 VReg_128:%vreg572
	%vreg574<def> = COPY %vreg562; VReg_128:%vreg574,%vreg562
	%vreg575<def> = COPY %vreg574:sub1; VReg_32:%vreg575 VReg_128:%vreg574
	%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
	%vreg577<def> = COPY %vreg576:sub0; VReg_32:%vreg577 VReg_64:%vreg576
	%vreg578<def> = COPY %vreg245; VReg_64:%vreg578,%vreg245
	%vreg579<def> = COPY %vreg578:sub1; VReg_32:%vreg579 VReg_64:%vreg578
	%vreg565<def> = V_ADD_I32_e32 %vreg573, %vreg577, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
	%vreg566<def> = V_ADDC_U32_e32 %vreg575, %vreg579, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
	%vreg567<def> = REG_SEQUENCE %vreg565, sub0, %vreg566, sub1; VReg_64:%vreg567 VReg_32:%vreg565,%vreg566
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
	%vreg698<def> = COPY %vreg697:sub0; VReg_32:%vreg698 VReg_128:%vreg697
	%vreg699<def> = COPY %vreg687; VReg_128:%vreg699,%vreg687
	%vreg700<def> = COPY %vreg699:sub1; VReg_32:%vreg700 VReg_128:%vreg699
	%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
	%vreg702<def> = COPY %vreg701:sub0; VReg_32:%vreg702 VReg_64:%vreg701
	%vreg703<def> = COPY %vreg247; VReg_64:%vreg703,%vreg247
	%vreg704<def> = COPY %vreg703:sub1; VReg_32:%vreg704 VReg_64:%vreg703
	%vreg690<def> = V_ADD_I32_e32 %vreg698, %vreg702, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
	%vreg691<def> = V_ADDC_U32_e32 %vreg700, %vreg704, %VCC<imp-def>, %VCC<imp-use>, %VCC<imp-def>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
	%vreg692<def> = REG_SEQUENCE %vreg690, sub0, %vreg691, sub1; VReg_64:%vreg692 VReg_32:%vreg690,%vreg691
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg816<def> = COPY %vreg23:sub1; VReg_32:%vreg816 VReg_64:%vreg23
	%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
	%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
	%vreg817<def> = V_ADDC_U32_e32 %vreg816<kill>, %vreg818, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg817,%vreg816,%vreg818
	%vreg812<def> = REG_SEQUENCE %vreg811, sub0, %vreg817, sub1; VReg_64:%vreg812 VReg_32:%vreg811,%vreg817
	%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
	%vreg825<def> = COPY %vreg24:sub1; VReg_32:%vreg825 VReg_64:%vreg24
	%vreg820<def> = V_ADD_I32_e32 %vreg284, %vreg819<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
	%vreg827<def> = COPY %vreg286; VReg_32:%vreg827 SReg_32:%vreg286
	%vreg826<def> = V_ADDC_U32_e32 %vreg825<kill>, %vreg827, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg826,%vreg825,%vreg827
	%vreg821<def> = REG_SEQUENCE %vreg820, sub0, %vreg826, sub1; VReg_64:%vreg821 VReg_32:%vreg820,%vreg826
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg545<def> = V_ADD_I32_e32 16, %vreg542, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg545,%vreg542
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg815<def> = COPY %vreg812; VReg_64:%vreg815,%vreg812
	%vreg824<def> = COPY %vreg821; VReg_64:%vreg824,%vreg821
	%vreg27<def> = COPY %vreg282; VGPR_32:%vreg27,%vreg282
	%vreg544<def> = COPY %vreg545; VReg_32:%vreg544,%vreg545
	SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg20, <BB#5>, %vreg38, <BB#11>; VGPR_32:%vreg32,%vreg20,%vreg38
	SI_END_CF %vreg302, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg302
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 SGPR_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg833, <BB#10>; VReg_64:%vreg34,%vreg19,%vreg833
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg842, <BB#10>; VReg_64:%vreg35,%vreg18,%vreg842
	%vreg455<def> = PHI %vreg456, <BB#6>, %vreg457, <BB#10>; VReg_32:%vreg455,%vreg456,%vreg457
	%vreg37<def> = PHI %vreg20, <BB#6>, %vreg38, <BB#10>; VGPR_32:%vreg37,%vreg20,%vreg38
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
	%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
	%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
	%vreg835<def> = V_ADDC_U32_e32 %vreg834<kill>, %vreg836, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg835,%vreg834,%vreg836
	%vreg830<def> = REG_SEQUENCE %vreg829, sub0, %vreg835, sub1; VReg_64:%vreg830 VReg_32:%vreg829,%vreg835
	%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
	%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
	%vreg838<def> = V_ADD_I32_e32 %vreg354, %vreg837<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
	%vreg845<def> = COPY %vreg356; VReg_32:%vreg845 SReg_32:%vreg356
	%vreg844<def> = V_ADDC_U32_e32 %vreg843<kill>, %vreg845, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg844,%vreg843,%vreg845
	%vreg839<def> = REG_SEQUENCE %vreg838, sub0, %vreg844, sub1; VReg_64:%vreg839 VReg_32:%vreg838,%vreg844
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg352, sub0_sub1, %vreg411, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg352,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
	%vreg458<def> = V_ADD_I32_e32 -1, %vreg455, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg458,%vreg455
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg833<def> = COPY %vreg830; VReg_64:%vreg833,%vreg830
	%vreg842<def> = COPY %vreg839; VReg_64:%vreg842,%vreg839
	%vreg38<def> = COPY %vreg370; VGPR_32:%vreg38,%vreg370
	%vreg457<def> = COPY %vreg458; VReg_32:%vreg457,%vreg458
	SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
	%vreg424<def> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg424,%vreg374,%vreg423
	%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
	%vreg425<def> = REG_SEQUENCE %vreg424, sub0, %vreg437, sub1; VReg_64:%vreg425 VReg_32:%vreg424,%vreg437
	%vreg428<def> = V_LSHL_B64 %vreg425<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
	%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
	%vreg429<def> = COPY %vreg428:sub1; VReg_32:%vreg429 VReg_64:%vreg428
	%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
	%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
	%vreg436<def> = V_ADD_I32_e32 %vreg847<kill>, %vreg435<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
	%vreg430<def> = V_ADDC_U32_e32 %vreg848, %vreg429<kill>, %VCC<imp-use>, %VCC<imp-def>; VReg_32:%vreg430,%vreg848,%vreg429
	%vreg432<def> = REG_SEQUENCE %vreg436, sub0, %vreg430, sub1; VReg_64:%vreg432 VReg_32:%vreg436,%vreg430
	%vreg388<def> = V_MUL_F32_e64 %vreg32, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg32,%vreg56
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg45<def> = COPY %vreg432; VReg_64:%vreg45,%vreg432
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg393<tied0>, <BB#16>, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg393
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417, sub0, %vreg416, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414, sub0_sub1, %vreg415, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421, sub0, %vreg420, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418, sub0_sub1, %vreg419, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg395, %EXEC<imp-def,dead>, %EXEC<imp-use>; SReg_64:%vreg395
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Eliminate PHI nodes for register allocation ***:
# Machine code for function svm_rbf: SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2<kill>; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0<kill>; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3<kill>; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1<kill>; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1<kill>; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg423<def> = V_ADD_I32_e32 %vreg63<kill>, %vreg59, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg59
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66<kill>; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg440<def> = V_ADD_I32_e32 %vreg71<kill>, %vreg57, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg57
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74<kill>; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48<kill>, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg442<def> = COPY %vreg57<kill>; VReg_32:%vreg442,%vreg57
	%vreg4<def> = COPY %vreg58<kill>; SReg_32:%vreg4,%vreg58
	%vreg445<def> = COPY %vreg59<kill>; VReg_32:%vreg445,%vreg59
	%vreg0<def> = COPY %vreg60<kill>; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70<kill>; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62<kill>; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg55<def> = COPY %vreg79<kill>; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg52<def> = COPY %vreg82<kill>; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83<kill>; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84<kill>; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85<kill>; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg448<def> = COPY %vreg90<kill>; VReg_32:%vreg448,%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91<kill>; VGPR_32:%vreg87,%vreg91
	%vreg450<def> = COPY %vreg448<kill>; VReg_32:%vreg450,%vreg448
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg443<def> = V_ADD_I32_e32 %vreg97<kill>, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg443<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg443
	%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg101, %EXEC<imp-use>; VReg_32:%vreg497,%vreg101
	%vreg104<def> = REG_SEQUENCE %vreg101<kill>, sub0, %vreg497<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101,%vreg497
	%vreg499<def> = V_LSHL_B64 %vreg104<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
	%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
	%vreg500<def> = COPY %vreg499:sub1<kill>; VReg_32:%vreg500 VReg_64:%vreg499
	%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
	%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
	%vreg515<def> = V_ADD_I32_e32 %vreg516<kill>, %vreg514<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
	%vreg501<def> = V_ADDC_U32_e32 %vreg500<kill>, %vreg517<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg501,%vreg500,%vreg517
	%vreg503<def> = REG_SEQUENCE %vreg515<kill>, sub0, %vreg501<kill>, sub1; VReg_64:%vreg503 VReg_32:%vreg515,%vreg501
	%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
	%vreg506<def> = COPY %vreg503:sub1<kill>; VReg_32:%vreg506 VReg_64:%vreg503
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1<kill>; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
	%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
	%vreg507<def> = V_ADDC_U32_e32 %vreg506<kill>, %vreg508<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg507,%vreg506,%vreg508
	%vreg509<def> = REG_SEQUENCE %vreg513<kill>, sub0, %vreg507<kill>, sub1; VReg_64:%vreg509 VReg_32:%vreg513,%vreg507
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg446<def> = V_ADD_I32_e32 %vreg123<kill>, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg446<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg446
	%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg127, %EXEC<imp-use>; VReg_32:%vreg520,%vreg127
	%vreg130<def> = REG_SEQUENCE %vreg127<kill>, sub0, %vreg520<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127,%vreg520
	%vreg522<def> = V_LSHL_B64 %vreg130<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
	%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
	%vreg523<def> = COPY %vreg522:sub1<kill>; VReg_32:%vreg523 VReg_64:%vreg522
	%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
	%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
	%vreg538<def> = V_ADD_I32_e32 %vreg539<kill>, %vreg537<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
	%vreg524<def> = V_ADDC_U32_e32 %vreg523<kill>, %vreg540<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg524,%vreg523,%vreg540
	%vreg526<def> = REG_SEQUENCE %vreg538<kill>, sub0, %vreg524<kill>, sub1; VReg_64:%vreg526 VReg_32:%vreg538,%vreg524
	%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
	%vreg529<def> = COPY %vreg526:sub1<kill>; VReg_32:%vreg529 VReg_64:%vreg526
	%vreg536<def> = V_ADD_I32_e32 %vreg117<kill>, %vreg535<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
	%vreg531<def> = COPY %vreg118<kill>; VReg_32:%vreg531 SReg_32:%vreg118
	%vreg530<def> = V_ADDC_U32_e32 %vreg529<kill>, %vreg531<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg530,%vreg529,%vreg531
	%vreg532<def> = REG_SEQUENCE %vreg536<kill>, sub0, %vreg530<kill>, sub1; VReg_64:%vreg532 VReg_32:%vreg536,%vreg530
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145<kill>; VGPR_32:%vreg95,%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg541<def> = COPY %vreg146<kill>; VReg_32:%vreg541,%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
	%vreg12<def> = COPY %vreg509<kill>; VReg_64:%vreg12,%vreg509
	%vreg11<def> = COPY %vreg532<kill>; VReg_64:%vreg11,%vreg532
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg543<def> = COPY %vreg541<kill>; VReg_32:%vreg543,%vreg541
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	%vreg451<def> = COPY %vreg13<kill>; VReg_32:%vreg451 SReg_32:%vreg13
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg86<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg453, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg453 VGPR_32:%vreg300
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4<kill>; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5<kill>, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg444<def> = V_ADD_I32_e32 %vreg305<kill>, %vreg442<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
	%vreg309<def> = V_MUL_LO_I32 %vreg50<kill>, %vreg444<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg444
	%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg309, %EXEC<imp-use>; VReg_32:%vreg548,%vreg309
	%vreg312<def> = REG_SEQUENCE %vreg309<kill>, sub0, %vreg548<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309,%vreg548
	%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
	%vreg550<def> = COPY %vreg312:sub1<kill>; VReg_32:%vreg550 VReg_64:%vreg312
	%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg453, %EXEC<imp-use>; VReg_32:%vreg494,%vreg453
	%vreg459<def> = REG_SEQUENCE %vreg453, sub0, %vreg494<kill>, sub1; VReg_64:%vreg459 VReg_32:%vreg453,%vreg494
	%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
	%vreg462<def> = COPY %vreg459:sub1<kill>; VReg_32:%vreg462 VReg_64:%vreg459
	%vreg493<def> = V_ADD_I32_e32 %vreg549<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
	%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg550<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg477,%vreg462,%vreg550
	%vreg479<def> = REG_SEQUENCE %vreg493<kill>, sub0, %vreg477<kill>, sub1; VReg_64:%vreg479 VReg_32:%vreg493,%vreg477
	%vreg482<def> = V_LSHL_B64 %vreg479<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
	%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
	%vreg483<def> = COPY %vreg482:sub1<kill>; VReg_32:%vreg483 VReg_64:%vreg482
	%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
	%vreg552<def> = COPY %vreg49:sub1<kill>; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
	%vreg490<def> = V_ADD_I32_e32 %vreg551<kill>, %vreg489<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
	%vreg484<def> = V_ADDC_U32_e32 %vreg552<kill>, %vreg483<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg484,%vreg552,%vreg483
	%vreg486<def> = REG_SEQUENCE %vreg490<kill>, sub0, %vreg484<kill>, sub1; VReg_64:%vreg486 VReg_32:%vreg490,%vreg484
	%vreg330<def> = COPY %vreg0<kill>; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1<kill>, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg447<def> = V_ADD_I32_e32 %vreg331<kill>, %vreg445<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
	%vreg335<def> = V_MUL_LO_I32 %vreg52<kill>, %vreg447<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg447
	%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg335, %EXEC<imp-use>; VReg_32:%vreg555,%vreg335
	%vreg338<def> = REG_SEQUENCE %vreg335<kill>, sub0, %vreg555<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335,%vreg555
	%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
	%vreg557<def> = COPY %vreg338:sub1<kill>; VReg_32:%vreg557 VReg_64:%vreg338
	%vreg492<def> = V_ADD_I32_e32 %vreg556<kill>, %vreg491<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
	%vreg463<def> = V_ADDC_U32_e32 %vreg462<kill>, %vreg557<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg463,%vreg462,%vreg557
	%vreg465<def> = REG_SEQUENCE %vreg492<kill>, sub0, %vreg463<kill>, sub1; VReg_64:%vreg465 VReg_32:%vreg492,%vreg463
	%vreg468<def> = V_LSHL_B64 %vreg465<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
	%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
	%vreg469<def> = COPY %vreg468:sub1<kill>; VReg_32:%vreg469 VReg_64:%vreg468
	%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
	%vreg559<def> = COPY %vreg51:sub1<kill>; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
	%vreg476<def> = V_ADD_I32_e32 %vreg558<kill>, %vreg475<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
	%vreg470<def> = V_ADDC_U32_e32 %vreg559<kill>, %vreg469<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg470,%vreg559,%vreg469
	%vreg472<def> = REG_SEQUENCE %vreg476<kill>, sub0, %vreg470<kill>, sub1; VReg_64:%vreg472 VReg_32:%vreg476,%vreg470
	%vreg454<def> = V_SUB_I32_e32 %vreg55<kill>, %vreg453<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg454,%vreg453 SReg_32:%vreg55
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
	%vreg19<def> = COPY %vreg486<kill>; VReg_64:%vreg19,%vreg486
	%vreg18<def> = COPY %vreg472<kill>; VReg_64:%vreg18,%vreg472
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg456<def> = COPY %vreg454<kill>; VReg_32:%vreg456,%vreg454
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg20<def> = PHI %vreg87, <BB#1>, %vreg27, <BB#3>; VGPR_32:%vreg20,%vreg87,%vreg27
	%vreg449<def> = PHI %vreg450, <BB#1>, %vreg451, <BB#3>; VReg_32:%vreg449,%vreg450,%vreg451
	%vreg56<def> = COPY %vreg78<kill>; VGPR_32:%vreg56 SGPR_32:%vreg78
	%vreg54<def> = COPY %vreg80<kill>; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81<kill>; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	SI_END_CF %vreg92<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
	%vreg453<def> = COPY %vreg449<kill>; VReg_32:%vreg453,%vreg449
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg22<def> = PHI %vreg93, <BB#2>, %vreg31, <BB#8>; SReg_64:%vreg22,%vreg31 SGPR_64:%vreg93
	%vreg23<def> = PHI %vreg12, <BB#2>, %vreg815, <BB#8>; VReg_64:%vreg23,%vreg12,%vreg815
	%vreg24<def> = PHI %vreg11, <BB#2>, %vreg824, <BB#8>; VReg_64:%vreg24,%vreg11,%vreg824
	%vreg542<def> = PHI %vreg543, <BB#2>, %vreg544, <BB#8>; VReg_32:%vreg542,%vreg543,%vreg544
	%vreg26<def> = PHI %vreg95, <BB#2>, %vreg27, <BB#8>; VGPR_32:%vreg26,%vreg95,%vreg27
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg147,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151<kill>, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155<kill>, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159<kill>, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163<kill>, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167<kill>, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171<kill>, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175<kill>, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148<kill>, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179<kill>, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183<def> = REG_SEQUENCE %vreg182, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
	%vreg561<def> = COPY %vreg560<kill>; VReg_64:%vreg561,%vreg560
	%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
	%vreg562<def> = REG_SEQUENCE %vreg561<kill>, sub0_sub1, %vreg564<kill>, sub2_sub3; VReg_128:%vreg562 VReg_64:%vreg561,%vreg564
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
	%vreg678<def> = COPY %vreg677:sub0<kill>; VReg_32:%vreg678 VReg_128:%vreg677
	%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
	%vreg680<def> = COPY %vreg679:sub1<kill>; VReg_32:%vreg680 VReg_128:%vreg679
	%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
	%vreg682<def> = COPY %vreg681:sub0<kill>; VReg_32:%vreg682 VReg_64:%vreg681
	%vreg683<def> = COPY %vreg187<kill>; VReg_64:%vreg683,%vreg187
	%vreg684<def> = COPY %vreg683:sub1<kill>; VReg_32:%vreg684 VReg_64:%vreg683
	%vreg670<def> = V_ADD_I32_e32 %vreg678<kill>, %vreg682<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
	%vreg671<def> = V_ADDC_U32_e32 %vreg680<kill>, %vreg684<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
	%vreg672<def> = REG_SEQUENCE %vreg670<kill>, sub0, %vreg671<kill>, sub1; VReg_64:%vreg672 VReg_32:%vreg670,%vreg671
	%vreg676<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg401, sub2, %vreg400, sub3; SReg_128:%vreg676 SGPR_64:%vreg147 SGPR_32:%vreg401,%vreg400
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
	%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
	%vreg686<def> = COPY %vreg685<kill>; VReg_64:%vreg686,%vreg685
	%vreg689<def> = COPY %vreg399<kill>; VReg_64:%vreg689 SGPR_64:%vreg399
	%vreg687<def> = REG_SEQUENCE %vreg686<kill>, sub0_sub1, %vreg689<kill>, sub2_sub3; VReg_128:%vreg687 VReg_64:%vreg686,%vreg689
	%vreg191<def> = COPY %vreg183<kill>; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
	%vreg803<def> = COPY %vreg802:sub0<kill>; VReg_32:%vreg803 VReg_128:%vreg802
	%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
	%vreg805<def> = COPY %vreg804:sub1<kill>; VReg_32:%vreg805 VReg_128:%vreg804
	%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
	%vreg807<def> = COPY %vreg806:sub0<kill>; VReg_32:%vreg807 VReg_64:%vreg806
	%vreg808<def> = COPY %vreg191<kill>; VReg_64:%vreg808,%vreg191
	%vreg809<def> = COPY %vreg808:sub1<kill>; VReg_32:%vreg809 VReg_64:%vreg808
	%vreg795<def> = V_ADD_I32_e32 %vreg803<kill>, %vreg807<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
	%vreg796<def> = V_ADDC_U32_e32 %vreg805<kill>, %vreg809<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
	%vreg797<def> = REG_SEQUENCE %vreg795<kill>, sub0, %vreg796<kill>, sub1; VReg_64:%vreg797 VReg_32:%vreg795,%vreg796
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192<kill>, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195<def> = REG_SEQUENCE %vreg194, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
	%vreg663<def> = COPY %vreg662:sub0<kill>; VReg_32:%vreg663 VReg_128:%vreg662
	%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
	%vreg665<def> = COPY %vreg664:sub1<kill>; VReg_32:%vreg665 VReg_128:%vreg664
	%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
	%vreg667<def> = COPY %vreg666:sub0<kill>; VReg_32:%vreg667 VReg_64:%vreg666
	%vreg668<def> = COPY %vreg197<kill>; VReg_64:%vreg668,%vreg197
	%vreg669<def> = COPY %vreg668:sub1<kill>; VReg_32:%vreg669 VReg_64:%vreg668
	%vreg655<def> = V_ADD_I32_e32 %vreg663<kill>, %vreg667<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
	%vreg656<def> = V_ADDC_U32_e32 %vreg665<kill>, %vreg669<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
	%vreg657<def> = REG_SEQUENCE %vreg655<kill>, sub0, %vreg656<kill>, sub1; VReg_64:%vreg657 VReg_32:%vreg655,%vreg656
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
	%vreg199<def> = COPY %vreg195<kill>; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
	%vreg788<def> = COPY %vreg787:sub0<kill>; VReg_32:%vreg788 VReg_128:%vreg787
	%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
	%vreg790<def> = COPY %vreg789:sub1<kill>; VReg_32:%vreg790 VReg_128:%vreg789
	%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
	%vreg792<def> = COPY %vreg791:sub0<kill>; VReg_32:%vreg792 VReg_64:%vreg791
	%vreg793<def> = COPY %vreg199<kill>; VReg_64:%vreg793,%vreg199
	%vreg794<def> = COPY %vreg793:sub1<kill>; VReg_32:%vreg794 VReg_64:%vreg793
	%vreg780<def> = V_ADD_I32_e32 %vreg788<kill>, %vreg792<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
	%vreg781<def> = V_ADDC_U32_e32 %vreg790<kill>, %vreg794<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
	%vreg782<def> = REG_SEQUENCE %vreg780<kill>, sub0, %vreg781<kill>, sub1; VReg_64:%vreg782 VReg_32:%vreg780,%vreg781
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200<kill>, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203<def> = REG_SEQUENCE %vreg202, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
	%vreg648<def> = COPY %vreg647:sub0<kill>; VReg_32:%vreg648 VReg_128:%vreg647
	%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
	%vreg650<def> = COPY %vreg649:sub1<kill>; VReg_32:%vreg650 VReg_128:%vreg649
	%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
	%vreg652<def> = COPY %vreg651:sub0<kill>; VReg_32:%vreg652 VReg_64:%vreg651
	%vreg653<def> = COPY %vreg205<kill>; VReg_64:%vreg653,%vreg205
	%vreg654<def> = COPY %vreg653:sub1<kill>; VReg_32:%vreg654 VReg_64:%vreg653
	%vreg640<def> = V_ADD_I32_e32 %vreg648<kill>, %vreg652<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
	%vreg641<def> = V_ADDC_U32_e32 %vreg650<kill>, %vreg654<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
	%vreg642<def> = REG_SEQUENCE %vreg640<kill>, sub0, %vreg641<kill>, sub1; VReg_64:%vreg642 VReg_32:%vreg640,%vreg641
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
	%vreg207<def> = COPY %vreg203<kill>; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
	%vreg773<def> = COPY %vreg772:sub0<kill>; VReg_32:%vreg773 VReg_128:%vreg772
	%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
	%vreg775<def> = COPY %vreg774:sub1<kill>; VReg_32:%vreg775 VReg_128:%vreg774
	%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
	%vreg777<def> = COPY %vreg776:sub0<kill>; VReg_32:%vreg777 VReg_64:%vreg776
	%vreg778<def> = COPY %vreg207<kill>; VReg_64:%vreg778,%vreg207
	%vreg779<def> = COPY %vreg778:sub1<kill>; VReg_32:%vreg779 VReg_64:%vreg778
	%vreg765<def> = V_ADD_I32_e32 %vreg773<kill>, %vreg777<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
	%vreg766<def> = V_ADDC_U32_e32 %vreg775<kill>, %vreg779<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
	%vreg767<def> = REG_SEQUENCE %vreg765<kill>, sub0, %vreg766<kill>, sub1; VReg_64:%vreg767 VReg_32:%vreg765,%vreg766
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208<kill>, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211<def> = REG_SEQUENCE %vreg210, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
	%vreg633<def> = COPY %vreg632:sub0<kill>; VReg_32:%vreg633 VReg_128:%vreg632
	%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
	%vreg635<def> = COPY %vreg634:sub1<kill>; VReg_32:%vreg635 VReg_128:%vreg634
	%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
	%vreg637<def> = COPY %vreg636:sub0<kill>; VReg_32:%vreg637 VReg_64:%vreg636
	%vreg638<def> = COPY %vreg213<kill>; VReg_64:%vreg638,%vreg213
	%vreg639<def> = COPY %vreg638:sub1<kill>; VReg_32:%vreg639 VReg_64:%vreg638
	%vreg625<def> = V_ADD_I32_e32 %vreg633<kill>, %vreg637<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
	%vreg626<def> = V_ADDC_U32_e32 %vreg635<kill>, %vreg639<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
	%vreg627<def> = REG_SEQUENCE %vreg625<kill>, sub0, %vreg626<kill>, sub1; VReg_64:%vreg627 VReg_32:%vreg625,%vreg626
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
	%vreg215<def> = COPY %vreg211<kill>; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
	%vreg758<def> = COPY %vreg757:sub0<kill>; VReg_32:%vreg758 VReg_128:%vreg757
	%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
	%vreg760<def> = COPY %vreg759:sub1<kill>; VReg_32:%vreg760 VReg_128:%vreg759
	%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
	%vreg762<def> = COPY %vreg761:sub0<kill>; VReg_32:%vreg762 VReg_64:%vreg761
	%vreg763<def> = COPY %vreg215<kill>; VReg_64:%vreg763,%vreg215
	%vreg764<def> = COPY %vreg763:sub1<kill>; VReg_32:%vreg764 VReg_64:%vreg763
	%vreg750<def> = V_ADD_I32_e32 %vreg758<kill>, %vreg762<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
	%vreg751<def> = V_ADDC_U32_e32 %vreg760<kill>, %vreg764<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
	%vreg752<def> = REG_SEQUENCE %vreg750<kill>, sub0, %vreg751<kill>, sub1; VReg_64:%vreg752 VReg_32:%vreg750,%vreg751
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216<kill>, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219<def> = REG_SEQUENCE %vreg218, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
	%vreg618<def> = COPY %vreg617:sub0<kill>; VReg_32:%vreg618 VReg_128:%vreg617
	%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
	%vreg620<def> = COPY %vreg619:sub1<kill>; VReg_32:%vreg620 VReg_128:%vreg619
	%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
	%vreg622<def> = COPY %vreg621:sub0<kill>; VReg_32:%vreg622 VReg_64:%vreg621
	%vreg623<def> = COPY %vreg221<kill>; VReg_64:%vreg623,%vreg221
	%vreg624<def> = COPY %vreg623:sub1<kill>; VReg_32:%vreg624 VReg_64:%vreg623
	%vreg610<def> = V_ADD_I32_e32 %vreg618<kill>, %vreg622<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
	%vreg611<def> = V_ADDC_U32_e32 %vreg620<kill>, %vreg624<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
	%vreg612<def> = REG_SEQUENCE %vreg610<kill>, sub0, %vreg611<kill>, sub1; VReg_64:%vreg612 VReg_32:%vreg610,%vreg611
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
	%vreg223<def> = COPY %vreg219<kill>; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
	%vreg743<def> = COPY %vreg742:sub0<kill>; VReg_32:%vreg743 VReg_128:%vreg742
	%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
	%vreg745<def> = COPY %vreg744:sub1<kill>; VReg_32:%vreg745 VReg_128:%vreg744
	%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
	%vreg747<def> = COPY %vreg746:sub0<kill>; VReg_32:%vreg747 VReg_64:%vreg746
	%vreg748<def> = COPY %vreg223<kill>; VReg_64:%vreg748,%vreg223
	%vreg749<def> = COPY %vreg748:sub1<kill>; VReg_32:%vreg749 VReg_64:%vreg748
	%vreg735<def> = V_ADD_I32_e32 %vreg743<kill>, %vreg747<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
	%vreg736<def> = V_ADDC_U32_e32 %vreg745<kill>, %vreg749<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
	%vreg737<def> = REG_SEQUENCE %vreg735<kill>, sub0, %vreg736<kill>, sub1; VReg_64:%vreg737 VReg_32:%vreg735,%vreg736
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224<kill>, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227<def> = REG_SEQUENCE %vreg226, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
	%vreg603<def> = COPY %vreg602:sub0<kill>; VReg_32:%vreg603 VReg_128:%vreg602
	%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
	%vreg605<def> = COPY %vreg604:sub1<kill>; VReg_32:%vreg605 VReg_128:%vreg604
	%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
	%vreg607<def> = COPY %vreg606:sub0<kill>; VReg_32:%vreg607 VReg_64:%vreg606
	%vreg608<def> = COPY %vreg229<kill>; VReg_64:%vreg608,%vreg229
	%vreg609<def> = COPY %vreg608:sub1<kill>; VReg_32:%vreg609 VReg_64:%vreg608
	%vreg595<def> = V_ADD_I32_e32 %vreg603<kill>, %vreg607<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
	%vreg596<def> = V_ADDC_U32_e32 %vreg605<kill>, %vreg609<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
	%vreg597<def> = REG_SEQUENCE %vreg595<kill>, sub0, %vreg596<kill>, sub1; VReg_64:%vreg597 VReg_32:%vreg595,%vreg596
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
	%vreg231<def> = COPY %vreg227<kill>; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
	%vreg728<def> = COPY %vreg727:sub0<kill>; VReg_32:%vreg728 VReg_128:%vreg727
	%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
	%vreg730<def> = COPY %vreg729:sub1<kill>; VReg_32:%vreg730 VReg_128:%vreg729
	%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
	%vreg732<def> = COPY %vreg731:sub0<kill>; VReg_32:%vreg732 VReg_64:%vreg731
	%vreg733<def> = COPY %vreg231<kill>; VReg_64:%vreg733,%vreg231
	%vreg734<def> = COPY %vreg733:sub1<kill>; VReg_32:%vreg734 VReg_64:%vreg733
	%vreg720<def> = V_ADD_I32_e32 %vreg728<kill>, %vreg732<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
	%vreg721<def> = V_ADDC_U32_e32 %vreg730<kill>, %vreg734<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
	%vreg722<def> = REG_SEQUENCE %vreg720<kill>, sub0, %vreg721<kill>, sub1; VReg_64:%vreg722 VReg_32:%vreg720,%vreg721
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232<kill>, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235<def> = REG_SEQUENCE %vreg234, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
	%vreg588<def> = COPY %vreg587:sub0<kill>; VReg_32:%vreg588 VReg_128:%vreg587
	%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
	%vreg590<def> = COPY %vreg589:sub1<kill>; VReg_32:%vreg590 VReg_128:%vreg589
	%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
	%vreg592<def> = COPY %vreg591:sub0<kill>; VReg_32:%vreg592 VReg_64:%vreg591
	%vreg593<def> = COPY %vreg237<kill>; VReg_64:%vreg593,%vreg237
	%vreg594<def> = COPY %vreg593:sub1<kill>; VReg_32:%vreg594 VReg_64:%vreg593
	%vreg580<def> = V_ADD_I32_e32 %vreg588<kill>, %vreg592<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
	%vreg581<def> = V_ADDC_U32_e32 %vreg590<kill>, %vreg594<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
	%vreg582<def> = REG_SEQUENCE %vreg580<kill>, sub0, %vreg581<kill>, sub1; VReg_64:%vreg582 VReg_32:%vreg580,%vreg581
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
	%vreg239<def> = COPY %vreg235<kill>; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
	%vreg713<def> = COPY %vreg712:sub0<kill>; VReg_32:%vreg713 VReg_128:%vreg712
	%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
	%vreg715<def> = COPY %vreg714:sub1<kill>; VReg_32:%vreg715 VReg_128:%vreg714
	%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
	%vreg717<def> = COPY %vreg716:sub0<kill>; VReg_32:%vreg717 VReg_64:%vreg716
	%vreg718<def> = COPY %vreg239<kill>; VReg_64:%vreg718,%vreg239
	%vreg719<def> = COPY %vreg718:sub1<kill>; VReg_32:%vreg719 VReg_64:%vreg718
	%vreg705<def> = V_ADD_I32_e32 %vreg713<kill>, %vreg717<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
	%vreg706<def> = V_ADDC_U32_e32 %vreg715<kill>, %vreg719<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
	%vreg707<def> = REG_SEQUENCE %vreg705<kill>, sub0, %vreg706<kill>, sub1; VReg_64:%vreg707 VReg_32:%vreg705,%vreg706
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240<kill>, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243<def> = REG_SEQUENCE %vreg242, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
	%vreg573<def> = COPY %vreg572:sub0<kill>; VReg_32:%vreg573 VReg_128:%vreg572
	%vreg574<def> = COPY %vreg562<kill>; VReg_128:%vreg574,%vreg562
	%vreg575<def> = COPY %vreg574:sub1<kill>; VReg_32:%vreg575 VReg_128:%vreg574
	%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
	%vreg577<def> = COPY %vreg576:sub0<kill>; VReg_32:%vreg577 VReg_64:%vreg576
	%vreg578<def> = COPY %vreg245<kill>; VReg_64:%vreg578,%vreg245
	%vreg579<def> = COPY %vreg578:sub1<kill>; VReg_32:%vreg579 VReg_64:%vreg578
	%vreg565<def> = V_ADD_I32_e32 %vreg573<kill>, %vreg577<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
	%vreg566<def> = V_ADDC_U32_e32 %vreg575<kill>, %vreg579<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
	%vreg567<def> = REG_SEQUENCE %vreg565<kill>, sub0, %vreg566<kill>, sub1; VReg_64:%vreg567 VReg_32:%vreg565,%vreg566
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
	%vreg247<def> = COPY %vreg243<kill>; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
	%vreg698<def> = COPY %vreg697:sub0<kill>; VReg_32:%vreg698 VReg_128:%vreg697
	%vreg699<def> = COPY %vreg687<kill>; VReg_128:%vreg699,%vreg687
	%vreg700<def> = COPY %vreg699:sub1<kill>; VReg_32:%vreg700 VReg_128:%vreg699
	%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
	%vreg702<def> = COPY %vreg701:sub0<kill>; VReg_32:%vreg702 VReg_64:%vreg701
	%vreg703<def> = COPY %vreg247<kill>; VReg_64:%vreg703,%vreg247
	%vreg704<def> = COPY %vreg703:sub1<kill>; VReg_32:%vreg704 VReg_64:%vreg703
	%vreg690<def> = V_ADD_I32_e32 %vreg698<kill>, %vreg702<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
	%vreg691<def> = V_ADDC_U32_e32 %vreg700<kill>, %vreg704<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
	%vreg692<def> = REG_SEQUENCE %vreg690<kill>, sub0, %vreg691<kill>, sub1; VReg_64:%vreg692 VReg_32:%vreg690,%vreg691
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676<kill>, %vreg692<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248<kill>, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15<kill>; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26<kill>, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg816<def> = COPY %vreg23:sub1<kill>; VReg_32:%vreg816 VReg_64:%vreg23
	%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
	%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
	%vreg817<def> = V_ADDC_U32_e32 %vreg816<kill>, %vreg818<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg817,%vreg816,%vreg818
	%vreg812<def> = REG_SEQUENCE %vreg811<kill>, sub0, %vreg817<kill>, sub1; VReg_64:%vreg812 VReg_32:%vreg811,%vreg817
	%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
	%vreg825<def> = COPY %vreg24:sub1<kill>; VReg_32:%vreg825 VReg_64:%vreg24
	%vreg820<def> = V_ADD_I32_e32 %vreg284<kill>, %vreg819<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
	%vreg827<def> = COPY %vreg286<kill>; VReg_32:%vreg827 SReg_32:%vreg286
	%vreg826<def> = V_ADDC_U32_e32 %vreg825<kill>, %vreg827<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg826,%vreg825,%vreg827
	%vreg821<def> = REG_SEQUENCE %vreg820<kill>, sub0, %vreg826<kill>, sub1; VReg_64:%vreg821 VReg_32:%vreg820,%vreg826
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg545<def> = V_ADD_I32_e32 16, %vreg542<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg545,%vreg542
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg815<def> = COPY %vreg812<kill>; VReg_64:%vreg815,%vreg812
	%vreg824<def> = COPY %vreg821<kill>; VReg_64:%vreg824,%vreg821
	%vreg27<def> = COPY %vreg282<kill>; VGPR_32:%vreg27,%vreg282
	%vreg544<def> = COPY %vreg545<kill>; VReg_32:%vreg544,%vreg545
	SI_LOOP %vreg298<kill>, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = PHI %vreg20, <BB#5>, %vreg38, <BB#11>; VGPR_32:%vreg32,%vreg20,%vreg38
	SI_END_CF %vreg302<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg33<def> = PHI %vreg303, <BB#6>, %vreg42, <BB#10>; SReg_64:%vreg33,%vreg42 SGPR_64:%vreg303
	%vreg34<def> = PHI %vreg19, <BB#6>, %vreg833, <BB#10>; VReg_64:%vreg34,%vreg19,%vreg833
	%vreg35<def> = PHI %vreg18, <BB#6>, %vreg842, <BB#10>; VReg_64:%vreg35,%vreg18,%vreg842
	%vreg455<def> = PHI %vreg456, <BB#6>, %vreg457, <BB#10>; VReg_32:%vreg455,%vreg456,%vreg457
	%vreg37<def> = PHI %vreg20, <BB#6>, %vreg38, <BB#10>; VGPR_32:%vreg37,%vreg20,%vreg38
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
	%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
	%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
	%vreg835<def> = V_ADDC_U32_e32 %vreg834<kill>, %vreg836<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg835,%vreg834,%vreg836
	%vreg830<def> = REG_SEQUENCE %vreg829<kill>, sub0, %vreg835<kill>, sub1; VReg_64:%vreg830 VReg_32:%vreg829,%vreg835
	%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
	%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
	%vreg838<def> = V_ADD_I32_e32 %vreg354<kill>, %vreg837<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
	%vreg845<def> = COPY %vreg356<kill>; VReg_32:%vreg845 SReg_32:%vreg356
	%vreg844<def> = V_ADDC_U32_e32 %vreg843<kill>, %vreg845<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg844,%vreg843,%vreg845
	%vreg839<def> = REG_SEQUENCE %vreg838<kill>, sub0, %vreg844<kill>, sub1; VReg_64:%vreg839 VReg_32:%vreg838,%vreg844
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg352, sub0_sub1, %vreg411<kill>, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg352,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366<kill>, %vreg34<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369<kill>, %vreg369, %vreg37<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
	%vreg458<def> = V_ADD_I32_e32 -1, %vreg455<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg458,%vreg455
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg833<def> = COPY %vreg830<kill>; VReg_64:%vreg833,%vreg830
	%vreg842<def> = COPY %vreg839<kill>; VReg_64:%vreg842,%vreg839
	%vreg38<def> = COPY %vreg370<kill>; VGPR_32:%vreg38,%vreg370
	%vreg457<def> = COPY %vreg458<kill>; VReg_32:%vreg457,%vreg458
	SI_LOOP %vreg372<kill>, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg42
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg373<def> = COPY %vreg54<kill>; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg440<kill>, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
	%vreg424<def> = V_ADD_I32_e32 %vreg374<kill>, %vreg423<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg424,%vreg374,%vreg423
	%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
	%vreg425<def> = REG_SEQUENCE %vreg424<kill>, sub0, %vreg437<kill>, sub1; VReg_64:%vreg425 VReg_32:%vreg424,%vreg437
	%vreg428<def> = V_LSHL_B64 %vreg425<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
	%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
	%vreg429<def> = COPY %vreg428:sub1<kill>; VReg_32:%vreg429 VReg_64:%vreg428
	%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
	%vreg848<def> = COPY %vreg53:sub1<kill>; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
	%vreg436<def> = V_ADD_I32_e32 %vreg847<kill>, %vreg435<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
	%vreg430<def> = V_ADDC_U32_e32 %vreg848<kill>, %vreg429<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg430,%vreg848,%vreg429
	%vreg432<def> = REG_SEQUENCE %vreg436<kill>, sub0, %vreg430<kill>, sub1; VReg_64:%vreg432 VReg_32:%vreg436,%vreg430
	%vreg388<def> = V_MUL_F32_e64 %vreg32<kill>, %vreg56<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg32,%vreg56
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg45<def> = COPY %vreg432<kill>; VReg_64:%vreg45,%vreg432
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg393<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg393
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417<kill>, sub0, %vreg416<kill>, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414<kill>, sub0_sub1, %vreg415<kill>, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg44<def> = COPY %vreg388<kill>; VGPR_32:%vreg44,%vreg388
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421<kill>, sub0, %vreg420<kill>, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418<kill>, sub0_sub1, %vreg419<kill>, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44<kill>, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg395<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Two-Address instruction pass ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2<kill>; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0<kill>; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3<kill>; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1<kill>; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1<kill>; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg423<def> = V_ADD_I32_e32 %vreg63<kill>, %vreg59, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg59
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66<kill>; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg440<def> = V_ADD_I32_e32 %vreg71<kill>, %vreg57, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg57
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74<kill>; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48<kill>, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg442<def> = COPY %vreg57<kill>; VReg_32:%vreg442,%vreg57
	%vreg4<def> = COPY %vreg58<kill>; SReg_32:%vreg4,%vreg58
	%vreg445<def> = COPY %vreg59<kill>; VReg_32:%vreg445,%vreg59
	%vreg0<def> = COPY %vreg60<kill>; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70<kill>; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62<kill>; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg55<def> = COPY %vreg79<kill>; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg52<def> = COPY %vreg82<kill>; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83<kill>; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84<kill>; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85<kill>; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg448<def> = COPY %vreg90<kill>; VReg_32:%vreg448,%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91<kill>; VGPR_32:%vreg87,%vreg91
	%vreg450<def> = COPY %vreg448<kill>; VReg_32:%vreg450,%vreg448
	%vreg849<def> = COPY %vreg87<kill>; VGPR_32:%vreg849,%vreg87
	%vreg850<def> = COPY %vreg450<kill>; VReg_32:%vreg850,%vreg450
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg443<def> = V_ADD_I32_e32 %vreg97<kill>, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg443<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg443
	%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg101, %EXEC<imp-use>; VReg_32:%vreg497,%vreg101
	%vreg104<def> = REG_SEQUENCE %vreg101<kill>, sub0, %vreg497<kill>, sub1; VReg_64:%vreg104 VReg_32:%vreg101,%vreg497
	%vreg499<def> = V_LSHL_B64 %vreg104<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
	%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
	%vreg500<def> = COPY %vreg499:sub1<kill>; VReg_32:%vreg500 VReg_64:%vreg499
	%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
	%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
	%vreg515<def> = V_ADD_I32_e32 %vreg516<kill>, %vreg514<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
	%vreg501<def> = V_ADDC_U32_e32 %vreg500<kill>, %vreg517<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg501,%vreg500,%vreg517
	%vreg503<def> = REG_SEQUENCE %vreg515<kill>, sub0, %vreg501<kill>, sub1; VReg_64:%vreg503 VReg_32:%vreg515,%vreg501
	%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
	%vreg506<def> = COPY %vreg503:sub1<kill>; VReg_32:%vreg506 VReg_64:%vreg503
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1<kill>; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
	%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
	%vreg507<def> = V_ADDC_U32_e32 %vreg506<kill>, %vreg508<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg507,%vreg506,%vreg508
	%vreg509<def> = REG_SEQUENCE %vreg513<kill>, sub0, %vreg507<kill>, sub1; VReg_64:%vreg509 VReg_32:%vreg513,%vreg507
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg446<def> = V_ADD_I32_e32 %vreg123<kill>, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg446<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg446
	%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg127, %EXEC<imp-use>; VReg_32:%vreg520,%vreg127
	%vreg130<def> = REG_SEQUENCE %vreg127<kill>, sub0, %vreg520<kill>, sub1; VReg_64:%vreg130 VReg_32:%vreg127,%vreg520
	%vreg522<def> = V_LSHL_B64 %vreg130<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
	%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
	%vreg523<def> = COPY %vreg522:sub1<kill>; VReg_32:%vreg523 VReg_64:%vreg522
	%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
	%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
	%vreg538<def> = V_ADD_I32_e32 %vreg539<kill>, %vreg537<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
	%vreg524<def> = V_ADDC_U32_e32 %vreg523<kill>, %vreg540<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg524,%vreg523,%vreg540
	%vreg526<def> = REG_SEQUENCE %vreg538<kill>, sub0, %vreg524<kill>, sub1; VReg_64:%vreg526 VReg_32:%vreg538,%vreg524
	%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
	%vreg529<def> = COPY %vreg526:sub1<kill>; VReg_32:%vreg529 VReg_64:%vreg526
	%vreg536<def> = V_ADD_I32_e32 %vreg117<kill>, %vreg535<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
	%vreg531<def> = COPY %vreg118<kill>; VReg_32:%vreg531 SReg_32:%vreg118
	%vreg530<def> = V_ADDC_U32_e32 %vreg529<kill>, %vreg531<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg530,%vreg529,%vreg531
	%vreg532<def> = REG_SEQUENCE %vreg536<kill>, sub0, %vreg530<kill>, sub1; VReg_64:%vreg532 VReg_32:%vreg536,%vreg530
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145<kill>; VGPR_32:%vreg95,%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg541<def> = COPY %vreg146<kill>; VReg_32:%vreg541,%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
	%vreg12<def> = COPY %vreg509<kill>; VReg_64:%vreg12,%vreg509
	%vreg11<def> = COPY %vreg532<kill>; VReg_64:%vreg11,%vreg532
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg543<def> = COPY %vreg541<kill>; VReg_32:%vreg543,%vreg541
	%vreg851<def> = COPY %vreg93<kill>; SReg_64:%vreg851 SGPR_64:%vreg93
	%vreg852<def> = COPY %vreg12<kill>; VReg_64:%vreg852,%vreg12
	%vreg853<def> = COPY %vreg11<kill>; VReg_64:%vreg853,%vreg11
	%vreg854<def> = COPY %vreg543<kill>; VReg_32:%vreg854,%vreg543
	%vreg855<def> = COPY %vreg95<kill>; VGPR_32:%vreg855,%vreg95
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	%vreg451<def> = COPY %vreg13<kill>; VReg_32:%vreg451 SReg_32:%vreg13
	%vreg849<def> = COPY %vreg27<kill>; VGPR_32:%vreg849,%vreg27
	%vreg850<def> = COPY %vreg451<kill>; VReg_32:%vreg850,%vreg451
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg86<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg453, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg453 VGPR_32:%vreg300
	%vreg856<def> = COPY %vreg20; VGPR_32:%vreg856,%vreg20
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4<kill>; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5<kill>, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg444<def> = V_ADD_I32_e32 %vreg305<kill>, %vreg442<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
	%vreg309<def> = V_MUL_LO_I32 %vreg50<kill>, %vreg444<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg444
	%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg309, %EXEC<imp-use>; VReg_32:%vreg548,%vreg309
	%vreg312<def> = REG_SEQUENCE %vreg309<kill>, sub0, %vreg548<kill>, sub1; VReg_64:%vreg312 VReg_32:%vreg309,%vreg548
	%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
	%vreg550<def> = COPY %vreg312:sub1<kill>; VReg_32:%vreg550 VReg_64:%vreg312
	%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg453, %EXEC<imp-use>; VReg_32:%vreg494,%vreg453
	%vreg459<def> = REG_SEQUENCE %vreg453, sub0, %vreg494<kill>, sub1; VReg_64:%vreg459 VReg_32:%vreg453,%vreg494
	%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
	%vreg462<def> = COPY %vreg459:sub1<kill>; VReg_32:%vreg462 VReg_64:%vreg459
	%vreg493<def> = V_ADD_I32_e32 %vreg549<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
	%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg550<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg477,%vreg462,%vreg550
	%vreg479<def> = REG_SEQUENCE %vreg493<kill>, sub0, %vreg477<kill>, sub1; VReg_64:%vreg479 VReg_32:%vreg493,%vreg477
	%vreg482<def> = V_LSHL_B64 %vreg479<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
	%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
	%vreg483<def> = COPY %vreg482:sub1<kill>; VReg_32:%vreg483 VReg_64:%vreg482
	%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
	%vreg552<def> = COPY %vreg49:sub1<kill>; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
	%vreg490<def> = V_ADD_I32_e32 %vreg551<kill>, %vreg489<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
	%vreg484<def> = V_ADDC_U32_e32 %vreg552<kill>, %vreg483<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg484,%vreg552,%vreg483
	%vreg486<def> = REG_SEQUENCE %vreg490<kill>, sub0, %vreg484<kill>, sub1; VReg_64:%vreg486 VReg_32:%vreg490,%vreg484
	%vreg330<def> = COPY %vreg0<kill>; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1<kill>, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg447<def> = V_ADD_I32_e32 %vreg331<kill>, %vreg445<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
	%vreg335<def> = V_MUL_LO_I32 %vreg52<kill>, %vreg447<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg447
	%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg335, %EXEC<imp-use>; VReg_32:%vreg555,%vreg335
	%vreg338<def> = REG_SEQUENCE %vreg335<kill>, sub0, %vreg555<kill>, sub1; VReg_64:%vreg338 VReg_32:%vreg335,%vreg555
	%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
	%vreg557<def> = COPY %vreg338:sub1<kill>; VReg_32:%vreg557 VReg_64:%vreg338
	%vreg492<def> = V_ADD_I32_e32 %vreg556<kill>, %vreg491<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
	%vreg463<def> = V_ADDC_U32_e32 %vreg462<kill>, %vreg557<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg463,%vreg462,%vreg557
	%vreg465<def> = REG_SEQUENCE %vreg492<kill>, sub0, %vreg463<kill>, sub1; VReg_64:%vreg465 VReg_32:%vreg492,%vreg463
	%vreg468<def> = V_LSHL_B64 %vreg465<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
	%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
	%vreg469<def> = COPY %vreg468:sub1<kill>; VReg_32:%vreg469 VReg_64:%vreg468
	%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
	%vreg559<def> = COPY %vreg51:sub1<kill>; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
	%vreg476<def> = V_ADD_I32_e32 %vreg558<kill>, %vreg475<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
	%vreg470<def> = V_ADDC_U32_e32 %vreg559<kill>, %vreg469<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg470,%vreg559,%vreg469
	%vreg472<def> = REG_SEQUENCE %vreg476<kill>, sub0, %vreg470<kill>, sub1; VReg_64:%vreg472 VReg_32:%vreg476,%vreg470
	%vreg454<def> = V_SUB_I32_e32 %vreg55<kill>, %vreg453<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg454,%vreg453 SReg_32:%vreg55
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
	%vreg19<def> = COPY %vreg486<kill>; VReg_64:%vreg19,%vreg486
	%vreg18<def> = COPY %vreg472<kill>; VReg_64:%vreg18,%vreg472
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg456<def> = COPY %vreg454<kill>; VReg_32:%vreg456,%vreg454
	%vreg857<def> = COPY %vreg303<kill>; SReg_64:%vreg857 SGPR_64:%vreg303
	%vreg858<def> = COPY %vreg19<kill>; VReg_64:%vreg858,%vreg19
	%vreg859<def> = COPY %vreg18<kill>; VReg_64:%vreg859,%vreg18
	%vreg860<def> = COPY %vreg456<kill>; VReg_32:%vreg860,%vreg456
	%vreg861<def> = COPY %vreg20<kill>; VGPR_32:%vreg861,%vreg20
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg449<def> = COPY %vreg850<kill>; VReg_32:%vreg449,%vreg850
	%vreg20<def> = COPY %vreg849<kill>; VGPR_32:%vreg20,%vreg849
	%vreg56<def> = COPY %vreg78<kill>; VGPR_32:%vreg56 SGPR_32:%vreg78
	%vreg54<def> = COPY %vreg80<kill>; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81<kill>; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	SI_END_CF %vreg92<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
	%vreg453<def> = COPY %vreg449<kill>; VReg_32:%vreg453,%vreg449
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg26<def> = COPY %vreg855<kill>; VGPR_32:%vreg26,%vreg855
	%vreg542<def> = COPY %vreg854<kill>; VReg_32:%vreg542,%vreg854
	%vreg24<def> = COPY %vreg853<kill>; VReg_64:%vreg24,%vreg853
	%vreg23<def> = COPY %vreg852<kill>; VReg_64:%vreg23,%vreg852
	%vreg22<def> = COPY %vreg851<kill>; SReg_64:%vreg22,%vreg851
	%vreg399<def> = REG_SEQUENCE %vreg401, sub0, %vreg400, sub1; SGPR_64:%vreg399 SGPR_32:%vreg401,%vreg400
	%vreg148<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg399, sub2_sub3; SReg_128:%vreg148 SGPR_64:%vreg147,%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151<kill>, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155<kill>, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159<kill>, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163<kill>, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167<kill>, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171<kill>, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175<kill>, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148<kill>, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179<kill>, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183<def> = REG_SEQUENCE %vreg182, sub0, %vreg181, sub1; SGPR_64:%vreg183 SReg_32:%vreg182,%vreg181
	%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
	%vreg561<def> = COPY %vreg560<kill>; VReg_64:%vreg561,%vreg560
	%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
	%vreg562<def> = REG_SEQUENCE %vreg561<kill>, sub0_sub1, %vreg564<kill>, sub2_sub3; VReg_128:%vreg562 VReg_64:%vreg561,%vreg564
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
	%vreg678<def> = COPY %vreg677:sub0<kill>; VReg_32:%vreg678 VReg_128:%vreg677
	%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
	%vreg680<def> = COPY %vreg679:sub1<kill>; VReg_32:%vreg680 VReg_128:%vreg679
	%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
	%vreg682<def> = COPY %vreg681:sub0<kill>; VReg_32:%vreg682 VReg_64:%vreg681
	%vreg683<def> = COPY %vreg187<kill>; VReg_64:%vreg683,%vreg187
	%vreg684<def> = COPY %vreg683:sub1<kill>; VReg_32:%vreg684 VReg_64:%vreg683
	%vreg670<def> = V_ADD_I32_e32 %vreg678<kill>, %vreg682<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
	%vreg671<def> = V_ADDC_U32_e32 %vreg680<kill>, %vreg684<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
	%vreg672<def> = REG_SEQUENCE %vreg670<kill>, sub0, %vreg671<kill>, sub1; VReg_64:%vreg672 VReg_32:%vreg670,%vreg671
	%vreg676<def> = REG_SEQUENCE %vreg147, sub0_sub1, %vreg401, sub2, %vreg400, sub3; SReg_128:%vreg676 SGPR_64:%vreg147 SGPR_32:%vreg401,%vreg400
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
	%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
	%vreg686<def> = COPY %vreg685<kill>; VReg_64:%vreg686,%vreg685
	%vreg689<def> = COPY %vreg399<kill>; VReg_64:%vreg689 SGPR_64:%vreg399
	%vreg687<def> = REG_SEQUENCE %vreg686<kill>, sub0_sub1, %vreg689<kill>, sub2_sub3; VReg_128:%vreg687 VReg_64:%vreg686,%vreg689
	%vreg191<def> = COPY %vreg183<kill>; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
	%vreg803<def> = COPY %vreg802:sub0<kill>; VReg_32:%vreg803 VReg_128:%vreg802
	%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
	%vreg805<def> = COPY %vreg804:sub1<kill>; VReg_32:%vreg805 VReg_128:%vreg804
	%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
	%vreg807<def> = COPY %vreg806:sub0<kill>; VReg_32:%vreg807 VReg_64:%vreg806
	%vreg808<def> = COPY %vreg191<kill>; VReg_64:%vreg808,%vreg191
	%vreg809<def> = COPY %vreg808:sub1<kill>; VReg_32:%vreg809 VReg_64:%vreg808
	%vreg795<def> = V_ADD_I32_e32 %vreg803<kill>, %vreg807<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
	%vreg796<def> = V_ADDC_U32_e32 %vreg805<kill>, %vreg809<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
	%vreg797<def> = REG_SEQUENCE %vreg795<kill>, sub0, %vreg796<kill>, sub1; VReg_64:%vreg797 VReg_32:%vreg795,%vreg796
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192<kill>, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195<def> = REG_SEQUENCE %vreg194, sub0, %vreg181, sub1; SGPR_64:%vreg195 SReg_32:%vreg194,%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
	%vreg663<def> = COPY %vreg662:sub0<kill>; VReg_32:%vreg663 VReg_128:%vreg662
	%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
	%vreg665<def> = COPY %vreg664:sub1<kill>; VReg_32:%vreg665 VReg_128:%vreg664
	%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
	%vreg667<def> = COPY %vreg666:sub0<kill>; VReg_32:%vreg667 VReg_64:%vreg666
	%vreg668<def> = COPY %vreg197<kill>; VReg_64:%vreg668,%vreg197
	%vreg669<def> = COPY %vreg668:sub1<kill>; VReg_32:%vreg669 VReg_64:%vreg668
	%vreg655<def> = V_ADD_I32_e32 %vreg663<kill>, %vreg667<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
	%vreg656<def> = V_ADDC_U32_e32 %vreg665<kill>, %vreg669<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
	%vreg657<def> = REG_SEQUENCE %vreg655<kill>, sub0, %vreg656<kill>, sub1; VReg_64:%vreg657 VReg_32:%vreg655,%vreg656
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
	%vreg199<def> = COPY %vreg195<kill>; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
	%vreg788<def> = COPY %vreg787:sub0<kill>; VReg_32:%vreg788 VReg_128:%vreg787
	%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
	%vreg790<def> = COPY %vreg789:sub1<kill>; VReg_32:%vreg790 VReg_128:%vreg789
	%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
	%vreg792<def> = COPY %vreg791:sub0<kill>; VReg_32:%vreg792 VReg_64:%vreg791
	%vreg793<def> = COPY %vreg199<kill>; VReg_64:%vreg793,%vreg199
	%vreg794<def> = COPY %vreg793:sub1<kill>; VReg_32:%vreg794 VReg_64:%vreg793
	%vreg780<def> = V_ADD_I32_e32 %vreg788<kill>, %vreg792<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
	%vreg781<def> = V_ADDC_U32_e32 %vreg790<kill>, %vreg794<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
	%vreg782<def> = REG_SEQUENCE %vreg780<kill>, sub0, %vreg781<kill>, sub1; VReg_64:%vreg782 VReg_32:%vreg780,%vreg781
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200<kill>, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203<def> = REG_SEQUENCE %vreg202, sub0, %vreg181, sub1; SGPR_64:%vreg203 SReg_32:%vreg202,%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
	%vreg648<def> = COPY %vreg647:sub0<kill>; VReg_32:%vreg648 VReg_128:%vreg647
	%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
	%vreg650<def> = COPY %vreg649:sub1<kill>; VReg_32:%vreg650 VReg_128:%vreg649
	%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
	%vreg652<def> = COPY %vreg651:sub0<kill>; VReg_32:%vreg652 VReg_64:%vreg651
	%vreg653<def> = COPY %vreg205<kill>; VReg_64:%vreg653,%vreg205
	%vreg654<def> = COPY %vreg653:sub1<kill>; VReg_32:%vreg654 VReg_64:%vreg653
	%vreg640<def> = V_ADD_I32_e32 %vreg648<kill>, %vreg652<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
	%vreg641<def> = V_ADDC_U32_e32 %vreg650<kill>, %vreg654<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
	%vreg642<def> = REG_SEQUENCE %vreg640<kill>, sub0, %vreg641<kill>, sub1; VReg_64:%vreg642 VReg_32:%vreg640,%vreg641
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
	%vreg207<def> = COPY %vreg203<kill>; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
	%vreg773<def> = COPY %vreg772:sub0<kill>; VReg_32:%vreg773 VReg_128:%vreg772
	%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
	%vreg775<def> = COPY %vreg774:sub1<kill>; VReg_32:%vreg775 VReg_128:%vreg774
	%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
	%vreg777<def> = COPY %vreg776:sub0<kill>; VReg_32:%vreg777 VReg_64:%vreg776
	%vreg778<def> = COPY %vreg207<kill>; VReg_64:%vreg778,%vreg207
	%vreg779<def> = COPY %vreg778:sub1<kill>; VReg_32:%vreg779 VReg_64:%vreg778
	%vreg765<def> = V_ADD_I32_e32 %vreg773<kill>, %vreg777<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
	%vreg766<def> = V_ADDC_U32_e32 %vreg775<kill>, %vreg779<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
	%vreg767<def> = REG_SEQUENCE %vreg765<kill>, sub0, %vreg766<kill>, sub1; VReg_64:%vreg767 VReg_32:%vreg765,%vreg766
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208<kill>, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211<def> = REG_SEQUENCE %vreg210, sub0, %vreg181, sub1; SGPR_64:%vreg211 SReg_32:%vreg210,%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
	%vreg633<def> = COPY %vreg632:sub0<kill>; VReg_32:%vreg633 VReg_128:%vreg632
	%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
	%vreg635<def> = COPY %vreg634:sub1<kill>; VReg_32:%vreg635 VReg_128:%vreg634
	%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
	%vreg637<def> = COPY %vreg636:sub0<kill>; VReg_32:%vreg637 VReg_64:%vreg636
	%vreg638<def> = COPY %vreg213<kill>; VReg_64:%vreg638,%vreg213
	%vreg639<def> = COPY %vreg638:sub1<kill>; VReg_32:%vreg639 VReg_64:%vreg638
	%vreg625<def> = V_ADD_I32_e32 %vreg633<kill>, %vreg637<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
	%vreg626<def> = V_ADDC_U32_e32 %vreg635<kill>, %vreg639<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
	%vreg627<def> = REG_SEQUENCE %vreg625<kill>, sub0, %vreg626<kill>, sub1; VReg_64:%vreg627 VReg_32:%vreg625,%vreg626
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
	%vreg215<def> = COPY %vreg211<kill>; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
	%vreg758<def> = COPY %vreg757:sub0<kill>; VReg_32:%vreg758 VReg_128:%vreg757
	%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
	%vreg760<def> = COPY %vreg759:sub1<kill>; VReg_32:%vreg760 VReg_128:%vreg759
	%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
	%vreg762<def> = COPY %vreg761:sub0<kill>; VReg_32:%vreg762 VReg_64:%vreg761
	%vreg763<def> = COPY %vreg215<kill>; VReg_64:%vreg763,%vreg215
	%vreg764<def> = COPY %vreg763:sub1<kill>; VReg_32:%vreg764 VReg_64:%vreg763
	%vreg750<def> = V_ADD_I32_e32 %vreg758<kill>, %vreg762<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
	%vreg751<def> = V_ADDC_U32_e32 %vreg760<kill>, %vreg764<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
	%vreg752<def> = REG_SEQUENCE %vreg750<kill>, sub0, %vreg751<kill>, sub1; VReg_64:%vreg752 VReg_32:%vreg750,%vreg751
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216<kill>, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219<def> = REG_SEQUENCE %vreg218, sub0, %vreg181, sub1; SGPR_64:%vreg219 SReg_32:%vreg218,%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
	%vreg618<def> = COPY %vreg617:sub0<kill>; VReg_32:%vreg618 VReg_128:%vreg617
	%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
	%vreg620<def> = COPY %vreg619:sub1<kill>; VReg_32:%vreg620 VReg_128:%vreg619
	%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
	%vreg622<def> = COPY %vreg621:sub0<kill>; VReg_32:%vreg622 VReg_64:%vreg621
	%vreg623<def> = COPY %vreg221<kill>; VReg_64:%vreg623,%vreg221
	%vreg624<def> = COPY %vreg623:sub1<kill>; VReg_32:%vreg624 VReg_64:%vreg623
	%vreg610<def> = V_ADD_I32_e32 %vreg618<kill>, %vreg622<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
	%vreg611<def> = V_ADDC_U32_e32 %vreg620<kill>, %vreg624<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
	%vreg612<def> = REG_SEQUENCE %vreg610<kill>, sub0, %vreg611<kill>, sub1; VReg_64:%vreg612 VReg_32:%vreg610,%vreg611
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
	%vreg223<def> = COPY %vreg219<kill>; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
	%vreg743<def> = COPY %vreg742:sub0<kill>; VReg_32:%vreg743 VReg_128:%vreg742
	%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
	%vreg745<def> = COPY %vreg744:sub1<kill>; VReg_32:%vreg745 VReg_128:%vreg744
	%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
	%vreg747<def> = COPY %vreg746:sub0<kill>; VReg_32:%vreg747 VReg_64:%vreg746
	%vreg748<def> = COPY %vreg223<kill>; VReg_64:%vreg748,%vreg223
	%vreg749<def> = COPY %vreg748:sub1<kill>; VReg_32:%vreg749 VReg_64:%vreg748
	%vreg735<def> = V_ADD_I32_e32 %vreg743<kill>, %vreg747<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
	%vreg736<def> = V_ADDC_U32_e32 %vreg745<kill>, %vreg749<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
	%vreg737<def> = REG_SEQUENCE %vreg735<kill>, sub0, %vreg736<kill>, sub1; VReg_64:%vreg737 VReg_32:%vreg735,%vreg736
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224<kill>, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227<def> = REG_SEQUENCE %vreg226, sub0, %vreg181, sub1; SGPR_64:%vreg227 SReg_32:%vreg226,%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
	%vreg603<def> = COPY %vreg602:sub0<kill>; VReg_32:%vreg603 VReg_128:%vreg602
	%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
	%vreg605<def> = COPY %vreg604:sub1<kill>; VReg_32:%vreg605 VReg_128:%vreg604
	%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
	%vreg607<def> = COPY %vreg606:sub0<kill>; VReg_32:%vreg607 VReg_64:%vreg606
	%vreg608<def> = COPY %vreg229<kill>; VReg_64:%vreg608,%vreg229
	%vreg609<def> = COPY %vreg608:sub1<kill>; VReg_32:%vreg609 VReg_64:%vreg608
	%vreg595<def> = V_ADD_I32_e32 %vreg603<kill>, %vreg607<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
	%vreg596<def> = V_ADDC_U32_e32 %vreg605<kill>, %vreg609<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
	%vreg597<def> = REG_SEQUENCE %vreg595<kill>, sub0, %vreg596<kill>, sub1; VReg_64:%vreg597 VReg_32:%vreg595,%vreg596
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
	%vreg231<def> = COPY %vreg227<kill>; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
	%vreg728<def> = COPY %vreg727:sub0<kill>; VReg_32:%vreg728 VReg_128:%vreg727
	%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
	%vreg730<def> = COPY %vreg729:sub1<kill>; VReg_32:%vreg730 VReg_128:%vreg729
	%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
	%vreg732<def> = COPY %vreg731:sub0<kill>; VReg_32:%vreg732 VReg_64:%vreg731
	%vreg733<def> = COPY %vreg231<kill>; VReg_64:%vreg733,%vreg231
	%vreg734<def> = COPY %vreg733:sub1<kill>; VReg_32:%vreg734 VReg_64:%vreg733
	%vreg720<def> = V_ADD_I32_e32 %vreg728<kill>, %vreg732<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
	%vreg721<def> = V_ADDC_U32_e32 %vreg730<kill>, %vreg734<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
	%vreg722<def> = REG_SEQUENCE %vreg720<kill>, sub0, %vreg721<kill>, sub1; VReg_64:%vreg722 VReg_32:%vreg720,%vreg721
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232<kill>, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235<def> = REG_SEQUENCE %vreg234, sub0, %vreg181, sub1; SGPR_64:%vreg235 SReg_32:%vreg234,%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
	%vreg588<def> = COPY %vreg587:sub0<kill>; VReg_32:%vreg588 VReg_128:%vreg587
	%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
	%vreg590<def> = COPY %vreg589:sub1<kill>; VReg_32:%vreg590 VReg_128:%vreg589
	%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
	%vreg592<def> = COPY %vreg591:sub0<kill>; VReg_32:%vreg592 VReg_64:%vreg591
	%vreg593<def> = COPY %vreg237<kill>; VReg_64:%vreg593,%vreg237
	%vreg594<def> = COPY %vreg593:sub1<kill>; VReg_32:%vreg594 VReg_64:%vreg593
	%vreg580<def> = V_ADD_I32_e32 %vreg588<kill>, %vreg592<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
	%vreg581<def> = V_ADDC_U32_e32 %vreg590<kill>, %vreg594<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
	%vreg582<def> = REG_SEQUENCE %vreg580<kill>, sub0, %vreg581<kill>, sub1; VReg_64:%vreg582 VReg_32:%vreg580,%vreg581
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
	%vreg239<def> = COPY %vreg235<kill>; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
	%vreg713<def> = COPY %vreg712:sub0<kill>; VReg_32:%vreg713 VReg_128:%vreg712
	%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
	%vreg715<def> = COPY %vreg714:sub1<kill>; VReg_32:%vreg715 VReg_128:%vreg714
	%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
	%vreg717<def> = COPY %vreg716:sub0<kill>; VReg_32:%vreg717 VReg_64:%vreg716
	%vreg718<def> = COPY %vreg239<kill>; VReg_64:%vreg718,%vreg239
	%vreg719<def> = COPY %vreg718:sub1<kill>; VReg_32:%vreg719 VReg_64:%vreg718
	%vreg705<def> = V_ADD_I32_e32 %vreg713<kill>, %vreg717<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
	%vreg706<def> = V_ADDC_U32_e32 %vreg715<kill>, %vreg719<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
	%vreg707<def> = REG_SEQUENCE %vreg705<kill>, sub0, %vreg706<kill>, sub1; VReg_64:%vreg707 VReg_32:%vreg705,%vreg706
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240<kill>, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243<def> = REG_SEQUENCE %vreg242, sub0, %vreg181, sub1; SGPR_64:%vreg243 SReg_32:%vreg242,%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
	%vreg573<def> = COPY %vreg572:sub0<kill>; VReg_32:%vreg573 VReg_128:%vreg572
	%vreg574<def> = COPY %vreg562<kill>; VReg_128:%vreg574,%vreg562
	%vreg575<def> = COPY %vreg574:sub1<kill>; VReg_32:%vreg575 VReg_128:%vreg574
	%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
	%vreg577<def> = COPY %vreg576:sub0<kill>; VReg_32:%vreg577 VReg_64:%vreg576
	%vreg578<def> = COPY %vreg245<kill>; VReg_64:%vreg578,%vreg245
	%vreg579<def> = COPY %vreg578:sub1<kill>; VReg_32:%vreg579 VReg_64:%vreg578
	%vreg565<def> = V_ADD_I32_e32 %vreg573<kill>, %vreg577<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
	%vreg566<def> = V_ADDC_U32_e32 %vreg575<kill>, %vreg579<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
	%vreg567<def> = REG_SEQUENCE %vreg565<kill>, sub0, %vreg566<kill>, sub1; VReg_64:%vreg567 VReg_32:%vreg565,%vreg566
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
	%vreg247<def> = COPY %vreg243<kill>; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
	%vreg698<def> = COPY %vreg697:sub0<kill>; VReg_32:%vreg698 VReg_128:%vreg697
	%vreg699<def> = COPY %vreg687<kill>; VReg_128:%vreg699,%vreg687
	%vreg700<def> = COPY %vreg699:sub1<kill>; VReg_32:%vreg700 VReg_128:%vreg699
	%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
	%vreg702<def> = COPY %vreg701:sub0<kill>; VReg_32:%vreg702 VReg_64:%vreg701
	%vreg703<def> = COPY %vreg247<kill>; VReg_64:%vreg703,%vreg247
	%vreg704<def> = COPY %vreg703:sub1<kill>; VReg_32:%vreg704 VReg_64:%vreg703
	%vreg690<def> = V_ADD_I32_e32 %vreg698<kill>, %vreg702<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
	%vreg691<def> = V_ADDC_U32_e32 %vreg700<kill>, %vreg704<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
	%vreg692<def> = REG_SEQUENCE %vreg690<kill>, sub0, %vreg691<kill>, sub1; VReg_64:%vreg692 VReg_32:%vreg690,%vreg691
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676<kill>, %vreg692<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248<kill>, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250<def> = REG_SEQUENCE %vreg249<kill>, sub0, %vreg241<kill>, sub1, %vreg233<kill>, sub2, %vreg225<kill>, sub3, %vreg217<kill>, sub4, %vreg209<kill>, sub5, %vreg201<kill>, sub6, %vreg193<kill>, sub7, %vreg180<kill>, sub8, %vreg176<kill>, sub9, %vreg172<kill>, sub10, %vreg168<kill>, sub11, %vreg164<kill>, sub12, %vreg160<kill>, sub13, %vreg156<kill>, sub14, %vreg152<kill>, sub15; VReg_512:%vreg250 VGPR_32:%vreg249,%vreg241,%vreg233,%vreg225,%vreg217,%vreg209,%vreg201,%vreg193,%vreg180,%vreg176,%vreg172,%vreg168,%vreg164,%vreg160,%vreg156,%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15<kill>; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26<kill>, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg816<def> = COPY %vreg23:sub1<kill>; VReg_32:%vreg816 VReg_64:%vreg23
	%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
	%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
	%vreg817<def> = V_ADDC_U32_e32 %vreg816<kill>, %vreg818<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg817,%vreg816,%vreg818
	%vreg812<def> = REG_SEQUENCE %vreg811<kill>, sub0, %vreg817<kill>, sub1; VReg_64:%vreg812 VReg_32:%vreg811,%vreg817
	%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
	%vreg825<def> = COPY %vreg24:sub1<kill>; VReg_32:%vreg825 VReg_64:%vreg24
	%vreg820<def> = V_ADD_I32_e32 %vreg284<kill>, %vreg819<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
	%vreg827<def> = COPY %vreg286<kill>; VReg_32:%vreg827 SReg_32:%vreg286
	%vreg826<def> = V_ADDC_U32_e32 %vreg825<kill>, %vreg827<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg826,%vreg825,%vreg827
	%vreg821<def> = REG_SEQUENCE %vreg820<kill>, sub0, %vreg826<kill>, sub1; VReg_64:%vreg821 VReg_32:%vreg820,%vreg826
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg545<def> = V_ADD_I32_e32 16, %vreg542<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg545,%vreg542
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg815<def> = COPY %vreg812<kill>; VReg_64:%vreg815,%vreg812
	%vreg824<def> = COPY %vreg821<kill>; VReg_64:%vreg824,%vreg821
	%vreg27<def> = COPY %vreg282<kill>; VGPR_32:%vreg27,%vreg282
	%vreg544<def> = COPY %vreg545<kill>; VReg_32:%vreg544,%vreg545
	%vreg851<def> = COPY %vreg31; SReg_64:%vreg851,%vreg31
	%vreg852<def> = COPY %vreg815<kill>; VReg_64:%vreg852,%vreg815
	%vreg853<def> = COPY %vreg824<kill>; VReg_64:%vreg853,%vreg824
	%vreg854<def> = COPY %vreg544<kill>; VReg_32:%vreg854,%vreg544
	%vreg855<def> = COPY %vreg27; VGPR_32:%vreg855,%vreg27
	SI_LOOP %vreg298<kill>, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = COPY %vreg856<kill>; VGPR_32:%vreg32,%vreg856
	SI_END_CF %vreg302<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg37<def> = COPY %vreg861<kill>; VGPR_32:%vreg37,%vreg861
	%vreg455<def> = COPY %vreg860<kill>; VReg_32:%vreg455,%vreg860
	%vreg35<def> = COPY %vreg859<kill>; VReg_64:%vreg35,%vreg859
	%vreg34<def> = COPY %vreg858<kill>; VReg_64:%vreg34,%vreg858
	%vreg33<def> = COPY %vreg857<kill>; SReg_64:%vreg33,%vreg857
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
	%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
	%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
	%vreg835<def> = V_ADDC_U32_e32 %vreg834<kill>, %vreg836<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg835,%vreg834,%vreg836
	%vreg830<def> = REG_SEQUENCE %vreg829<kill>, sub0, %vreg835<kill>, sub1; VReg_64:%vreg830 VReg_32:%vreg829,%vreg835
	%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
	%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
	%vreg838<def> = V_ADD_I32_e32 %vreg354<kill>, %vreg837<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
	%vreg845<def> = COPY %vreg356<kill>; VReg_32:%vreg845 SReg_32:%vreg356
	%vreg844<def> = V_ADDC_U32_e32 %vreg843<kill>, %vreg845<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg844,%vreg843,%vreg845
	%vreg839<def> = REG_SEQUENCE %vreg838<kill>, sub0, %vreg844<kill>, sub1; VReg_64:%vreg839 VReg_32:%vreg838,%vreg844
	%vreg411<def> = REG_SEQUENCE %vreg413, sub0, %vreg412, sub1; SGPR_64:%vreg411 SGPR_32:%vreg413,%vreg412
	%vreg366<def> = REG_SEQUENCE %vreg352, sub0_sub1, %vreg411<kill>, sub2_sub3; SReg_128:%vreg366 SGPR_64:%vreg352,%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366<kill>, %vreg34<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369<kill>, %vreg369, %vreg37<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
	%vreg458<def> = V_ADD_I32_e32 -1, %vreg455<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg458,%vreg455
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg833<def> = COPY %vreg830<kill>; VReg_64:%vreg833,%vreg830
	%vreg842<def> = COPY %vreg839<kill>; VReg_64:%vreg842,%vreg839
	%vreg38<def> = COPY %vreg370<kill>; VGPR_32:%vreg38,%vreg370
	%vreg457<def> = COPY %vreg458<kill>; VReg_32:%vreg457,%vreg458
	%vreg857<def> = COPY %vreg42; SReg_64:%vreg857,%vreg42
	%vreg858<def> = COPY %vreg833<kill>; VReg_64:%vreg858,%vreg833
	%vreg859<def> = COPY %vreg842<kill>; VReg_64:%vreg859,%vreg842
	%vreg860<def> = COPY %vreg457<kill>; VReg_32:%vreg860,%vreg457
	%vreg861<def> = COPY %vreg38; VGPR_32:%vreg861,%vreg38
	SI_LOOP %vreg372<kill>, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg42
	%vreg856<def> = COPY %vreg38<kill>; VGPR_32:%vreg856,%vreg38
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg373<def> = COPY %vreg54<kill>; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg440<kill>, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
	%vreg424<def> = V_ADD_I32_e32 %vreg374<kill>, %vreg423<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg424,%vreg374,%vreg423
	%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
	%vreg425<def> = REG_SEQUENCE %vreg424<kill>, sub0, %vreg437<kill>, sub1; VReg_64:%vreg425 VReg_32:%vreg424,%vreg437
	%vreg428<def> = V_LSHL_B64 %vreg425<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
	%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
	%vreg429<def> = COPY %vreg428:sub1<kill>; VReg_32:%vreg429 VReg_64:%vreg428
	%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
	%vreg848<def> = COPY %vreg53:sub1<kill>; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
	%vreg436<def> = V_ADD_I32_e32 %vreg847<kill>, %vreg435<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
	%vreg430<def> = V_ADDC_U32_e32 %vreg848<kill>, %vreg429<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg430,%vreg848,%vreg429
	%vreg432<def> = REG_SEQUENCE %vreg436<kill>, sub0, %vreg430<kill>, sub1; VReg_64:%vreg432 VReg_32:%vreg436,%vreg430
	%vreg388<def> = V_MUL_F32_e64 %vreg32<kill>, %vreg56<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg32,%vreg56
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg45<def> = COPY %vreg432<kill>; VReg_64:%vreg45,%vreg432
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def,tied1> = SI_ELSE %vreg393<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg393
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415<def> = REG_SEQUENCE %vreg417<kill>, sub0, %vreg416<kill>, sub1; SGPR_64:%vreg415 SGPR_32:%vreg417,%vreg416
	%vreg396<def> = REG_SEQUENCE %vreg414<kill>, sub0_sub1, %vreg415<kill>, sub2_sub3; SReg_128:%vreg396 SGPR_64:%vreg414,%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg44<def> = COPY %vreg388<kill>; VGPR_32:%vreg44,%vreg388
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419<def> = REG_SEQUENCE %vreg421<kill>, sub0, %vreg420<kill>, sub1; SGPR_64:%vreg419 SGPR_32:%vreg421,%vreg420
	%vreg394<def> = REG_SEQUENCE %vreg418<kill>, sub0_sub1, %vreg419<kill>, sub2_sub3; SReg_128:%vreg394 SGPR_64:%vreg418,%vreg419
	BUFFER_STORE_DWORD %vreg44<kill>, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg395<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Slot index numbering ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%vreg60<def> = COPY %SGPR2<kill>; SReg_32:%vreg60
	%vreg59<def> = COPY %VGPR0<kill>; VReg_32:%vreg59
	%vreg58<def> = COPY %SGPR3<kill>; SReg_32:%vreg58
	%vreg57<def> = COPY %VGPR1<kill>; VReg_32:%vreg57
	%vreg48<def> = COPY %SGPR0_SGPR1<kill>; SReg_64:%vreg48
	%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
	%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
	%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
	%vreg423<def> = V_ADD_I32_e32 %vreg63<kill>, %vreg59, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg59
	%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
	%vreg67<def> = COPY %vreg66<kill>; VGPR_32:%vreg67 SGPR_32:%vreg66
	%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
	%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
	%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
	%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
	%vreg440<def> = V_ADD_I32_e32 %vreg71<kill>, %vreg57, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg57
	%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
	%vreg75<def> = COPY %vreg74<kill>; VGPR_32:%vreg75 SGPR_32:%vreg74
	%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
	%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
	%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
	%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
	%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
	%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
	%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
	%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
	%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
	%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48<kill>, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
	%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Predecessors according to CFG: BB#0
	%vreg442<def> = COPY %vreg57<kill>; VReg_32:%vreg442,%vreg57
	%vreg4<def> = COPY %vreg58<kill>; SReg_32:%vreg4,%vreg58
	%vreg445<def> = COPY %vreg59<kill>; VReg_32:%vreg445,%vreg59
	%vreg0<def> = COPY %vreg60<kill>; SReg_32:%vreg0,%vreg60
	%vreg5<def> = COPY %vreg70<kill>; SReg_32:%vreg5 SGPR_32:%vreg70
	%vreg1<def> = COPY %vreg62<kill>; SReg_32:%vreg1 SGPR_32:%vreg62
	%vreg55<def> = COPY %vreg79<kill>; SReg_32:%vreg55 SGPR_32:%vreg79
	%vreg52<def> = COPY %vreg82<kill>; SReg_32:%vreg52 SGPR_32:%vreg82
	%vreg51<def> = COPY %vreg83<kill>; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	%vreg50<def> = COPY %vreg84<kill>; SReg_32:%vreg50 SGPR_32:%vreg84
	%vreg49<def> = COPY %vreg85<kill>; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
	%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
	%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
	%vreg448<def> = COPY %vreg90<kill>; VReg_32:%vreg448,%vreg90
	%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
	%vreg87<def> = COPY %vreg91<kill>; VGPR_32:%vreg87,%vreg91
	%vreg450<def> = COPY %vreg448<kill>; VReg_32:%vreg450,%vreg448
	%vreg849<def> = COPY %vreg87<kill>; VGPR_32:%vreg849,%vreg87
	%vreg850<def> = COPY %vreg450<kill>; VReg_32:%vreg850,%vreg450
	%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Predecessors according to CFG: BB#1
	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
	%vreg443<def> = V_ADD_I32_e32 %vreg97<kill>, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
	%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg443<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg443
	%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg101, %EXEC<imp-use>; VReg_32:%vreg497,%vreg101
	%vreg104:sub0<def,read-undef> = COPY %vreg101<kill>; VReg_64:%vreg104 VReg_32:%vreg101
	%vreg104:sub1<def> = COPY %vreg497<kill>; VReg_64:%vreg104 VReg_32:%vreg497
	%vreg499<def> = V_LSHL_B64 %vreg104<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
	%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
	%vreg500<def> = COPY %vreg499:sub1<kill>; VReg_32:%vreg500 VReg_64:%vreg499
	%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
	%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
	%vreg515<def> = V_ADD_I32_e32 %vreg516<kill>, %vreg514<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
	%vreg501<def> = V_ADDC_U32_e32 %vreg500<kill>, %vreg517<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg501,%vreg500,%vreg517
	%vreg503:sub0<def,read-undef> = COPY %vreg515<kill>; VReg_64:%vreg503 VReg_32:%vreg515
	%vreg503:sub1<def> = COPY %vreg501<kill>; VReg_64:%vreg503 VReg_32:%vreg501
	%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
	%vreg506<def> = COPY %vreg503:sub1<kill>; VReg_32:%vreg506 VReg_64:%vreg503
	%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	%vreg118<def> = COPY %vreg116:sub1<kill>; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
	%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
	%vreg507<def> = V_ADDC_U32_e32 %vreg506<kill>, %vreg508<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg507,%vreg506,%vreg508
	%vreg509:sub0<def,read-undef> = COPY %vreg513<kill>; VReg_64:%vreg509 VReg_32:%vreg513
	%vreg509:sub1<def> = COPY %vreg507<kill>; VReg_64:%vreg509 VReg_32:%vreg507
	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
	%vreg446<def> = V_ADD_I32_e32 %vreg123<kill>, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
	%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg446<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg446
	%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg127, %EXEC<imp-use>; VReg_32:%vreg520,%vreg127
	%vreg130:sub0<def,read-undef> = COPY %vreg127<kill>; VReg_64:%vreg130 VReg_32:%vreg127
	%vreg130:sub1<def> = COPY %vreg520<kill>; VReg_64:%vreg130 VReg_32:%vreg520
	%vreg522<def> = V_LSHL_B64 %vreg130<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
	%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
	%vreg523<def> = COPY %vreg522:sub1<kill>; VReg_32:%vreg523 VReg_64:%vreg522
	%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
	%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
	%vreg538<def> = V_ADD_I32_e32 %vreg539<kill>, %vreg537<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
	%vreg524<def> = V_ADDC_U32_e32 %vreg523<kill>, %vreg540<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg524,%vreg523,%vreg540
	%vreg526:sub0<def,read-undef> = COPY %vreg538<kill>; VReg_64:%vreg526 VReg_32:%vreg538
	%vreg526:sub1<def> = COPY %vreg524<kill>; VReg_64:%vreg526 VReg_32:%vreg524
	%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
	%vreg529<def> = COPY %vreg526:sub1<kill>; VReg_32:%vreg529 VReg_64:%vreg526
	%vreg536<def> = V_ADD_I32_e32 %vreg117<kill>, %vreg535<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
	%vreg531<def> = COPY %vreg118<kill>; VReg_32:%vreg531 SReg_32:%vreg118
	%vreg530<def> = V_ADDC_U32_e32 %vreg529<kill>, %vreg531<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg530,%vreg529,%vreg531
	%vreg532:sub0<def,read-undef> = COPY %vreg536<kill>; VReg_64:%vreg532 VReg_32:%vreg536
	%vreg532:sub1<def> = COPY %vreg530<kill>; VReg_64:%vreg532 VReg_32:%vreg530
	%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
	%vreg95<def> = COPY %vreg145<kill>; VGPR_32:%vreg95,%vreg145
	%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
	%vreg541<def> = COPY %vreg146<kill>; VReg_32:%vreg541,%vreg146
	%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
	%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
	%vreg12<def> = COPY %vreg509<kill>; VReg_64:%vreg12,%vreg509
	%vreg11<def> = COPY %vreg532<kill>; VReg_64:%vreg11,%vreg532
	%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
	%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
	%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
	%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
	%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
	%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
	%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
	%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
	%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
	%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
	%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
	%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
	%vreg543<def> = COPY %vreg541<kill>; VReg_32:%vreg543,%vreg541
	%vreg851<def> = COPY %vreg93<kill>; SReg_64:%vreg851 SGPR_64:%vreg93
	%vreg852<def> = COPY %vreg12<kill>; VReg_64:%vreg852,%vreg12
	%vreg853<def> = COPY %vreg11<kill>; VReg_64:%vreg853,%vreg11
	%vreg854<def> = COPY %vreg543<kill>; VReg_32:%vreg854,%vreg543
	%vreg855<def> = COPY %vreg95<kill>; VGPR_32:%vreg855,%vreg95
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Predecessors according to CFG: BB#8
	SI_END_CF %vreg31<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg31
	%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
	%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
	%vreg451<def> = COPY %vreg13<kill>; VReg_32:%vreg451 SReg_32:%vreg13
	%vreg849<def> = COPY %vreg27<kill>; VGPR_32:%vreg849,%vreg27
	%vreg850<def> = COPY %vreg451<kill>; VReg_32:%vreg850,%vreg451
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %vreg86<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Predecessors according to CFG: BB#7
	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
	%vreg301<def> = V_CMP_LT_I32_e64 %vreg453, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg453 VGPR_32:%vreg300
	%vreg856<def> = COPY %vreg20; VGPR_32:%vreg856,%vreg20
	%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Predecessors according to CFG: BB#5
	%vreg304<def> = COPY %vreg4<kill>; VGPR_32:%vreg304 SReg_32:%vreg4
	%vreg305<def> = V_MUL_LO_I32 %vreg5<kill>, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
	%vreg444<def> = V_ADD_I32_e32 %vreg305<kill>, %vreg442<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
	%vreg309<def> = V_MUL_LO_I32 %vreg50<kill>, %vreg444<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg444
	%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg309, %EXEC<imp-use>; VReg_32:%vreg548,%vreg309
	%vreg312:sub0<def,read-undef> = COPY %vreg309<kill>; VReg_64:%vreg312 VReg_32:%vreg309
	%vreg312:sub1<def> = COPY %vreg548<kill>; VReg_64:%vreg312 VReg_32:%vreg548
	%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
	%vreg550<def> = COPY %vreg312:sub1<kill>; VReg_32:%vreg550 VReg_64:%vreg312
	%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg453, %EXEC<imp-use>; VReg_32:%vreg494,%vreg453
	%vreg459:sub0<def,read-undef> = COPY %vreg453; VReg_64:%vreg459 VReg_32:%vreg453
	%vreg459:sub1<def> = COPY %vreg494<kill>; VReg_64:%vreg459 VReg_32:%vreg494
	%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
	%vreg462<def> = COPY %vreg459:sub1<kill>; VReg_32:%vreg462 VReg_64:%vreg459
	%vreg493<def> = V_ADD_I32_e32 %vreg549<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
	%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg550<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg477,%vreg462,%vreg550
	%vreg479:sub0<def,read-undef> = COPY %vreg493<kill>; VReg_64:%vreg479 VReg_32:%vreg493
	%vreg479:sub1<def> = COPY %vreg477<kill>; VReg_64:%vreg479 VReg_32:%vreg477
	%vreg482<def> = V_LSHL_B64 %vreg479<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
	%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
	%vreg483<def> = COPY %vreg482:sub1<kill>; VReg_32:%vreg483 VReg_64:%vreg482
	%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
	%vreg552<def> = COPY %vreg49:sub1<kill>; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
	%vreg490<def> = V_ADD_I32_e32 %vreg551<kill>, %vreg489<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
	%vreg484<def> = V_ADDC_U32_e32 %vreg552<kill>, %vreg483<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg484,%vreg552,%vreg483
	%vreg486:sub0<def,read-undef> = COPY %vreg490<kill>; VReg_64:%vreg486 VReg_32:%vreg490
	%vreg486:sub1<def> = COPY %vreg484<kill>; VReg_64:%vreg486 VReg_32:%vreg484
	%vreg330<def> = COPY %vreg0<kill>; VGPR_32:%vreg330 SReg_32:%vreg0
	%vreg331<def> = V_MUL_LO_I32 %vreg1<kill>, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
	%vreg447<def> = V_ADD_I32_e32 %vreg331<kill>, %vreg445<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
	%vreg335<def> = V_MUL_LO_I32 %vreg52<kill>, %vreg447<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg447
	%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg335, %EXEC<imp-use>; VReg_32:%vreg555,%vreg335
	%vreg338:sub0<def,read-undef> = COPY %vreg335<kill>; VReg_64:%vreg338 VReg_32:%vreg335
	%vreg338:sub1<def> = COPY %vreg555<kill>; VReg_64:%vreg338 VReg_32:%vreg555
	%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
	%vreg557<def> = COPY %vreg338:sub1<kill>; VReg_32:%vreg557 VReg_64:%vreg338
	%vreg492<def> = V_ADD_I32_e32 %vreg556<kill>, %vreg491<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
	%vreg463<def> = V_ADDC_U32_e32 %vreg462<kill>, %vreg557<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg463,%vreg462,%vreg557
	%vreg465:sub0<def,read-undef> = COPY %vreg492<kill>; VReg_64:%vreg465 VReg_32:%vreg492
	%vreg465:sub1<def> = COPY %vreg463<kill>; VReg_64:%vreg465 VReg_32:%vreg463
	%vreg468<def> = V_LSHL_B64 %vreg465<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
	%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
	%vreg469<def> = COPY %vreg468:sub1<kill>; VReg_32:%vreg469 VReg_64:%vreg468
	%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
	%vreg559<def> = COPY %vreg51:sub1<kill>; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
	%vreg476<def> = V_ADD_I32_e32 %vreg558<kill>, %vreg475<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
	%vreg470<def> = V_ADDC_U32_e32 %vreg559<kill>, %vreg469<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg470,%vreg559,%vreg469
	%vreg472:sub0<def,read-undef> = COPY %vreg476<kill>; VReg_64:%vreg472 VReg_32:%vreg476
	%vreg472:sub1<def> = COPY %vreg470<kill>; VReg_64:%vreg472 VReg_32:%vreg470
	%vreg454<def> = V_SUB_I32_e32 %vreg55<kill>, %vreg453<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg454,%vreg453 SReg_32:%vreg55
	%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
	%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
	%vreg19<def> = COPY %vreg486<kill>; VReg_64:%vreg19,%vreg486
	%vreg18<def> = COPY %vreg472<kill>; VReg_64:%vreg18,%vreg472
	%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
	%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
	%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
	%vreg456<def> = COPY %vreg454<kill>; VReg_32:%vreg456,%vreg454
	%vreg857<def> = COPY %vreg303<kill>; SReg_64:%vreg857 SGPR_64:%vreg303
	%vreg858<def> = COPY %vreg19<kill>; VReg_64:%vreg858,%vreg19
	%vreg859<def> = COPY %vreg18<kill>; VReg_64:%vreg859,%vreg18
	%vreg860<def> = COPY %vreg456<kill>; VReg_32:%vreg860,%vreg456
	%vreg861<def> = COPY %vreg20<kill>; VGPR_32:%vreg861,%vreg20
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Predecessors according to CFG: BB#1 BB#3
	%vreg449<def> = COPY %vreg850<kill>; VReg_32:%vreg449,%vreg850
	%vreg20<def> = COPY %vreg849<kill>; VGPR_32:%vreg20,%vreg849
	%vreg56<def> = COPY %vreg78<kill>; VGPR_32:%vreg56 SGPR_32:%vreg78
	%vreg54<def> = COPY %vreg80<kill>; SReg_32:%vreg54 SGPR_32:%vreg80
	%vreg53<def> = COPY %vreg81<kill>; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	SI_END_CF %vreg92<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
	%vreg453<def> = COPY %vreg449<kill>; VReg_32:%vreg453,%vreg449
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Predecessors according to CFG: BB#2 BB#8
	%vreg26<def> = COPY %vreg855<kill>; VGPR_32:%vreg26,%vreg855
	%vreg542<def> = COPY %vreg854<kill>; VReg_32:%vreg542,%vreg854
	%vreg24<def> = COPY %vreg853<kill>; VReg_64:%vreg24,%vreg853
	%vreg23<def> = COPY %vreg852<kill>; VReg_64:%vreg23,%vreg852
	%vreg22<def> = COPY %vreg851<kill>; SReg_64:%vreg22,%vreg851
	%vreg399:sub0<def,read-undef> = COPY %vreg401; SGPR_64:%vreg399 SGPR_32:%vreg401
	%vreg399:sub1<def> = COPY %vreg400; SGPR_64:%vreg399 SGPR_32:%vreg400
	%vreg148:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg148 SGPR_64:%vreg147
	%vreg148:sub2_sub3<def> = COPY %vreg399; SReg_128:%vreg148 SGPR_64:%vreg399
	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
	%vreg152<def> = V_MUL_F32_e32 %vreg151<kill>, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
	%vreg156<def> = V_MUL_F32_e32 %vreg155<kill>, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
	%vreg160<def> = V_MUL_F32_e32 %vreg159<kill>, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
	%vreg164<def> = V_MUL_F32_e32 %vreg163<kill>, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
	%vreg168<def> = V_MUL_F32_e32 %vreg167<kill>, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
	%vreg172<def> = V_MUL_F32_e32 %vreg171<kill>, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
	%vreg176<def> = V_MUL_F32_e32 %vreg175<kill>, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148<kill>, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
	%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
	%vreg180<def> = V_MUL_F32_e32 %vreg179<kill>, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
	%vreg183:sub0<def,read-undef> = COPY %vreg182; SGPR_64:%vreg183 SReg_32:%vreg182
	%vreg183:sub1<def> = COPY %vreg181; SGPR_64:%vreg183 SReg_32:%vreg181
	%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
	%vreg561<def> = COPY %vreg560<kill>; VReg_64:%vreg561,%vreg560
	%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg561<kill>; VReg_128:%vreg562 VReg_64:%vreg561
	%vreg562:sub2_sub3<def> = COPY %vreg564<kill>; VReg_128:%vreg562 VReg_64:%vreg564
	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
	%vreg678<def> = COPY %vreg677:sub0<kill>; VReg_32:%vreg678 VReg_128:%vreg677
	%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
	%vreg680<def> = COPY %vreg679:sub1<kill>; VReg_32:%vreg680 VReg_128:%vreg679
	%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
	%vreg682<def> = COPY %vreg681:sub0<kill>; VReg_32:%vreg682 VReg_64:%vreg681
	%vreg683<def> = COPY %vreg187<kill>; VReg_64:%vreg683,%vreg187
	%vreg684<def> = COPY %vreg683:sub1<kill>; VReg_32:%vreg684 VReg_64:%vreg683
	%vreg670<def> = V_ADD_I32_e32 %vreg678<kill>, %vreg682<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
	%vreg671<def> = V_ADDC_U32_e32 %vreg680<kill>, %vreg684<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
	%vreg672:sub0<def,read-undef> = COPY %vreg670<kill>; VReg_64:%vreg672 VReg_32:%vreg670
	%vreg672:sub1<def> = COPY %vreg671<kill>; VReg_64:%vreg672 VReg_32:%vreg671
	%vreg676:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg676 SGPR_64:%vreg147
	%vreg676:sub2<def> = COPY %vreg401; SReg_128:%vreg676 SGPR_32:%vreg401
	%vreg676:sub3<def> = COPY %vreg400; SReg_128:%vreg676 SGPR_32:%vreg400
	%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
	%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
	%vreg686<def> = COPY %vreg685<kill>; VReg_64:%vreg686,%vreg685
	%vreg689<def> = COPY %vreg399<kill>; VReg_64:%vreg689 SGPR_64:%vreg399
	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg686<kill>; VReg_128:%vreg687 VReg_64:%vreg686
	%vreg687:sub2_sub3<def> = COPY %vreg689<kill>; VReg_128:%vreg687 VReg_64:%vreg689
	%vreg191<def> = COPY %vreg183<kill>; VReg_64:%vreg191 SGPR_64:%vreg183
	%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
	%vreg803<def> = COPY %vreg802:sub0<kill>; VReg_32:%vreg803 VReg_128:%vreg802
	%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
	%vreg805<def> = COPY %vreg804:sub1<kill>; VReg_32:%vreg805 VReg_128:%vreg804
	%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
	%vreg807<def> = COPY %vreg806:sub0<kill>; VReg_32:%vreg807 VReg_64:%vreg806
	%vreg808<def> = COPY %vreg191<kill>; VReg_64:%vreg808,%vreg191
	%vreg809<def> = COPY %vreg808:sub1<kill>; VReg_32:%vreg809 VReg_64:%vreg808
	%vreg795<def> = V_ADD_I32_e32 %vreg803<kill>, %vreg807<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
	%vreg796<def> = V_ADDC_U32_e32 %vreg805<kill>, %vreg809<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
	%vreg797:sub0<def,read-undef> = COPY %vreg795<kill>; VReg_64:%vreg797 VReg_32:%vreg795
	%vreg797:sub1<def> = COPY %vreg796<kill>; VReg_64:%vreg797 VReg_32:%vreg796
	%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
	%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
	%vreg193<def> = V_MUL_F32_e32 %vreg192<kill>, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
	%vreg195:sub0<def,read-undef> = COPY %vreg194; SGPR_64:%vreg195 SReg_32:%vreg194
	%vreg195:sub1<def> = COPY %vreg181; SGPR_64:%vreg195 SReg_32:%vreg181
	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
	%vreg663<def> = COPY %vreg662:sub0<kill>; VReg_32:%vreg663 VReg_128:%vreg662
	%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
	%vreg665<def> = COPY %vreg664:sub1<kill>; VReg_32:%vreg665 VReg_128:%vreg664
	%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
	%vreg667<def> = COPY %vreg666:sub0<kill>; VReg_32:%vreg667 VReg_64:%vreg666
	%vreg668<def> = COPY %vreg197<kill>; VReg_64:%vreg668,%vreg197
	%vreg669<def> = COPY %vreg668:sub1<kill>; VReg_32:%vreg669 VReg_64:%vreg668
	%vreg655<def> = V_ADD_I32_e32 %vreg663<kill>, %vreg667<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
	%vreg656<def> = V_ADDC_U32_e32 %vreg665<kill>, %vreg669<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
	%vreg657:sub0<def,read-undef> = COPY %vreg655<kill>; VReg_64:%vreg657 VReg_32:%vreg655
	%vreg657:sub1<def> = COPY %vreg656<kill>; VReg_64:%vreg657 VReg_32:%vreg656
	%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
	%vreg199<def> = COPY %vreg195<kill>; VReg_64:%vreg199 SGPR_64:%vreg195
	%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
	%vreg788<def> = COPY %vreg787:sub0<kill>; VReg_32:%vreg788 VReg_128:%vreg787
	%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
	%vreg790<def> = COPY %vreg789:sub1<kill>; VReg_32:%vreg790 VReg_128:%vreg789
	%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
	%vreg792<def> = COPY %vreg791:sub0<kill>; VReg_32:%vreg792 VReg_64:%vreg791
	%vreg793<def> = COPY %vreg199<kill>; VReg_64:%vreg793,%vreg199
	%vreg794<def> = COPY %vreg793:sub1<kill>; VReg_32:%vreg794 VReg_64:%vreg793
	%vreg780<def> = V_ADD_I32_e32 %vreg788<kill>, %vreg792<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
	%vreg781<def> = V_ADDC_U32_e32 %vreg790<kill>, %vreg794<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
	%vreg782:sub0<def,read-undef> = COPY %vreg780<kill>; VReg_64:%vreg782 VReg_32:%vreg780
	%vreg782:sub1<def> = COPY %vreg781<kill>; VReg_64:%vreg782 VReg_32:%vreg781
	%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
	%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
	%vreg201<def> = V_MUL_F32_e32 %vreg200<kill>, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
	%vreg203:sub0<def,read-undef> = COPY %vreg202; SGPR_64:%vreg203 SReg_32:%vreg202
	%vreg203:sub1<def> = COPY %vreg181; SGPR_64:%vreg203 SReg_32:%vreg181
	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
	%vreg648<def> = COPY %vreg647:sub0<kill>; VReg_32:%vreg648 VReg_128:%vreg647
	%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
	%vreg650<def> = COPY %vreg649:sub1<kill>; VReg_32:%vreg650 VReg_128:%vreg649
	%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
	%vreg652<def> = COPY %vreg651:sub0<kill>; VReg_32:%vreg652 VReg_64:%vreg651
	%vreg653<def> = COPY %vreg205<kill>; VReg_64:%vreg653,%vreg205
	%vreg654<def> = COPY %vreg653:sub1<kill>; VReg_32:%vreg654 VReg_64:%vreg653
	%vreg640<def> = V_ADD_I32_e32 %vreg648<kill>, %vreg652<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
	%vreg641<def> = V_ADDC_U32_e32 %vreg650<kill>, %vreg654<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
	%vreg642:sub0<def,read-undef> = COPY %vreg640<kill>; VReg_64:%vreg642 VReg_32:%vreg640
	%vreg642:sub1<def> = COPY %vreg641<kill>; VReg_64:%vreg642 VReg_32:%vreg641
	%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
	%vreg207<def> = COPY %vreg203<kill>; VReg_64:%vreg207 SGPR_64:%vreg203
	%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
	%vreg773<def> = COPY %vreg772:sub0<kill>; VReg_32:%vreg773 VReg_128:%vreg772
	%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
	%vreg775<def> = COPY %vreg774:sub1<kill>; VReg_32:%vreg775 VReg_128:%vreg774
	%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
	%vreg777<def> = COPY %vreg776:sub0<kill>; VReg_32:%vreg777 VReg_64:%vreg776
	%vreg778<def> = COPY %vreg207<kill>; VReg_64:%vreg778,%vreg207
	%vreg779<def> = COPY %vreg778:sub1<kill>; VReg_32:%vreg779 VReg_64:%vreg778
	%vreg765<def> = V_ADD_I32_e32 %vreg773<kill>, %vreg777<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
	%vreg766<def> = V_ADDC_U32_e32 %vreg775<kill>, %vreg779<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
	%vreg767:sub0<def,read-undef> = COPY %vreg765<kill>; VReg_64:%vreg767 VReg_32:%vreg765
	%vreg767:sub1<def> = COPY %vreg766<kill>; VReg_64:%vreg767 VReg_32:%vreg766
	%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
	%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
	%vreg209<def> = V_MUL_F32_e32 %vreg208<kill>, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
	%vreg211:sub0<def,read-undef> = COPY %vreg210; SGPR_64:%vreg211 SReg_32:%vreg210
	%vreg211:sub1<def> = COPY %vreg181; SGPR_64:%vreg211 SReg_32:%vreg181
	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
	%vreg633<def> = COPY %vreg632:sub0<kill>; VReg_32:%vreg633 VReg_128:%vreg632
	%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
	%vreg635<def> = COPY %vreg634:sub1<kill>; VReg_32:%vreg635 VReg_128:%vreg634
	%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
	%vreg637<def> = COPY %vreg636:sub0<kill>; VReg_32:%vreg637 VReg_64:%vreg636
	%vreg638<def> = COPY %vreg213<kill>; VReg_64:%vreg638,%vreg213
	%vreg639<def> = COPY %vreg638:sub1<kill>; VReg_32:%vreg639 VReg_64:%vreg638
	%vreg625<def> = V_ADD_I32_e32 %vreg633<kill>, %vreg637<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
	%vreg626<def> = V_ADDC_U32_e32 %vreg635<kill>, %vreg639<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
	%vreg627:sub0<def,read-undef> = COPY %vreg625<kill>; VReg_64:%vreg627 VReg_32:%vreg625
	%vreg627:sub1<def> = COPY %vreg626<kill>; VReg_64:%vreg627 VReg_32:%vreg626
	%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
	%vreg215<def> = COPY %vreg211<kill>; VReg_64:%vreg215 SGPR_64:%vreg211
	%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
	%vreg758<def> = COPY %vreg757:sub0<kill>; VReg_32:%vreg758 VReg_128:%vreg757
	%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
	%vreg760<def> = COPY %vreg759:sub1<kill>; VReg_32:%vreg760 VReg_128:%vreg759
	%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
	%vreg762<def> = COPY %vreg761:sub0<kill>; VReg_32:%vreg762 VReg_64:%vreg761
	%vreg763<def> = COPY %vreg215<kill>; VReg_64:%vreg763,%vreg215
	%vreg764<def> = COPY %vreg763:sub1<kill>; VReg_32:%vreg764 VReg_64:%vreg763
	%vreg750<def> = V_ADD_I32_e32 %vreg758<kill>, %vreg762<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
	%vreg751<def> = V_ADDC_U32_e32 %vreg760<kill>, %vreg764<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
	%vreg752:sub0<def,read-undef> = COPY %vreg750<kill>; VReg_64:%vreg752 VReg_32:%vreg750
	%vreg752:sub1<def> = COPY %vreg751<kill>; VReg_64:%vreg752 VReg_32:%vreg751
	%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
	%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
	%vreg217<def> = V_MUL_F32_e32 %vreg216<kill>, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
	%vreg219:sub0<def,read-undef> = COPY %vreg218; SGPR_64:%vreg219 SReg_32:%vreg218
	%vreg219:sub1<def> = COPY %vreg181; SGPR_64:%vreg219 SReg_32:%vreg181
	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
	%vreg618<def> = COPY %vreg617:sub0<kill>; VReg_32:%vreg618 VReg_128:%vreg617
	%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
	%vreg620<def> = COPY %vreg619:sub1<kill>; VReg_32:%vreg620 VReg_128:%vreg619
	%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
	%vreg622<def> = COPY %vreg621:sub0<kill>; VReg_32:%vreg622 VReg_64:%vreg621
	%vreg623<def> = COPY %vreg221<kill>; VReg_64:%vreg623,%vreg221
	%vreg624<def> = COPY %vreg623:sub1<kill>; VReg_32:%vreg624 VReg_64:%vreg623
	%vreg610<def> = V_ADD_I32_e32 %vreg618<kill>, %vreg622<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
	%vreg611<def> = V_ADDC_U32_e32 %vreg620<kill>, %vreg624<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
	%vreg612:sub0<def,read-undef> = COPY %vreg610<kill>; VReg_64:%vreg612 VReg_32:%vreg610
	%vreg612:sub1<def> = COPY %vreg611<kill>; VReg_64:%vreg612 VReg_32:%vreg611
	%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
	%vreg223<def> = COPY %vreg219<kill>; VReg_64:%vreg223 SGPR_64:%vreg219
	%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
	%vreg743<def> = COPY %vreg742:sub0<kill>; VReg_32:%vreg743 VReg_128:%vreg742
	%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
	%vreg745<def> = COPY %vreg744:sub1<kill>; VReg_32:%vreg745 VReg_128:%vreg744
	%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
	%vreg747<def> = COPY %vreg746:sub0<kill>; VReg_32:%vreg747 VReg_64:%vreg746
	%vreg748<def> = COPY %vreg223<kill>; VReg_64:%vreg748,%vreg223
	%vreg749<def> = COPY %vreg748:sub1<kill>; VReg_32:%vreg749 VReg_64:%vreg748
	%vreg735<def> = V_ADD_I32_e32 %vreg743<kill>, %vreg747<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
	%vreg736<def> = V_ADDC_U32_e32 %vreg745<kill>, %vreg749<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
	%vreg737:sub0<def,read-undef> = COPY %vreg735<kill>; VReg_64:%vreg737 VReg_32:%vreg735
	%vreg737:sub1<def> = COPY %vreg736<kill>; VReg_64:%vreg737 VReg_32:%vreg736
	%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
	%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
	%vreg225<def> = V_MUL_F32_e32 %vreg224<kill>, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
	%vreg227:sub0<def,read-undef> = COPY %vreg226; SGPR_64:%vreg227 SReg_32:%vreg226
	%vreg227:sub1<def> = COPY %vreg181; SGPR_64:%vreg227 SReg_32:%vreg181
	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
	%vreg603<def> = COPY %vreg602:sub0<kill>; VReg_32:%vreg603 VReg_128:%vreg602
	%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
	%vreg605<def> = COPY %vreg604:sub1<kill>; VReg_32:%vreg605 VReg_128:%vreg604
	%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
	%vreg607<def> = COPY %vreg606:sub0<kill>; VReg_32:%vreg607 VReg_64:%vreg606
	%vreg608<def> = COPY %vreg229<kill>; VReg_64:%vreg608,%vreg229
	%vreg609<def> = COPY %vreg608:sub1<kill>; VReg_32:%vreg609 VReg_64:%vreg608
	%vreg595<def> = V_ADD_I32_e32 %vreg603<kill>, %vreg607<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
	%vreg596<def> = V_ADDC_U32_e32 %vreg605<kill>, %vreg609<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
	%vreg597:sub0<def,read-undef> = COPY %vreg595<kill>; VReg_64:%vreg597 VReg_32:%vreg595
	%vreg597:sub1<def> = COPY %vreg596<kill>; VReg_64:%vreg597 VReg_32:%vreg596
	%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
	%vreg231<def> = COPY %vreg227<kill>; VReg_64:%vreg231 SGPR_64:%vreg227
	%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
	%vreg728<def> = COPY %vreg727:sub0<kill>; VReg_32:%vreg728 VReg_128:%vreg727
	%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
	%vreg730<def> = COPY %vreg729:sub1<kill>; VReg_32:%vreg730 VReg_128:%vreg729
	%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
	%vreg732<def> = COPY %vreg731:sub0<kill>; VReg_32:%vreg732 VReg_64:%vreg731
	%vreg733<def> = COPY %vreg231<kill>; VReg_64:%vreg733,%vreg231
	%vreg734<def> = COPY %vreg733:sub1<kill>; VReg_32:%vreg734 VReg_64:%vreg733
	%vreg720<def> = V_ADD_I32_e32 %vreg728<kill>, %vreg732<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
	%vreg721<def> = V_ADDC_U32_e32 %vreg730<kill>, %vreg734<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
	%vreg722:sub0<def,read-undef> = COPY %vreg720<kill>; VReg_64:%vreg722 VReg_32:%vreg720
	%vreg722:sub1<def> = COPY %vreg721<kill>; VReg_64:%vreg722 VReg_32:%vreg721
	%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
	%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
	%vreg233<def> = V_MUL_F32_e32 %vreg232<kill>, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
	%vreg235:sub0<def,read-undef> = COPY %vreg234; SGPR_64:%vreg235 SReg_32:%vreg234
	%vreg235:sub1<def> = COPY %vreg181; SGPR_64:%vreg235 SReg_32:%vreg181
	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
	%vreg588<def> = COPY %vreg587:sub0<kill>; VReg_32:%vreg588 VReg_128:%vreg587
	%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
	%vreg590<def> = COPY %vreg589:sub1<kill>; VReg_32:%vreg590 VReg_128:%vreg589
	%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
	%vreg592<def> = COPY %vreg591:sub0<kill>; VReg_32:%vreg592 VReg_64:%vreg591
	%vreg593<def> = COPY %vreg237<kill>; VReg_64:%vreg593,%vreg237
	%vreg594<def> = COPY %vreg593:sub1<kill>; VReg_32:%vreg594 VReg_64:%vreg593
	%vreg580<def> = V_ADD_I32_e32 %vreg588<kill>, %vreg592<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
	%vreg581<def> = V_ADDC_U32_e32 %vreg590<kill>, %vreg594<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
	%vreg582:sub0<def,read-undef> = COPY %vreg580<kill>; VReg_64:%vreg582 VReg_32:%vreg580
	%vreg582:sub1<def> = COPY %vreg581<kill>; VReg_64:%vreg582 VReg_32:%vreg581
	%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
	%vreg239<def> = COPY %vreg235<kill>; VReg_64:%vreg239 SGPR_64:%vreg235
	%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
	%vreg713<def> = COPY %vreg712:sub0<kill>; VReg_32:%vreg713 VReg_128:%vreg712
	%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
	%vreg715<def> = COPY %vreg714:sub1<kill>; VReg_32:%vreg715 VReg_128:%vreg714
	%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
	%vreg717<def> = COPY %vreg716:sub0<kill>; VReg_32:%vreg717 VReg_64:%vreg716
	%vreg718<def> = COPY %vreg239<kill>; VReg_64:%vreg718,%vreg239
	%vreg719<def> = COPY %vreg718:sub1<kill>; VReg_32:%vreg719 VReg_64:%vreg718
	%vreg705<def> = V_ADD_I32_e32 %vreg713<kill>, %vreg717<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
	%vreg706<def> = V_ADDC_U32_e32 %vreg715<kill>, %vreg719<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
	%vreg707:sub0<def,read-undef> = COPY %vreg705<kill>; VReg_64:%vreg707 VReg_32:%vreg705
	%vreg707:sub1<def> = COPY %vreg706<kill>; VReg_64:%vreg707 VReg_32:%vreg706
	%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
	%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
	%vreg241<def> = V_MUL_F32_e32 %vreg240<kill>, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
	%vreg243:sub0<def,read-undef> = COPY %vreg242; SGPR_64:%vreg243 SReg_32:%vreg242
	%vreg243:sub1<def> = COPY %vreg181; SGPR_64:%vreg243 SReg_32:%vreg181
	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
	%vreg573<def> = COPY %vreg572:sub0<kill>; VReg_32:%vreg573 VReg_128:%vreg572
	%vreg574<def> = COPY %vreg562<kill>; VReg_128:%vreg574,%vreg562
	%vreg575<def> = COPY %vreg574:sub1<kill>; VReg_32:%vreg575 VReg_128:%vreg574
	%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
	%vreg577<def> = COPY %vreg576:sub0<kill>; VReg_32:%vreg577 VReg_64:%vreg576
	%vreg578<def> = COPY %vreg245<kill>; VReg_64:%vreg578,%vreg245
	%vreg579<def> = COPY %vreg578:sub1<kill>; VReg_32:%vreg579 VReg_64:%vreg578
	%vreg565<def> = V_ADD_I32_e32 %vreg573<kill>, %vreg577<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
	%vreg566<def> = V_ADDC_U32_e32 %vreg575<kill>, %vreg579<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
	%vreg567:sub0<def,read-undef> = COPY %vreg565<kill>; VReg_64:%vreg567 VReg_32:%vreg565
	%vreg567:sub1<def> = COPY %vreg566<kill>; VReg_64:%vreg567 VReg_32:%vreg566
	%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
	%vreg247<def> = COPY %vreg243<kill>; VReg_64:%vreg247 SGPR_64:%vreg243
	%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
	%vreg698<def> = COPY %vreg697:sub0<kill>; VReg_32:%vreg698 VReg_128:%vreg697
	%vreg699<def> = COPY %vreg687<kill>; VReg_128:%vreg699,%vreg687
	%vreg700<def> = COPY %vreg699:sub1<kill>; VReg_32:%vreg700 VReg_128:%vreg699
	%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
	%vreg702<def> = COPY %vreg701:sub0<kill>; VReg_32:%vreg702 VReg_64:%vreg701
	%vreg703<def> = COPY %vreg247<kill>; VReg_64:%vreg703,%vreg247
	%vreg704<def> = COPY %vreg703:sub1<kill>; VReg_32:%vreg704 VReg_64:%vreg703
	%vreg690<def> = V_ADD_I32_e32 %vreg698<kill>, %vreg702<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
	%vreg691<def> = V_ADDC_U32_e32 %vreg700<kill>, %vreg704<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
	%vreg692:sub0<def,read-undef> = COPY %vreg690<kill>; VReg_64:%vreg692 VReg_32:%vreg690
	%vreg692:sub1<def> = COPY %vreg691<kill>; VReg_64:%vreg692 VReg_32:%vreg691
	%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676<kill>, %vreg692<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
	%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
	%vreg249<def> = V_MUL_F32_e32 %vreg248<kill>, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
	%vreg250:sub0<def,read-undef> = COPY %vreg249<kill>; VReg_512:%vreg250 VGPR_32:%vreg249
	%vreg250:sub1<def> = COPY %vreg241<kill>; VReg_512:%vreg250 VGPR_32:%vreg241
	%vreg250:sub2<def> = COPY %vreg233<kill>; VReg_512:%vreg250 VGPR_32:%vreg233
	%vreg250:sub3<def> = COPY %vreg225<kill>; VReg_512:%vreg250 VGPR_32:%vreg225
	%vreg250:sub4<def> = COPY %vreg217<kill>; VReg_512:%vreg250 VGPR_32:%vreg217
	%vreg250:sub5<def> = COPY %vreg209<kill>; VReg_512:%vreg250 VGPR_32:%vreg209
	%vreg250:sub6<def> = COPY %vreg201<kill>; VReg_512:%vreg250 VGPR_32:%vreg201
	%vreg250:sub7<def> = COPY %vreg193<kill>; VReg_512:%vreg250 VGPR_32:%vreg193
	%vreg250:sub8<def> = COPY %vreg180<kill>; VReg_512:%vreg250 VGPR_32:%vreg180
	%vreg250:sub9<def> = COPY %vreg176<kill>; VReg_512:%vreg250 VGPR_32:%vreg176
	%vreg250:sub10<def> = COPY %vreg172<kill>; VReg_512:%vreg250 VGPR_32:%vreg172
	%vreg250:sub11<def> = COPY %vreg168<kill>; VReg_512:%vreg250 VGPR_32:%vreg168
	%vreg250:sub12<def> = COPY %vreg164<kill>; VReg_512:%vreg250 VGPR_32:%vreg164
	%vreg250:sub13<def> = COPY %vreg160<kill>; VReg_512:%vreg250 VGPR_32:%vreg160
	%vreg250:sub14<def> = COPY %vreg156<kill>; VReg_512:%vreg250 VGPR_32:%vreg156
	%vreg250:sub15<def> = COPY %vreg152<kill>; VReg_512:%vreg250 VGPR_32:%vreg152
	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
	%vreg280<def> = COPY %vreg250:sub15<kill>; VSrc_32:%vreg280 VReg_512:%vreg250
	%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
	%vreg282<def> = V_ADD_F32_e32 %vreg26<kill>, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	%vreg816<def> = COPY %vreg23:sub1<kill>; VReg_32:%vreg816 VReg_64:%vreg23
	%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
	%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
	%vreg817<def> = V_ADDC_U32_e32 %vreg816<kill>, %vreg818<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg817,%vreg816,%vreg818
	%vreg812:sub0<def,read-undef> = COPY %vreg811<kill>; VReg_64:%vreg812 VReg_32:%vreg811
	%vreg812:sub1<def> = COPY %vreg817<kill>; VReg_64:%vreg812 VReg_32:%vreg817
	%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
	%vreg825<def> = COPY %vreg24:sub1<kill>; VReg_32:%vreg825 VReg_64:%vreg24
	%vreg820<def> = V_ADD_I32_e32 %vreg284<kill>, %vreg819<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
	%vreg827<def> = COPY %vreg286<kill>; VReg_32:%vreg827 SReg_32:%vreg286
	%vreg826<def> = V_ADDC_U32_e32 %vreg825<kill>, %vreg827<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg826,%vreg825,%vreg827
	%vreg821:sub0<def,read-undef> = COPY %vreg820<kill>; VReg_64:%vreg821 VReg_32:%vreg820
	%vreg821:sub1<def> = COPY %vreg826<kill>; VReg_64:%vreg821 VReg_32:%vreg826
	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	%vreg545<def> = V_ADD_I32_e32 16, %vreg542<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg545,%vreg542
	%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
	%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	%vreg815<def> = COPY %vreg812<kill>; VReg_64:%vreg815,%vreg812
	%vreg824<def> = COPY %vreg821<kill>; VReg_64:%vreg824,%vreg821
	%vreg27<def> = COPY %vreg282<kill>; VGPR_32:%vreg27,%vreg282
	%vreg544<def> = COPY %vreg545<kill>; VReg_32:%vreg544,%vreg545
	%vreg851<def> = COPY %vreg31; SReg_64:%vreg851,%vreg31
	%vreg852<def> = COPY %vreg815<kill>; VReg_64:%vreg852,%vreg815
	%vreg853<def> = COPY %vreg824<kill>; VReg_64:%vreg853,%vreg824
	%vreg854<def> = COPY %vreg544<kill>; VReg_32:%vreg854,%vreg544
	%vreg855<def> = COPY %vreg27; VGPR_32:%vreg855,%vreg27
	SI_LOOP %vreg298<kill>, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Predecessors according to CFG: BB#5 BB#11
	%vreg32<def> = COPY %vreg856<kill>; VGPR_32:%vreg32,%vreg856
	SI_END_CF %vreg302<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Predecessors according to CFG: BB#6 BB#10
	%vreg37<def> = COPY %vreg861<kill>; VGPR_32:%vreg37,%vreg861
	%vreg455<def> = COPY %vreg860<kill>; VReg_32:%vreg455,%vreg860
	%vreg35<def> = COPY %vreg859<kill>; VReg_64:%vreg35,%vreg859
	%vreg34<def> = COPY %vreg858<kill>; VReg_64:%vreg34,%vreg858
	%vreg33<def> = COPY %vreg857<kill>; SReg_64:%vreg33,%vreg857
	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
	%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
	%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
	%vreg835<def> = V_ADDC_U32_e32 %vreg834<kill>, %vreg836<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg835,%vreg834,%vreg836
	%vreg830:sub0<def,read-undef> = COPY %vreg829<kill>; VReg_64:%vreg830 VReg_32:%vreg829
	%vreg830:sub1<def> = COPY %vreg835<kill>; VReg_64:%vreg830 VReg_32:%vreg835
	%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
	%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
	%vreg838<def> = V_ADD_I32_e32 %vreg354<kill>, %vreg837<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
	%vreg845<def> = COPY %vreg356<kill>; VReg_32:%vreg845 SReg_32:%vreg356
	%vreg844<def> = V_ADDC_U32_e32 %vreg843<kill>, %vreg845<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg844,%vreg843,%vreg845
	%vreg839:sub0<def,read-undef> = COPY %vreg838<kill>; VReg_64:%vreg839 VReg_32:%vreg838
	%vreg839:sub1<def> = COPY %vreg844<kill>; VReg_64:%vreg839 VReg_32:%vreg844
	%vreg411:sub0<def,read-undef> = COPY %vreg413; SGPR_64:%vreg411 SGPR_32:%vreg413
	%vreg411:sub1<def> = COPY %vreg412; SGPR_64:%vreg411 SGPR_32:%vreg412
	%vreg366:sub0_sub1<def,read-undef> = COPY %vreg352; SReg_128:%vreg366 SGPR_64:%vreg352
	%vreg366:sub2_sub3<def> = COPY %vreg411<kill>; SReg_128:%vreg366 SGPR_64:%vreg411
	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366<kill>, %vreg34<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
	%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
	%vreg370<def> = V_MAD_F32 %vreg369<kill>, %vreg369, %vreg37<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
	%vreg458<def> = V_ADD_I32_e32 -1, %vreg455<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg458,%vreg455
	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
	%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	%vreg833<def> = COPY %vreg830<kill>; VReg_64:%vreg833,%vreg830
	%vreg842<def> = COPY %vreg839<kill>; VReg_64:%vreg842,%vreg839
	%vreg38<def> = COPY %vreg370<kill>; VGPR_32:%vreg38,%vreg370
	%vreg457<def> = COPY %vreg458<kill>; VReg_32:%vreg457,%vreg458
	%vreg857<def> = COPY %vreg42; SReg_64:%vreg857,%vreg42
	%vreg858<def> = COPY %vreg833<kill>; VReg_64:%vreg858,%vreg833
	%vreg859<def> = COPY %vreg842<kill>; VReg_64:%vreg859,%vreg842
	%vreg860<def> = COPY %vreg457<kill>; VReg_32:%vreg860,%vreg457
	%vreg861<def> = COPY %vreg38; VGPR_32:%vreg861,%vreg38
	SI_LOOP %vreg372<kill>, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Predecessors according to CFG: BB#10
	SI_END_CF %vreg42<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg42
	%vreg856<def> = COPY %vreg38<kill>; VGPR_32:%vreg856,%vreg38
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Predecessors according to CFG: BB#9
	%vreg373<def> = COPY %vreg54<kill>; VGPR_32:%vreg373 SReg_32:%vreg54
	%vreg374<def> = V_MUL_LO_I32 %vreg440<kill>, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
	%vreg424<def> = V_ADD_I32_e32 %vreg374<kill>, %vreg423<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg424,%vreg374,%vreg423
	%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
	%vreg425:sub0<def,read-undef> = COPY %vreg424<kill>; VReg_64:%vreg425 VReg_32:%vreg424
	%vreg425:sub1<def> = COPY %vreg437<kill>; VReg_64:%vreg425 VReg_32:%vreg437
	%vreg428<def> = V_LSHL_B64 %vreg425<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
	%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
	%vreg429<def> = COPY %vreg428:sub1<kill>; VReg_32:%vreg429 VReg_64:%vreg428
	%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
	%vreg848<def> = COPY %vreg53:sub1<kill>; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
	%vreg436<def> = V_ADD_I32_e32 %vreg847<kill>, %vreg435<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
	%vreg430<def> = V_ADDC_U32_e32 %vreg848<kill>, %vreg429<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg430,%vreg848,%vreg429
	%vreg432:sub0<def,read-undef> = COPY %vreg436<kill>; VReg_64:%vreg432 VReg_32:%vreg436
	%vreg432:sub1<def> = COPY %vreg430<kill>; VReg_64:%vreg432 VReg_32:%vreg430
	%vreg388<def> = V_MUL_F32_e64 %vreg32<kill>, %vreg56<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg32,%vreg56
	%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
	%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
	%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
	%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
	%vreg45<def> = COPY %vreg432<kill>; VReg_64:%vreg45,%vreg432
	%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Predecessors according to CFG: BB#12 BB#15
	%vreg395<def> = COPY %vreg393<kill>; SReg_64:%vreg395,%vreg393
	%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Predecessors according to CFG: BB#13
	%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
	%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
	%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
	%vreg415:sub0<def,read-undef> = COPY %vreg417<kill>; SGPR_64:%vreg415 SGPR_32:%vreg417
	%vreg415:sub1<def> = COPY %vreg416<kill>; SGPR_64:%vreg415 SGPR_32:%vreg416
	%vreg396:sub0_sub1<def,read-undef> = COPY %vreg414<kill>; SReg_128:%vreg396 SGPR_64:%vreg414
	%vreg396:sub2_sub3<def> = COPY %vreg415<kill>; SReg_128:%vreg396 SGPR_64:%vreg415
	%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
	BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Predecessors according to CFG: BB#12
	%vreg44<def> = COPY %vreg388<kill>; VGPR_32:%vreg44,%vreg388
	%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
	%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
	%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
	%vreg419:sub0<def,read-undef> = COPY %vreg421<kill>; SGPR_64:%vreg419 SGPR_32:%vreg421
	%vreg419:sub1<def> = COPY %vreg420<kill>; SGPR_64:%vreg419 SGPR_32:%vreg420
	%vreg394:sub0_sub1<def,read-undef> = COPY %vreg418<kill>; SReg_128:%vreg394 SGPR_64:%vreg418
	%vreg394:sub2_sub3<def> = COPY %vreg419<kill>; SReg_128:%vreg394 SGPR_64:%vreg419
	BUFFER_STORE_DWORD %vreg44<kill>, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %vreg395<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Live Interval Analysis ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg60<def> = COPY %SGPR2<kill>; SReg_32:%vreg60
32B		%vreg59<def> = COPY %VGPR0<kill>; VReg_32:%vreg59
48B		%vreg58<def> = COPY %SGPR3<kill>; SReg_32:%vreg58
64B		%vreg57<def> = COPY %VGPR1<kill>; VReg_32:%vreg57
80B		%vreg48<def> = COPY %SGPR0_SGPR1<kill>; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
112B		%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63<kill>, %vreg59, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg59
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66<kill>; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
224B		%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71<kill>, %vreg57, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg57
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74<kill>; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
368B		%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
384B		%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
400B		%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
416B		%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
432B		%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
448B		%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48<kill>, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
464B		%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
512B		%vreg442<def> = COPY %vreg57<kill>; VReg_32:%vreg442,%vreg57
528B		%vreg4<def> = COPY %vreg58<kill>; SReg_32:%vreg4,%vreg58
544B		%vreg445<def> = COPY %vreg59<kill>; VReg_32:%vreg445,%vreg59
560B		%vreg0<def> = COPY %vreg60<kill>; SReg_32:%vreg0,%vreg60
576B		%vreg5<def> = COPY %vreg70<kill>; SReg_32:%vreg5 SGPR_32:%vreg70
592B		%vreg1<def> = COPY %vreg62<kill>; SReg_32:%vreg1 SGPR_32:%vreg62
608B		%vreg55<def> = COPY %vreg79<kill>; SReg_32:%vreg55 SGPR_32:%vreg79
624B		%vreg52<def> = COPY %vreg82<kill>; SReg_32:%vreg52 SGPR_32:%vreg82
640B		%vreg51<def> = COPY %vreg83<kill>; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
656B		%vreg50<def> = COPY %vreg84<kill>; SReg_32:%vreg50 SGPR_32:%vreg84
672B		%vreg49<def> = COPY %vreg85<kill>; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
736B		%vreg448<def> = COPY %vreg90<kill>; VReg_32:%vreg448,%vreg90
752B		%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
768B		%vreg87<def> = COPY %vreg91<kill>; VGPR_32:%vreg87,%vreg91
784B		%vreg450<def> = COPY %vreg448<kill>; VReg_32:%vreg450,%vreg448
800B		%vreg849<def> = COPY %vreg87<kill>; VGPR_32:%vreg849,%vreg87
816B		%vreg850<def> = COPY %vreg450<kill>; VReg_32:%vreg850,%vreg450
832B		%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97<kill>, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg443<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg443
944B		%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg101, %EXEC<imp-use>; VReg_32:%vreg497,%vreg101
960B		%vreg104:sub0<def,read-undef> = COPY %vreg101<kill>; VReg_64:%vreg104 VReg_32:%vreg101
976B		%vreg104:sub1<def> = COPY %vreg497<kill>; VReg_64:%vreg104 VReg_32:%vreg497
992B		%vreg499<def> = V_LSHL_B64 %vreg104<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1008B		%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
1024B		%vreg500<def> = COPY %vreg499:sub1<kill>; VReg_32:%vreg500 VReg_64:%vreg499
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
1072B		%vreg515<def> = V_ADD_I32_e32 %vreg516<kill>, %vreg514<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
1088B		%vreg501<def> = V_ADDC_U32_e32 %vreg500<kill>, %vreg517<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg501,%vreg500,%vreg517
1104B		%vreg503:sub0<def,read-undef> = COPY %vreg515<kill>; VReg_64:%vreg503 VReg_32:%vreg515
1120B		%vreg503:sub1<def> = COPY %vreg501<kill>; VReg_64:%vreg503 VReg_32:%vreg501
1136B		%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
1152B		%vreg506<def> = COPY %vreg503:sub1<kill>; VReg_32:%vreg506 VReg_64:%vreg503
1168B		%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
1184B		%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
1200B		%vreg118<def> = COPY %vreg116:sub1<kill>; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
1216B		%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
1232B		%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
1248B		%vreg507<def> = V_ADDC_U32_e32 %vreg506<kill>, %vreg508<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg507,%vreg506,%vreg508
1264B		%vreg509:sub0<def,read-undef> = COPY %vreg513<kill>; VReg_64:%vreg509 VReg_32:%vreg513
1280B		%vreg509:sub1<def> = COPY %vreg507<kill>; VReg_64:%vreg509 VReg_32:%vreg507
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123<kill>, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg446<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg127, %EXEC<imp-use>; VReg_32:%vreg520,%vreg127
1376B		%vreg130:sub0<def,read-undef> = COPY %vreg127<kill>; VReg_64:%vreg130 VReg_32:%vreg127
1392B		%vreg130:sub1<def> = COPY %vreg520<kill>; VReg_64:%vreg130 VReg_32:%vreg520
1408B		%vreg522<def> = V_LSHL_B64 %vreg130<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1424B		%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
1440B		%vreg523<def> = COPY %vreg522:sub1<kill>; VReg_32:%vreg523 VReg_64:%vreg522
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
1488B		%vreg538<def> = V_ADD_I32_e32 %vreg539<kill>, %vreg537<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
1504B		%vreg524<def> = V_ADDC_U32_e32 %vreg523<kill>, %vreg540<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg524,%vreg523,%vreg540
1520B		%vreg526:sub0<def,read-undef> = COPY %vreg538<kill>; VReg_64:%vreg526 VReg_32:%vreg538
1536B		%vreg526:sub1<def> = COPY %vreg524<kill>; VReg_64:%vreg526 VReg_32:%vreg524
1552B		%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
1568B		%vreg529<def> = COPY %vreg526:sub1<kill>; VReg_32:%vreg529 VReg_64:%vreg526
1584B		%vreg536<def> = V_ADD_I32_e32 %vreg117<kill>, %vreg535<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
1600B		%vreg531<def> = COPY %vreg118<kill>; VReg_32:%vreg531 SReg_32:%vreg118
1616B		%vreg530<def> = V_ADDC_U32_e32 %vreg529<kill>, %vreg531<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg530,%vreg529,%vreg531
1632B		%vreg532:sub0<def,read-undef> = COPY %vreg536<kill>; VReg_64:%vreg532 VReg_32:%vreg536
1648B		%vreg532:sub1<def> = COPY %vreg530<kill>; VReg_64:%vreg532 VReg_32:%vreg530
1664B		%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
1680B		%vreg95<def> = COPY %vreg145<kill>; VGPR_32:%vreg95,%vreg145
1696B		%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
1712B		%vreg541<def> = COPY %vreg146<kill>; VReg_32:%vreg541,%vreg146
1728B		%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
1744B		%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
1760B		%vreg12<def> = COPY %vreg509<kill>; VReg_64:%vreg12,%vreg509
1776B		%vreg11<def> = COPY %vreg532<kill>; VReg_64:%vreg11,%vreg532
1792B		%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
1808B		%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
1824B		%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
1840B		%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
1856B		%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
1872B		%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
1888B		%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
1904B		%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
1920B		%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
1936B		%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
1952B		%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
1968B		%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
1984B		%vreg543<def> = COPY %vreg541<kill>; VReg_32:%vreg543,%vreg541
2000B		%vreg851<def> = COPY %vreg93<kill>; SReg_64:%vreg851 SGPR_64:%vreg93
2016B		%vreg852<def> = COPY %vreg12<kill>; VReg_64:%vreg852,%vreg12
2032B		%vreg853<def> = COPY %vreg11<kill>; VReg_64:%vreg853,%vreg11
2048B		%vreg854<def> = COPY %vreg543<kill>; VReg_32:%vreg854,%vreg543
2064B		%vreg855<def> = COPY %vreg95<kill>; VGPR_32:%vreg855,%vreg95
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg31<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg31
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg451<def> = COPY %vreg13<kill>; VReg_32:%vreg451 SReg_32:%vreg13
2176B		%vreg849<def> = COPY %vreg27<kill>; VGPR_32:%vreg849,%vreg27
2192B		%vreg850<def> = COPY %vreg451<kill>; VReg_32:%vreg850,%vreg451
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg453, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg453 VGPR_32:%vreg300
2320B		%vreg856<def> = COPY %vreg20; VGPR_32:%vreg856,%vreg20
2336B		%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4<kill>; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5<kill>, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305<kill>, %vreg442<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg309<def> = V_MUL_LO_I32 %vreg50<kill>, %vreg444<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg309, %EXEC<imp-use>; VReg_32:%vreg548,%vreg309
2464B		%vreg312:sub0<def,read-undef> = COPY %vreg309<kill>; VReg_64:%vreg312 VReg_32:%vreg309
2480B		%vreg312:sub1<def> = COPY %vreg548<kill>; VReg_64:%vreg312 VReg_32:%vreg548
2496B		%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
2512B		%vreg550<def> = COPY %vreg312:sub1<kill>; VReg_32:%vreg550 VReg_64:%vreg312
2528B		%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg453, %EXEC<imp-use>; VReg_32:%vreg494,%vreg453
2544B		%vreg459:sub0<def,read-undef> = COPY %vreg453; VReg_64:%vreg459 VReg_32:%vreg453
2560B		%vreg459:sub1<def> = COPY %vreg494<kill>; VReg_64:%vreg459 VReg_32:%vreg494
2576B		%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
2592B		%vreg462<def> = COPY %vreg459:sub1<kill>; VReg_32:%vreg462 VReg_64:%vreg459
2608B		%vreg493<def> = V_ADD_I32_e32 %vreg549<kill>, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
2624B		%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg550<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg477,%vreg462,%vreg550
2640B		%vreg479:sub0<def,read-undef> = COPY %vreg493<kill>; VReg_64:%vreg479 VReg_32:%vreg493
2656B		%vreg479:sub1<def> = COPY %vreg477<kill>; VReg_64:%vreg479 VReg_32:%vreg477
2672B		%vreg482<def> = V_LSHL_B64 %vreg479<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2688B		%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
2704B		%vreg483<def> = COPY %vreg482:sub1<kill>; VReg_32:%vreg483 VReg_64:%vreg482
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1<kill>; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
2752B		%vreg490<def> = V_ADD_I32_e32 %vreg551<kill>, %vreg489<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
2768B		%vreg484<def> = V_ADDC_U32_e32 %vreg552<kill>, %vreg483<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg484,%vreg552,%vreg483
2784B		%vreg486:sub0<def,read-undef> = COPY %vreg490<kill>; VReg_64:%vreg486 VReg_32:%vreg490
2800B		%vreg486:sub1<def> = COPY %vreg484<kill>; VReg_64:%vreg486 VReg_32:%vreg484
2816B		%vreg330<def> = COPY %vreg0<kill>; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1<kill>, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331<kill>, %vreg445<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg335<def> = V_MUL_LO_I32 %vreg52<kill>, %vreg447<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg335, %EXEC<imp-use>; VReg_32:%vreg555,%vreg335
2896B		%vreg338:sub0<def,read-undef> = COPY %vreg335<kill>; VReg_64:%vreg338 VReg_32:%vreg335
2912B		%vreg338:sub1<def> = COPY %vreg555<kill>; VReg_64:%vreg338 VReg_32:%vreg555
2928B		%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
2944B		%vreg557<def> = COPY %vreg338:sub1<kill>; VReg_32:%vreg557 VReg_64:%vreg338
2960B		%vreg492<def> = V_ADD_I32_e32 %vreg556<kill>, %vreg491<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
2976B		%vreg463<def> = V_ADDC_U32_e32 %vreg462<kill>, %vreg557<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg463,%vreg462,%vreg557
2992B		%vreg465:sub0<def,read-undef> = COPY %vreg492<kill>; VReg_64:%vreg465 VReg_32:%vreg492
3008B		%vreg465:sub1<def> = COPY %vreg463<kill>; VReg_64:%vreg465 VReg_32:%vreg463
3024B		%vreg468<def> = V_LSHL_B64 %vreg465<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3040B		%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
3056B		%vreg469<def> = COPY %vreg468:sub1<kill>; VReg_32:%vreg469 VReg_64:%vreg468
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1<kill>; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
3104B		%vreg476<def> = V_ADD_I32_e32 %vreg558<kill>, %vreg475<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
3120B		%vreg470<def> = V_ADDC_U32_e32 %vreg559<kill>, %vreg469<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg470,%vreg559,%vreg469
3136B		%vreg472:sub0<def,read-undef> = COPY %vreg476<kill>; VReg_64:%vreg472 VReg_32:%vreg476
3152B		%vreg472:sub1<def> = COPY %vreg470<kill>; VReg_64:%vreg472 VReg_32:%vreg470
3168B		%vreg454<def> = V_SUB_I32_e32 %vreg55<kill>, %vreg453<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg454,%vreg453 SReg_32:%vreg55
3184B		%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
3200B		%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
3216B		%vreg19<def> = COPY %vreg486<kill>; VReg_64:%vreg19,%vreg486
3232B		%vreg18<def> = COPY %vreg472<kill>; VReg_64:%vreg18,%vreg472
3248B		%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
3264B		%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
3280B		%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
3296B		%vreg456<def> = COPY %vreg454<kill>; VReg_32:%vreg456,%vreg454
3312B		%vreg857<def> = COPY %vreg303<kill>; SReg_64:%vreg857 SGPR_64:%vreg303
3328B		%vreg858<def> = COPY %vreg19<kill>; VReg_64:%vreg858,%vreg19
3344B		%vreg859<def> = COPY %vreg18<kill>; VReg_64:%vreg859,%vreg18
3360B		%vreg860<def> = COPY %vreg456<kill>; VReg_32:%vreg860,%vreg456
3376B		%vreg861<def> = COPY %vreg20<kill>; VGPR_32:%vreg861,%vreg20
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3424B		%vreg449<def> = COPY %vreg850<kill>; VReg_32:%vreg449,%vreg850
3440B		%vreg20<def> = COPY %vreg849<kill>; VGPR_32:%vreg20,%vreg849
3456B		%vreg56<def> = COPY %vreg78<kill>; VGPR_32:%vreg56 SGPR_32:%vreg78
3472B		%vreg54<def> = COPY %vreg80<kill>; SReg_32:%vreg54 SGPR_32:%vreg80
3488B		%vreg53<def> = COPY %vreg81<kill>; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
3504B		SI_END_CF %vreg92<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3520B		%vreg453<def> = COPY %vreg449<kill>; VReg_32:%vreg453,%vreg449
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3568B		%vreg26<def> = COPY %vreg855<kill>; VGPR_32:%vreg26,%vreg855
3584B		%vreg542<def> = COPY %vreg854<kill>; VReg_32:%vreg542,%vreg854
3600B		%vreg24<def> = COPY %vreg853<kill>; VReg_64:%vreg24,%vreg853
3616B		%vreg23<def> = COPY %vreg852<kill>; VReg_64:%vreg23,%vreg852
3632B		%vreg22<def> = COPY %vreg851<kill>; SReg_64:%vreg22,%vreg851
3648B		%vreg399:sub0<def,read-undef> = COPY %vreg401; SGPR_64:%vreg399 SGPR_32:%vreg401
3664B		%vreg399:sub1<def> = COPY %vreg400; SGPR_64:%vreg399 SGPR_32:%vreg400
3680B		%vreg148:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg148 SGPR_64:%vreg147
3696B		%vreg148:sub2_sub3<def> = COPY %vreg399; SReg_128:%vreg148 SGPR_64:%vreg399
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg152<def> = V_MUL_F32_e32 %vreg151<kill>, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg156<def> = V_MUL_F32_e32 %vreg155<kill>, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg160<def> = V_MUL_F32_e32 %vreg159<kill>, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg164<def> = V_MUL_F32_e32 %vreg163<kill>, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg168<def> = V_MUL_F32_e32 %vreg167<kill>, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg172<def> = V_MUL_F32_e32 %vreg171<kill>, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg176<def> = V_MUL_F32_e32 %vreg175<kill>, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148<kill>, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg180<def> = V_MUL_F32_e32 %vreg179<kill>, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
4224B		%vreg183:sub0<def,read-undef> = COPY %vreg182; SGPR_64:%vreg183 SReg_32:%vreg182
4240B		%vreg183:sub1<def> = COPY %vreg181; SGPR_64:%vreg183 SReg_32:%vreg181
4256B		%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
4272B		%vreg561<def> = COPY %vreg560<kill>; VReg_64:%vreg561,%vreg560
4288B		%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
4304B		%vreg562:sub0_sub1<def,read-undef> = COPY %vreg561<kill>; VReg_128:%vreg562 VReg_64:%vreg561
4320B		%vreg562:sub2_sub3<def> = COPY %vreg564<kill>; VReg_128:%vreg562 VReg_64:%vreg564
4336B		%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
4352B		%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
4368B		%vreg678<def> = COPY %vreg677:sub0<kill>; VReg_32:%vreg678 VReg_128:%vreg677
4384B		%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
4400B		%vreg680<def> = COPY %vreg679:sub1<kill>; VReg_32:%vreg680 VReg_128:%vreg679
4416B		%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
4432B		%vreg682<def> = COPY %vreg681:sub0<kill>; VReg_32:%vreg682 VReg_64:%vreg681
4448B		%vreg683<def> = COPY %vreg187<kill>; VReg_64:%vreg683,%vreg187
4464B		%vreg684<def> = COPY %vreg683:sub1<kill>; VReg_32:%vreg684 VReg_64:%vreg683
4480B		%vreg670<def> = V_ADD_I32_e32 %vreg678<kill>, %vreg682<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
4496B		%vreg671<def> = V_ADDC_U32_e32 %vreg680<kill>, %vreg684<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
4512B		%vreg672:sub0<def,read-undef> = COPY %vreg670<kill>; VReg_64:%vreg672 VReg_32:%vreg670
4528B		%vreg672:sub1<def> = COPY %vreg671<kill>; VReg_64:%vreg672 VReg_32:%vreg671
4544B		%vreg676:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg676 SGPR_64:%vreg147
4560B		%vreg676:sub2<def> = COPY %vreg401; SReg_128:%vreg676 SGPR_32:%vreg401
4576B		%vreg676:sub3<def> = COPY %vreg400; SReg_128:%vreg676 SGPR_32:%vreg400
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4608B		%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
4624B		%vreg686<def> = COPY %vreg685<kill>; VReg_64:%vreg686,%vreg685
4640B		%vreg689<def> = COPY %vreg399<kill>; VReg_64:%vreg689 SGPR_64:%vreg399
4656B		%vreg687:sub0_sub1<def,read-undef> = COPY %vreg686<kill>; VReg_128:%vreg687 VReg_64:%vreg686
4672B		%vreg687:sub2_sub3<def> = COPY %vreg689<kill>; VReg_128:%vreg687 VReg_64:%vreg689
4688B		%vreg191<def> = COPY %vreg183<kill>; VReg_64:%vreg191 SGPR_64:%vreg183
4704B		%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
4720B		%vreg803<def> = COPY %vreg802:sub0<kill>; VReg_32:%vreg803 VReg_128:%vreg802
4736B		%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
4752B		%vreg805<def> = COPY %vreg804:sub1<kill>; VReg_32:%vreg805 VReg_128:%vreg804
4768B		%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
4784B		%vreg807<def> = COPY %vreg806:sub0<kill>; VReg_32:%vreg807 VReg_64:%vreg806
4800B		%vreg808<def> = COPY %vreg191<kill>; VReg_64:%vreg808,%vreg191
4816B		%vreg809<def> = COPY %vreg808:sub1<kill>; VReg_32:%vreg809 VReg_64:%vreg808
4832B		%vreg795<def> = V_ADD_I32_e32 %vreg803<kill>, %vreg807<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
4848B		%vreg796<def> = V_ADDC_U32_e32 %vreg805<kill>, %vreg809<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
4864B		%vreg797:sub0<def,read-undef> = COPY %vreg795<kill>; VReg_64:%vreg797 VReg_32:%vreg795
4880B		%vreg797:sub1<def> = COPY %vreg796<kill>; VReg_64:%vreg797 VReg_32:%vreg796
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg193<def> = V_MUL_F32_e32 %vreg192<kill>, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
4944B		%vreg195:sub0<def,read-undef> = COPY %vreg194; SGPR_64:%vreg195 SReg_32:%vreg194
4960B		%vreg195:sub1<def> = COPY %vreg181; SGPR_64:%vreg195 SReg_32:%vreg181
4976B		%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
4992B		%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
5008B		%vreg663<def> = COPY %vreg662:sub0<kill>; VReg_32:%vreg663 VReg_128:%vreg662
5024B		%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
5040B		%vreg665<def> = COPY %vreg664:sub1<kill>; VReg_32:%vreg665 VReg_128:%vreg664
5056B		%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
5072B		%vreg667<def> = COPY %vreg666:sub0<kill>; VReg_32:%vreg667 VReg_64:%vreg666
5088B		%vreg668<def> = COPY %vreg197<kill>; VReg_64:%vreg668,%vreg197
5104B		%vreg669<def> = COPY %vreg668:sub1<kill>; VReg_32:%vreg669 VReg_64:%vreg668
5120B		%vreg655<def> = V_ADD_I32_e32 %vreg663<kill>, %vreg667<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
5136B		%vreg656<def> = V_ADDC_U32_e32 %vreg665<kill>, %vreg669<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
5152B		%vreg657:sub0<def,read-undef> = COPY %vreg655<kill>; VReg_64:%vreg657 VReg_32:%vreg655
5168B		%vreg657:sub1<def> = COPY %vreg656<kill>; VReg_64:%vreg657 VReg_32:%vreg656
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg199<def> = COPY %vreg195<kill>; VReg_64:%vreg199 SGPR_64:%vreg195
5216B		%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
5232B		%vreg788<def> = COPY %vreg787:sub0<kill>; VReg_32:%vreg788 VReg_128:%vreg787
5248B		%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
5264B		%vreg790<def> = COPY %vreg789:sub1<kill>; VReg_32:%vreg790 VReg_128:%vreg789
5280B		%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
5296B		%vreg792<def> = COPY %vreg791:sub0<kill>; VReg_32:%vreg792 VReg_64:%vreg791
5312B		%vreg793<def> = COPY %vreg199<kill>; VReg_64:%vreg793,%vreg199
5328B		%vreg794<def> = COPY %vreg793:sub1<kill>; VReg_32:%vreg794 VReg_64:%vreg793
5344B		%vreg780<def> = V_ADD_I32_e32 %vreg788<kill>, %vreg792<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
5360B		%vreg781<def> = V_ADDC_U32_e32 %vreg790<kill>, %vreg794<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
5376B		%vreg782:sub0<def,read-undef> = COPY %vreg780<kill>; VReg_64:%vreg782 VReg_32:%vreg780
5392B		%vreg782:sub1<def> = COPY %vreg781<kill>; VReg_64:%vreg782 VReg_32:%vreg781
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg201<def> = V_MUL_F32_e32 %vreg200<kill>, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
5456B		%vreg203:sub0<def,read-undef> = COPY %vreg202; SGPR_64:%vreg203 SReg_32:%vreg202
5472B		%vreg203:sub1<def> = COPY %vreg181; SGPR_64:%vreg203 SReg_32:%vreg181
5488B		%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
5504B		%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
5520B		%vreg648<def> = COPY %vreg647:sub0<kill>; VReg_32:%vreg648 VReg_128:%vreg647
5536B		%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
5552B		%vreg650<def> = COPY %vreg649:sub1<kill>; VReg_32:%vreg650 VReg_128:%vreg649
5568B		%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
5584B		%vreg652<def> = COPY %vreg651:sub0<kill>; VReg_32:%vreg652 VReg_64:%vreg651
5600B		%vreg653<def> = COPY %vreg205<kill>; VReg_64:%vreg653,%vreg205
5616B		%vreg654<def> = COPY %vreg653:sub1<kill>; VReg_32:%vreg654 VReg_64:%vreg653
5632B		%vreg640<def> = V_ADD_I32_e32 %vreg648<kill>, %vreg652<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
5648B		%vreg641<def> = V_ADDC_U32_e32 %vreg650<kill>, %vreg654<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
5664B		%vreg642:sub0<def,read-undef> = COPY %vreg640<kill>; VReg_64:%vreg642 VReg_32:%vreg640
5680B		%vreg642:sub1<def> = COPY %vreg641<kill>; VReg_64:%vreg642 VReg_32:%vreg641
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg207<def> = COPY %vreg203<kill>; VReg_64:%vreg207 SGPR_64:%vreg203
5728B		%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
5744B		%vreg773<def> = COPY %vreg772:sub0<kill>; VReg_32:%vreg773 VReg_128:%vreg772
5760B		%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
5776B		%vreg775<def> = COPY %vreg774:sub1<kill>; VReg_32:%vreg775 VReg_128:%vreg774
5792B		%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
5808B		%vreg777<def> = COPY %vreg776:sub0<kill>; VReg_32:%vreg777 VReg_64:%vreg776
5824B		%vreg778<def> = COPY %vreg207<kill>; VReg_64:%vreg778,%vreg207
5840B		%vreg779<def> = COPY %vreg778:sub1<kill>; VReg_32:%vreg779 VReg_64:%vreg778
5856B		%vreg765<def> = V_ADD_I32_e32 %vreg773<kill>, %vreg777<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
5872B		%vreg766<def> = V_ADDC_U32_e32 %vreg775<kill>, %vreg779<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
5888B		%vreg767:sub0<def,read-undef> = COPY %vreg765<kill>; VReg_64:%vreg767 VReg_32:%vreg765
5904B		%vreg767:sub1<def> = COPY %vreg766<kill>; VReg_64:%vreg767 VReg_32:%vreg766
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg209<def> = V_MUL_F32_e32 %vreg208<kill>, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
5968B		%vreg211:sub0<def,read-undef> = COPY %vreg210; SGPR_64:%vreg211 SReg_32:%vreg210
5984B		%vreg211:sub1<def> = COPY %vreg181; SGPR_64:%vreg211 SReg_32:%vreg181
6000B		%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
6016B		%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
6032B		%vreg633<def> = COPY %vreg632:sub0<kill>; VReg_32:%vreg633 VReg_128:%vreg632
6048B		%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
6064B		%vreg635<def> = COPY %vreg634:sub1<kill>; VReg_32:%vreg635 VReg_128:%vreg634
6080B		%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
6096B		%vreg637<def> = COPY %vreg636:sub0<kill>; VReg_32:%vreg637 VReg_64:%vreg636
6112B		%vreg638<def> = COPY %vreg213<kill>; VReg_64:%vreg638,%vreg213
6128B		%vreg639<def> = COPY %vreg638:sub1<kill>; VReg_32:%vreg639 VReg_64:%vreg638
6144B		%vreg625<def> = V_ADD_I32_e32 %vreg633<kill>, %vreg637<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
6160B		%vreg626<def> = V_ADDC_U32_e32 %vreg635<kill>, %vreg639<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
6176B		%vreg627:sub0<def,read-undef> = COPY %vreg625<kill>; VReg_64:%vreg627 VReg_32:%vreg625
6192B		%vreg627:sub1<def> = COPY %vreg626<kill>; VReg_64:%vreg627 VReg_32:%vreg626
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg215<def> = COPY %vreg211<kill>; VReg_64:%vreg215 SGPR_64:%vreg211
6240B		%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
6256B		%vreg758<def> = COPY %vreg757:sub0<kill>; VReg_32:%vreg758 VReg_128:%vreg757
6272B		%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
6288B		%vreg760<def> = COPY %vreg759:sub1<kill>; VReg_32:%vreg760 VReg_128:%vreg759
6304B		%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
6320B		%vreg762<def> = COPY %vreg761:sub0<kill>; VReg_32:%vreg762 VReg_64:%vreg761
6336B		%vreg763<def> = COPY %vreg215<kill>; VReg_64:%vreg763,%vreg215
6352B		%vreg764<def> = COPY %vreg763:sub1<kill>; VReg_32:%vreg764 VReg_64:%vreg763
6368B		%vreg750<def> = V_ADD_I32_e32 %vreg758<kill>, %vreg762<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
6384B		%vreg751<def> = V_ADDC_U32_e32 %vreg760<kill>, %vreg764<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
6400B		%vreg752:sub0<def,read-undef> = COPY %vreg750<kill>; VReg_64:%vreg752 VReg_32:%vreg750
6416B		%vreg752:sub1<def> = COPY %vreg751<kill>; VReg_64:%vreg752 VReg_32:%vreg751
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg217<def> = V_MUL_F32_e32 %vreg216<kill>, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
6480B		%vreg219:sub0<def,read-undef> = COPY %vreg218; SGPR_64:%vreg219 SReg_32:%vreg218
6496B		%vreg219:sub1<def> = COPY %vreg181; SGPR_64:%vreg219 SReg_32:%vreg181
6512B		%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
6528B		%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
6544B		%vreg618<def> = COPY %vreg617:sub0<kill>; VReg_32:%vreg618 VReg_128:%vreg617
6560B		%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
6576B		%vreg620<def> = COPY %vreg619:sub1<kill>; VReg_32:%vreg620 VReg_128:%vreg619
6592B		%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
6608B		%vreg622<def> = COPY %vreg621:sub0<kill>; VReg_32:%vreg622 VReg_64:%vreg621
6624B		%vreg623<def> = COPY %vreg221<kill>; VReg_64:%vreg623,%vreg221
6640B		%vreg624<def> = COPY %vreg623:sub1<kill>; VReg_32:%vreg624 VReg_64:%vreg623
6656B		%vreg610<def> = V_ADD_I32_e32 %vreg618<kill>, %vreg622<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
6672B		%vreg611<def> = V_ADDC_U32_e32 %vreg620<kill>, %vreg624<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
6688B		%vreg612:sub0<def,read-undef> = COPY %vreg610<kill>; VReg_64:%vreg612 VReg_32:%vreg610
6704B		%vreg612:sub1<def> = COPY %vreg611<kill>; VReg_64:%vreg612 VReg_32:%vreg611
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg223<def> = COPY %vreg219<kill>; VReg_64:%vreg223 SGPR_64:%vreg219
6752B		%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
6768B		%vreg743<def> = COPY %vreg742:sub0<kill>; VReg_32:%vreg743 VReg_128:%vreg742
6784B		%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
6800B		%vreg745<def> = COPY %vreg744:sub1<kill>; VReg_32:%vreg745 VReg_128:%vreg744
6816B		%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
6832B		%vreg747<def> = COPY %vreg746:sub0<kill>; VReg_32:%vreg747 VReg_64:%vreg746
6848B		%vreg748<def> = COPY %vreg223<kill>; VReg_64:%vreg748,%vreg223
6864B		%vreg749<def> = COPY %vreg748:sub1<kill>; VReg_32:%vreg749 VReg_64:%vreg748
6880B		%vreg735<def> = V_ADD_I32_e32 %vreg743<kill>, %vreg747<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
6896B		%vreg736<def> = V_ADDC_U32_e32 %vreg745<kill>, %vreg749<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
6912B		%vreg737:sub0<def,read-undef> = COPY %vreg735<kill>; VReg_64:%vreg737 VReg_32:%vreg735
6928B		%vreg737:sub1<def> = COPY %vreg736<kill>; VReg_64:%vreg737 VReg_32:%vreg736
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg225<def> = V_MUL_F32_e32 %vreg224<kill>, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
6992B		%vreg227:sub0<def,read-undef> = COPY %vreg226; SGPR_64:%vreg227 SReg_32:%vreg226
7008B		%vreg227:sub1<def> = COPY %vreg181; SGPR_64:%vreg227 SReg_32:%vreg181
7024B		%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
7040B		%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
7056B		%vreg603<def> = COPY %vreg602:sub0<kill>; VReg_32:%vreg603 VReg_128:%vreg602
7072B		%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
7088B		%vreg605<def> = COPY %vreg604:sub1<kill>; VReg_32:%vreg605 VReg_128:%vreg604
7104B		%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
7120B		%vreg607<def> = COPY %vreg606:sub0<kill>; VReg_32:%vreg607 VReg_64:%vreg606
7136B		%vreg608<def> = COPY %vreg229<kill>; VReg_64:%vreg608,%vreg229
7152B		%vreg609<def> = COPY %vreg608:sub1<kill>; VReg_32:%vreg609 VReg_64:%vreg608
7168B		%vreg595<def> = V_ADD_I32_e32 %vreg603<kill>, %vreg607<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
7184B		%vreg596<def> = V_ADDC_U32_e32 %vreg605<kill>, %vreg609<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
7200B		%vreg597:sub0<def,read-undef> = COPY %vreg595<kill>; VReg_64:%vreg597 VReg_32:%vreg595
7216B		%vreg597:sub1<def> = COPY %vreg596<kill>; VReg_64:%vreg597 VReg_32:%vreg596
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg231<def> = COPY %vreg227<kill>; VReg_64:%vreg231 SGPR_64:%vreg227
7264B		%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
7280B		%vreg728<def> = COPY %vreg727:sub0<kill>; VReg_32:%vreg728 VReg_128:%vreg727
7296B		%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
7312B		%vreg730<def> = COPY %vreg729:sub1<kill>; VReg_32:%vreg730 VReg_128:%vreg729
7328B		%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
7344B		%vreg732<def> = COPY %vreg731:sub0<kill>; VReg_32:%vreg732 VReg_64:%vreg731
7360B		%vreg733<def> = COPY %vreg231<kill>; VReg_64:%vreg733,%vreg231
7376B		%vreg734<def> = COPY %vreg733:sub1<kill>; VReg_32:%vreg734 VReg_64:%vreg733
7392B		%vreg720<def> = V_ADD_I32_e32 %vreg728<kill>, %vreg732<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
7408B		%vreg721<def> = V_ADDC_U32_e32 %vreg730<kill>, %vreg734<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
7424B		%vreg722:sub0<def,read-undef> = COPY %vreg720<kill>; VReg_64:%vreg722 VReg_32:%vreg720
7440B		%vreg722:sub1<def> = COPY %vreg721<kill>; VReg_64:%vreg722 VReg_32:%vreg721
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg233<def> = V_MUL_F32_e32 %vreg232<kill>, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
7504B		%vreg235:sub0<def,read-undef> = COPY %vreg234; SGPR_64:%vreg235 SReg_32:%vreg234
7520B		%vreg235:sub1<def> = COPY %vreg181; SGPR_64:%vreg235 SReg_32:%vreg181
7536B		%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
7552B		%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
7568B		%vreg588<def> = COPY %vreg587:sub0<kill>; VReg_32:%vreg588 VReg_128:%vreg587
7584B		%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
7600B		%vreg590<def> = COPY %vreg589:sub1<kill>; VReg_32:%vreg590 VReg_128:%vreg589
7616B		%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
7632B		%vreg592<def> = COPY %vreg591:sub0<kill>; VReg_32:%vreg592 VReg_64:%vreg591
7648B		%vreg593<def> = COPY %vreg237<kill>; VReg_64:%vreg593,%vreg237
7664B		%vreg594<def> = COPY %vreg593:sub1<kill>; VReg_32:%vreg594 VReg_64:%vreg593
7680B		%vreg580<def> = V_ADD_I32_e32 %vreg588<kill>, %vreg592<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
7696B		%vreg581<def> = V_ADDC_U32_e32 %vreg590<kill>, %vreg594<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
7712B		%vreg582:sub0<def,read-undef> = COPY %vreg580<kill>; VReg_64:%vreg582 VReg_32:%vreg580
7728B		%vreg582:sub1<def> = COPY %vreg581<kill>; VReg_64:%vreg582 VReg_32:%vreg581
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg239<def> = COPY %vreg235<kill>; VReg_64:%vreg239 SGPR_64:%vreg235
7776B		%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
7792B		%vreg713<def> = COPY %vreg712:sub0<kill>; VReg_32:%vreg713 VReg_128:%vreg712
7808B		%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
7824B		%vreg715<def> = COPY %vreg714:sub1<kill>; VReg_32:%vreg715 VReg_128:%vreg714
7840B		%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
7856B		%vreg717<def> = COPY %vreg716:sub0<kill>; VReg_32:%vreg717 VReg_64:%vreg716
7872B		%vreg718<def> = COPY %vreg239<kill>; VReg_64:%vreg718,%vreg239
7888B		%vreg719<def> = COPY %vreg718:sub1<kill>; VReg_32:%vreg719 VReg_64:%vreg718
7904B		%vreg705<def> = V_ADD_I32_e32 %vreg713<kill>, %vreg717<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
7920B		%vreg706<def> = V_ADDC_U32_e32 %vreg715<kill>, %vreg719<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
7936B		%vreg707:sub0<def,read-undef> = COPY %vreg705<kill>; VReg_64:%vreg707 VReg_32:%vreg705
7952B		%vreg707:sub1<def> = COPY %vreg706<kill>; VReg_64:%vreg707 VReg_32:%vreg706
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg241<def> = V_MUL_F32_e32 %vreg240<kill>, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
8016B		%vreg243:sub0<def,read-undef> = COPY %vreg242; SGPR_64:%vreg243 SReg_32:%vreg242
8032B		%vreg243:sub1<def> = COPY %vreg181; SGPR_64:%vreg243 SReg_32:%vreg181
8048B		%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
8064B		%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
8080B		%vreg573<def> = COPY %vreg572:sub0<kill>; VReg_32:%vreg573 VReg_128:%vreg572
8096B		%vreg574<def> = COPY %vreg562<kill>; VReg_128:%vreg574,%vreg562
8112B		%vreg575<def> = COPY %vreg574:sub1<kill>; VReg_32:%vreg575 VReg_128:%vreg574
8128B		%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
8144B		%vreg577<def> = COPY %vreg576:sub0<kill>; VReg_32:%vreg577 VReg_64:%vreg576
8160B		%vreg578<def> = COPY %vreg245<kill>; VReg_64:%vreg578,%vreg245
8176B		%vreg579<def> = COPY %vreg578:sub1<kill>; VReg_32:%vreg579 VReg_64:%vreg578
8192B		%vreg565<def> = V_ADD_I32_e32 %vreg573<kill>, %vreg577<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
8208B		%vreg566<def> = V_ADDC_U32_e32 %vreg575<kill>, %vreg579<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
8224B		%vreg567:sub0<def,read-undef> = COPY %vreg565<kill>; VReg_64:%vreg567 VReg_32:%vreg565
8240B		%vreg567:sub1<def> = COPY %vreg566<kill>; VReg_64:%vreg567 VReg_32:%vreg566
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg247<def> = COPY %vreg243<kill>; VReg_64:%vreg247 SGPR_64:%vreg243
8288B		%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
8304B		%vreg698<def> = COPY %vreg697:sub0<kill>; VReg_32:%vreg698 VReg_128:%vreg697
8320B		%vreg699<def> = COPY %vreg687<kill>; VReg_128:%vreg699,%vreg687
8336B		%vreg700<def> = COPY %vreg699:sub1<kill>; VReg_32:%vreg700 VReg_128:%vreg699
8352B		%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
8368B		%vreg702<def> = COPY %vreg701:sub0<kill>; VReg_32:%vreg702 VReg_64:%vreg701
8384B		%vreg703<def> = COPY %vreg247<kill>; VReg_64:%vreg703,%vreg247
8400B		%vreg704<def> = COPY %vreg703:sub1<kill>; VReg_32:%vreg704 VReg_64:%vreg703
8416B		%vreg690<def> = V_ADD_I32_e32 %vreg698<kill>, %vreg702<kill>, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
8432B		%vreg691<def> = V_ADDC_U32_e32 %vreg700<kill>, %vreg704<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
8448B		%vreg692:sub0<def,read-undef> = COPY %vreg690<kill>; VReg_64:%vreg692 VReg_32:%vreg690
8464B		%vreg692:sub1<def> = COPY %vreg691<kill>; VReg_64:%vreg692 VReg_32:%vreg691
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676<kill>, %vreg692<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg249<def> = V_MUL_F32_e32 %vreg248<kill>, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
8528B		%vreg250:sub0<def,read-undef> = COPY %vreg249<kill>; VReg_512:%vreg250 VGPR_32:%vreg249
8544B		%vreg250:sub1<def> = COPY %vreg241<kill>; VReg_512:%vreg250 VGPR_32:%vreg241
8560B		%vreg250:sub2<def> = COPY %vreg233<kill>; VReg_512:%vreg250 VGPR_32:%vreg233
8576B		%vreg250:sub3<def> = COPY %vreg225<kill>; VReg_512:%vreg250 VGPR_32:%vreg225
8592B		%vreg250:sub4<def> = COPY %vreg217<kill>; VReg_512:%vreg250 VGPR_32:%vreg217
8608B		%vreg250:sub5<def> = COPY %vreg209<kill>; VReg_512:%vreg250 VGPR_32:%vreg209
8624B		%vreg250:sub6<def> = COPY %vreg201<kill>; VReg_512:%vreg250 VGPR_32:%vreg201
8640B		%vreg250:sub7<def> = COPY %vreg193<kill>; VReg_512:%vreg250 VGPR_32:%vreg193
8656B		%vreg250:sub8<def> = COPY %vreg180<kill>; VReg_512:%vreg250 VGPR_32:%vreg180
8672B		%vreg250:sub9<def> = COPY %vreg176<kill>; VReg_512:%vreg250 VGPR_32:%vreg176
8688B		%vreg250:sub10<def> = COPY %vreg172<kill>; VReg_512:%vreg250 VGPR_32:%vreg172
8704B		%vreg250:sub11<def> = COPY %vreg168<kill>; VReg_512:%vreg250 VGPR_32:%vreg168
8720B		%vreg250:sub12<def> = COPY %vreg164<kill>; VReg_512:%vreg250 VGPR_32:%vreg164
8736B		%vreg250:sub13<def> = COPY %vreg160<kill>; VReg_512:%vreg250 VGPR_32:%vreg160
8752B		%vreg250:sub14<def> = COPY %vreg156<kill>; VReg_512:%vreg250 VGPR_32:%vreg156
8768B		%vreg250:sub15<def> = COPY %vreg152<kill>; VReg_512:%vreg250 VGPR_32:%vreg152
8784B		%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
8800B		%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg252<kill>, %vreg251<kill>, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
8832B		%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg254<kill>, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
8864B		%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg256<kill>, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
8896B		%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg258<kill>, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
8928B		%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg260<kill>, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
8960B		%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg262<kill>, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
8992B		%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg264<kill>, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
9024B		%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg266<kill>, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
9056B		%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg268<kill>, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
9088B		%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg270<kill>, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
9120B		%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg272<kill>, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
9152B		%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg274<kill>, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
9184B		%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg276<kill>, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
9216B		%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg278<kill>, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
9248B		%vreg280<def> = COPY %vreg250:sub15<kill>; VSrc_32:%vreg280 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg280<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
9280B		%vreg282<def> = V_ADD_F32_e32 %vreg26<kill>, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
9296B		%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
9312B		%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
9328B		%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
9344B		%vreg816<def> = COPY %vreg23:sub1<kill>; VReg_32:%vreg816 VReg_64:%vreg23
9360B		%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
9376B		%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
9392B		%vreg817<def> = V_ADDC_U32_e32 %vreg816<kill>, %vreg818<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg817,%vreg816,%vreg818
9408B		%vreg812:sub0<def,read-undef> = COPY %vreg811<kill>; VReg_64:%vreg812 VReg_32:%vreg811
9424B		%vreg812:sub1<def> = COPY %vreg817<kill>; VReg_64:%vreg812 VReg_32:%vreg817
9440B		%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
9456B		%vreg825<def> = COPY %vreg24:sub1<kill>; VReg_32:%vreg825 VReg_64:%vreg24
9472B		%vreg820<def> = V_ADD_I32_e32 %vreg284<kill>, %vreg819<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
9488B		%vreg827<def> = COPY %vreg286<kill>; VReg_32:%vreg827 SReg_32:%vreg286
9504B		%vreg826<def> = V_ADDC_U32_e32 %vreg825<kill>, %vreg827<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg826,%vreg825,%vreg827
9520B		%vreg821:sub0<def,read-undef> = COPY %vreg820<kill>; VReg_64:%vreg821 VReg_32:%vreg820
9536B		%vreg821:sub1<def> = COPY %vreg826<kill>; VReg_64:%vreg821 VReg_32:%vreg826
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg545<def> = V_ADD_I32_e32 16, %vreg542<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg545,%vreg542
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
9600B		%vreg298<def> = SI_IF_BREAK %vreg297<kill>, %vreg22<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
9616B		%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
9632B		%vreg815<def> = COPY %vreg812<kill>; VReg_64:%vreg815,%vreg812
9648B		%vreg824<def> = COPY %vreg821<kill>; VReg_64:%vreg824,%vreg821
9664B		%vreg27<def> = COPY %vreg282<kill>; VGPR_32:%vreg27,%vreg282
9680B		%vreg544<def> = COPY %vreg545<kill>; VReg_32:%vreg544,%vreg545
9696B		%vreg851<def> = COPY %vreg31; SReg_64:%vreg851,%vreg31
9712B		%vreg852<def> = COPY %vreg815<kill>; VReg_64:%vreg852,%vreg815
9728B		%vreg853<def> = COPY %vreg824<kill>; VReg_64:%vreg853,%vreg824
9744B		%vreg854<def> = COPY %vreg544<kill>; VReg_32:%vreg854,%vreg544
9760B		%vreg855<def> = COPY %vreg27; VGPR_32:%vreg855,%vreg27
9776B		SI_LOOP %vreg298<kill>, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9824B		%vreg32<def> = COPY %vreg856<kill>; VGPR_32:%vreg32,%vreg856
9840B		SI_END_CF %vreg302<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
9888B		%vreg37<def> = COPY %vreg861<kill>; VGPR_32:%vreg37,%vreg861
9904B		%vreg455<def> = COPY %vreg860<kill>; VReg_32:%vreg455,%vreg860
9920B		%vreg35<def> = COPY %vreg859<kill>; VReg_64:%vreg35,%vreg859
9936B		%vreg34<def> = COPY %vreg858<kill>; VReg_64:%vreg34,%vreg858
9952B		%vreg33<def> = COPY %vreg857<kill>; SReg_64:%vreg33,%vreg857
9968B		%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
9984B		%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
10000B		%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
10016B		%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
10032B		%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
10048B		%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
10064B		%vreg835<def> = V_ADDC_U32_e32 %vreg834<kill>, %vreg836<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg835,%vreg834,%vreg836
10080B		%vreg830:sub0<def,read-undef> = COPY %vreg829<kill>; VReg_64:%vreg830 VReg_32:%vreg829
10096B		%vreg830:sub1<def> = COPY %vreg835<kill>; VReg_64:%vreg830 VReg_32:%vreg835
10112B		%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
10128B		%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
10144B		%vreg838<def> = V_ADD_I32_e32 %vreg354<kill>, %vreg837<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
10160B		%vreg845<def> = COPY %vreg356<kill>; VReg_32:%vreg845 SReg_32:%vreg356
10176B		%vreg844<def> = V_ADDC_U32_e32 %vreg843<kill>, %vreg845<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg844,%vreg843,%vreg845
10192B		%vreg839:sub0<def,read-undef> = COPY %vreg838<kill>; VReg_64:%vreg839 VReg_32:%vreg838
10208B		%vreg839:sub1<def> = COPY %vreg844<kill>; VReg_64:%vreg839 VReg_32:%vreg844
10224B		%vreg411:sub0<def,read-undef> = COPY %vreg413; SGPR_64:%vreg411 SGPR_32:%vreg413
10240B		%vreg411:sub1<def> = COPY %vreg412; SGPR_64:%vreg411 SGPR_32:%vreg412
10256B		%vreg366:sub0_sub1<def,read-undef> = COPY %vreg352; SReg_128:%vreg366 SGPR_64:%vreg352
10272B		%vreg366:sub2_sub3<def> = COPY %vreg411<kill>; SReg_128:%vreg366 SGPR_64:%vreg411
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366<kill>, %vreg34<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg370<def> = V_MAD_F32 %vreg369<kill>, %vreg369, %vreg37<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
10352B		%vreg458<def> = V_ADD_I32_e32 -1, %vreg455<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg458,%vreg455
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
10384B		%vreg372<def> = SI_IF_BREAK %vreg371<kill>, %vreg33<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
10400B		%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
10416B		%vreg833<def> = COPY %vreg830<kill>; VReg_64:%vreg833,%vreg830
10432B		%vreg842<def> = COPY %vreg839<kill>; VReg_64:%vreg842,%vreg839
10448B		%vreg38<def> = COPY %vreg370<kill>; VGPR_32:%vreg38,%vreg370
10464B		%vreg457<def> = COPY %vreg458<kill>; VReg_32:%vreg457,%vreg458
10480B		%vreg857<def> = COPY %vreg42; SReg_64:%vreg857,%vreg42
10496B		%vreg858<def> = COPY %vreg833<kill>; VReg_64:%vreg858,%vreg833
10512B		%vreg859<def> = COPY %vreg842<kill>; VReg_64:%vreg859,%vreg842
10528B		%vreg860<def> = COPY %vreg457<kill>; VReg_32:%vreg860,%vreg457
10544B		%vreg861<def> = COPY %vreg38; VGPR_32:%vreg861,%vreg38
10560B		SI_LOOP %vreg372<kill>, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg42<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg42
10624B		%vreg856<def> = COPY %vreg38<kill>; VGPR_32:%vreg856,%vreg38
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54<kill>; VGPR_32:%vreg373 SReg_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440<kill>, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg424<def> = V_ADD_I32_e32 %vreg374<kill>, %vreg423<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg424,%vreg374,%vreg423
10720B		%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
10736B		%vreg425:sub0<def,read-undef> = COPY %vreg424<kill>; VReg_64:%vreg425 VReg_32:%vreg424
10752B		%vreg425:sub1<def> = COPY %vreg437<kill>; VReg_64:%vreg425 VReg_32:%vreg437
10768B		%vreg428<def> = V_LSHL_B64 %vreg425<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10784B		%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
10800B		%vreg429<def> = COPY %vreg428:sub1<kill>; VReg_32:%vreg429 VReg_64:%vreg428
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1<kill>; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
10848B		%vreg436<def> = V_ADD_I32_e32 %vreg847<kill>, %vreg435<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
10864B		%vreg430<def> = V_ADDC_U32_e32 %vreg848<kill>, %vreg429<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg430,%vreg848,%vreg429
10880B		%vreg432:sub0<def,read-undef> = COPY %vreg436<kill>; VReg_64:%vreg432 VReg_32:%vreg436
10896B		%vreg432:sub1<def> = COPY %vreg430<kill>; VReg_64:%vreg432 VReg_32:%vreg430
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg32<kill>, %vreg56<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg32,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
10992B		%vreg45<def> = COPY %vreg432<kill>; VReg_64:%vreg45,%vreg432
11008B		%vreg393<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11056B		%vreg395<def> = COPY %vreg393<kill>; SReg_64:%vreg395,%vreg393
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
11136B		%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
11152B		%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
11168B		%vreg415:sub0<def,read-undef> = COPY %vreg417<kill>; SGPR_64:%vreg415 SGPR_32:%vreg417
11184B		%vreg415:sub1<def> = COPY %vreg416<kill>; SGPR_64:%vreg415 SGPR_32:%vreg416
11200B		%vreg396:sub0_sub1<def,read-undef> = COPY %vreg414<kill>; SReg_128:%vreg396 SGPR_64:%vreg414
11216B		%vreg396:sub2_sub3<def> = COPY %vreg415<kill>; SReg_128:%vreg396 SGPR_64:%vreg415
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11296B		%vreg44<def> = COPY %vreg388<kill>; VGPR_32:%vreg44,%vreg388
11312B		%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
11328B		%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
11344B		%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
11360B		%vreg419:sub0<def,read-undef> = COPY %vreg421<kill>; SGPR_64:%vreg419 SGPR_32:%vreg421
11376B		%vreg419:sub1<def> = COPY %vreg420<kill>; SGPR_64:%vreg419 SGPR_32:%vreg420
11392B		%vreg394:sub0_sub1<def,read-undef> = COPY %vreg418<kill>; SReg_128:%vreg394 SGPR_64:%vreg418
11408B		%vreg394:sub2_sub3<def> = COPY %vreg419<kill>; SReg_128:%vreg394 SGPR_64:%vreg419
11424B		BUFFER_STORE_DWORD %vreg44<kill>, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

Computing live-in reg-units in ABI blocks.
0B	BB#0 SGPR0#0 SGPR1#0 VGPR1#0 SGPR3#0 VGPR0#0 SGPR2#0
Created 6 new intervals.
********** INTERVALS **********
SGPR0 [0B,80r:0)  0@0B-phi
SGPR1 [0B,80r:0)  0@0B-phi
SGPR2 [0B,16r:0)  0@0B-phi
SGPR3 [0B,48r:0)  0@0B-phi
VGPR0 [0B,32r:0)  0@0B-phi
VGPR1 [0B,64r:0)  0@0B-phi
%vreg0 [560r,2224B:0)[2272B,2816r:0)[3408B,9808B:0)  0@560r
%vreg1 [592r,2224B:0)[2272B,2832r:0)[3408B,9808B:0)  0@592r
%vreg4 [528r,2224B:0)[2272B,2384r:0)[3408B,9808B:0)  0@528r
%vreg5 [576r,2224B:0)[2272B,2400r:0)[3408B,9808B:0)  0@576r
%vreg9 [688r,2096B:0)[3552B,9808B:0)  0@688r
%vreg11 [1776r,2032r:0)  0@1776r
%vreg12 [1760r,2016r:0)  0@1760r
%vreg13 [2144r,2160r:0)  0@2144r
%vreg18 [3232r,3344r:0)  0@3232r
%vreg19 [3216r,3328r:0)  0@3216r
%vreg20 [2272B,3376r:0)[3440r,3552B:0)  0@3440r
%vreg22 [3632r,9600r:0)  0@3632r
%vreg23 [3616r,9344r:0)  0@3616r
%vreg24 [3600r,9456r:0)  0@3600r
%vreg26 [3568r,9280r:0)  0@3568r
%vreg27 [2096B,2176r:0)[9664r,9808B:0)  0@9664r
%vreg31 [2096B,2112r:0)[9616r,9808B:0)  0@9616r
%vreg32 [9824r,9872B:0)[10656B,10912r:0)  0@9824r
%vreg33 [9952r,10384r:0)  0@9952r
%vreg34 [9936r,10304r:0)  0@9936r
%vreg35 [9920r,10288r:0)  0@9920r
%vreg37 [9888r,10336r:0)  0@9888r
%vreg38 [10448r,10624r:0)  0@10448r
%vreg42 [10400r,10608r:0)  0@10400r
%vreg44 [11296r,11424r:0)  0@11296r
%vreg45 [10992r,11248r:0)[11280B,11456B:0)  0@10992r
%vreg48 [80r,448r:0)  0@80r
%vreg49 [672r,2224B:0)[2272B,2736r:0)[3408B,9808B:0)  0@672r
%vreg50 [656r,2224B:0)[2272B,2432r:0)[3408B,9808B:0)  0@656r
%vreg51 [640r,2224B:0)[2272B,3088r:0)[3408B,9808B:0)  0@640r
%vreg52 [624r,2224B:0)[2272B,2864r:0)[3408B,9808B:0)  0@624r
%vreg53 [2272B,3408B:0)[3488r,3552B:0)[9808B,10832r:0)  0@3488r
%vreg54 [2272B,3408B:0)[3472r,3552B:0)[9808B,10672r:0)  0@3472r
%vreg55 [608r,2224B:0)[2272B,3168r:0)[3408B,9808B:0)  0@608r
%vreg56 [2272B,3408B:0)[3456r,3552B:0)[9808B,10912r:0)  0@3456r
%vreg57 [64r,512r:0)  0@64r
%vreg58 [48r,528r:0)  0@48r
%vreg59 [32r,544r:0)  0@32r
%vreg60 [16r,560r:0)  0@16r
%vreg61 [96r,128r:0)  0@96r
%vreg62 [112r,592r:0)  0@112r
%vreg63 [128r,144r:0)  0@128r
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%vreg67 [176r,192r:0)  0@176r
%vreg68 [192r,320r:0)  0@192r
%vreg69 [208r,240r:0)  0@208r
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%vreg74 [272r,288r:0)  0@272r
%vreg75 [288r,304r:0)  0@288r
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%vreg77 [320r,464r:0)  0@320r
%vreg78 [336r,2224B:0)[3408B,3456r:0)[3552B,9808B:0)  0@336r
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%vreg81 [384r,2224B:0)[3408B,3488r:0)[3552B,9808B:0)  0@384r
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%vreg86 [464r,2240r:0)[2272B,11504B:0)  0@464r
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%vreg89 [704r,832r:0)  0@704r
%vreg90 [720r,736r:0)  0@720r
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%vreg92 [832r,2224B:0)[3408B,3504r:0)[3552B,9808B:0)  0@832r
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%vreg95 [1680r,2064r:0)  0@1680r
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%vreg104 [960r,976r:1)[976r,992r:0)  0@976r 1@960r
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%vreg117 [1184r,1584r:0)  0@1184r
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%vreg148 [3680r,3696r:1)[3696r,4176r:0)  0@3696r 1@3680r
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%vreg150 [3728r,3744r:0)  0@3728r
%vreg151 [3744r,3760r:0)  0@3744r
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%vreg153 [3776r,3808r:0)  0@3776r
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%vreg158 [3856r,3872r:0)  0@3856r
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%vreg160 [3888r,8736r:0)  0@3888r
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%vreg163 [3936r,3952r:0)  0@3936r
%vreg164 [3952r,8720r:0)  0@3952r
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%vreg167 [4000r,4016r:0)  0@4000r
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%vreg170 [4048r,4064r:0)  0@4048r
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%vreg172 [4080r,8688r:0)  0@4080r
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%vreg176 [4144r,8672r:0)  0@4144r
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%vreg183 [4224r,4240r:1)[4240r,4688r:0)  0@4240r 1@4224r
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%vreg207 [5712r,5824r:0)  0@5712r
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%vreg522 [1408r,1440r:0)  0@1408r
%vreg523 [1440r,1504r:0)  0@1440r
%vreg524 [1504r,1536r:0)  0@1504r
%vreg526 [1520r,1536r:1)[1536r,1568r:0)  0@1536r 1@1520r
%vreg529 [1568r,1616r:0)  0@1568r
%vreg530 [1616r,1648r:0)  0@1616r
%vreg531 [1600r,1616r:0)  0@1600r
%vreg532 [1632r,1648r:1)[1648r,1776r:0)  0@1648r 1@1632r
%vreg535 [1552r,1584r:0)  0@1552r
%vreg536 [1584r,1632r:0)  0@1584r
%vreg537 [1424r,1488r:0)  0@1424r
%vreg538 [1488r,1520r:0)  0@1488r
%vreg539 [1456r,1488r:0)  0@1456r
%vreg540 [1472r,1504r:0)  0@1472r
%vreg541 [1712r,1984r:0)  0@1712r
%vreg542 [3584r,9568r:0)  0@3584r
%vreg543 [1984r,2048r:0)  0@1984r
%vreg544 [9680r,9744r:0)  0@9680r
%vreg545 [9568r,9680r:0)  0@9568r
%vreg548 [2448r,2480r:0)  0@2448r
%vreg549 [2496r,2608r:0)  0@2496r
%vreg550 [2512r,2624r:0)  0@2512r
%vreg551 [2720r,2752r:0)  0@2720r
%vreg552 [2736r,2768r:0)  0@2736r
%vreg555 [2880r,2912r:0)  0@2880r
%vreg556 [2928r,2960r:0)  0@2928r
%vreg557 [2944r,2976r:0)  0@2944r
%vreg558 [3072r,3104r:0)  0@3072r
%vreg559 [3088r,3120r:0)  0@3088r
%vreg560 [4256r,4272r:0)  0@4256r
%vreg561 [4272r,4304r:0)  0@4272r
%vreg562 [4304r,4320r:1)[4320r,8096r:0)  0@4320r 1@4304r
%vreg564 [4288r,4320r:0)  0@4288r
%vreg565 [8192r,8224r:0)  0@8192r
%vreg566 [8208r,8240r:0)  0@8208r
%vreg567 [8224r,8240r:1)[8240r,8256r:0)  0@8240r 1@8224r
%vreg572 [8064r,8080r:0)  0@8064r
%vreg573 [8080r,8192r:0)  0@8080r
%vreg574 [8096r,8112r:0)  0@8096r
%vreg575 [8112r,8208r:0)  0@8112r
%vreg576 [8128r,8144r:0)  0@8128r
%vreg577 [8144r,8192r:0)  0@8144r
%vreg578 [8160r,8176r:0)  0@8160r
%vreg579 [8176r,8208r:0)  0@8176r
%vreg580 [7680r,7712r:0)  0@7680r
%vreg581 [7696r,7728r:0)  0@7696r
%vreg582 [7712r,7728r:1)[7728r,7744r:0)  0@7728r 1@7712r
%vreg587 [7552r,7568r:0)  0@7552r
%vreg588 [7568r,7680r:0)  0@7568r
%vreg589 [7584r,7600r:0)  0@7584r
%vreg590 [7600r,7696r:0)  0@7600r
%vreg591 [7616r,7632r:0)  0@7616r
%vreg592 [7632r,7680r:0)  0@7632r
%vreg593 [7648r,7664r:0)  0@7648r
%vreg594 [7664r,7696r:0)  0@7664r
%vreg595 [7168r,7200r:0)  0@7168r
%vreg596 [7184r,7216r:0)  0@7184r
%vreg597 [7200r,7216r:1)[7216r,7232r:0)  0@7216r 1@7200r
%vreg602 [7040r,7056r:0)  0@7040r
%vreg603 [7056r,7168r:0)  0@7056r
%vreg604 [7072r,7088r:0)  0@7072r
%vreg605 [7088r,7184r:0)  0@7088r
%vreg606 [7104r,7120r:0)  0@7104r
%vreg607 [7120r,7168r:0)  0@7120r
%vreg608 [7136r,7152r:0)  0@7136r
%vreg609 [7152r,7184r:0)  0@7152r
%vreg610 [6656r,6688r:0)  0@6656r
%vreg611 [6672r,6704r:0)  0@6672r
%vreg612 [6688r,6704r:1)[6704r,6720r:0)  0@6704r 1@6688r
%vreg617 [6528r,6544r:0)  0@6528r
%vreg618 [6544r,6656r:0)  0@6544r
%vreg619 [6560r,6576r:0)  0@6560r
%vreg620 [6576r,6672r:0)  0@6576r
%vreg621 [6592r,6608r:0)  0@6592r
%vreg622 [6608r,6656r:0)  0@6608r
%vreg623 [6624r,6640r:0)  0@6624r
%vreg624 [6640r,6672r:0)  0@6640r
%vreg625 [6144r,6176r:0)  0@6144r
%vreg626 [6160r,6192r:0)  0@6160r
%vreg627 [6176r,6192r:1)[6192r,6208r:0)  0@6192r 1@6176r
%vreg632 [6016r,6032r:0)  0@6016r
%vreg633 [6032r,6144r:0)  0@6032r
%vreg634 [6048r,6064r:0)  0@6048r
%vreg635 [6064r,6160r:0)  0@6064r
%vreg636 [6080r,6096r:0)  0@6080r
%vreg637 [6096r,6144r:0)  0@6096r
%vreg638 [6112r,6128r:0)  0@6112r
%vreg639 [6128r,6160r:0)  0@6128r
%vreg640 [5632r,5664r:0)  0@5632r
%vreg641 [5648r,5680r:0)  0@5648r
%vreg642 [5664r,5680r:1)[5680r,5696r:0)  0@5680r 1@5664r
%vreg647 [5504r,5520r:0)  0@5504r
%vreg648 [5520r,5632r:0)  0@5520r
%vreg649 [5536r,5552r:0)  0@5536r
%vreg650 [5552r,5648r:0)  0@5552r
%vreg651 [5568r,5584r:0)  0@5568r
%vreg652 [5584r,5632r:0)  0@5584r
%vreg653 [5600r,5616r:0)  0@5600r
%vreg654 [5616r,5648r:0)  0@5616r
%vreg655 [5120r,5152r:0)  0@5120r
%vreg656 [5136r,5168r:0)  0@5136r
%vreg657 [5152r,5168r:1)[5168r,5184r:0)  0@5168r 1@5152r
%vreg662 [4992r,5008r:0)  0@4992r
%vreg663 [5008r,5120r:0)  0@5008r
%vreg664 [5024r,5040r:0)  0@5024r
%vreg665 [5040r,5136r:0)  0@5040r
%vreg666 [5056r,5072r:0)  0@5056r
%vreg667 [5072r,5120r:0)  0@5072r
%vreg668 [5088r,5104r:0)  0@5088r
%vreg669 [5104r,5136r:0)  0@5104r
%vreg670 [4480r,4512r:0)  0@4480r
%vreg671 [4496r,4528r:0)  0@4496r
%vreg672 [4512r,4528r:1)[4528r,4592r:0)  0@4528r 1@4512r
%vreg676 [4544r,4560r:2)[4560r,4576r:1)[4576r,8480r:0)  0@4576r 1@4560r 2@4544r
%vreg677 [4352r,4368r:0)  0@4352r
%vreg678 [4368r,4480r:0)  0@4368r
%vreg679 [4384r,4400r:0)  0@4384r
%vreg680 [4400r,4496r:0)  0@4400r
%vreg681 [4416r,4432r:0)  0@4416r
%vreg682 [4432r,4480r:0)  0@4432r
%vreg683 [4448r,4464r:0)  0@4448r
%vreg684 [4464r,4496r:0)  0@4464r
%vreg685 [4608r,4624r:0)  0@4608r
%vreg686 [4624r,4656r:0)  0@4624r
%vreg687 [4656r,4672r:1)[4672r,8320r:0)  0@4672r 1@4656r
%vreg689 [4640r,4672r:0)  0@4640r
%vreg690 [8416r,8448r:0)  0@8416r
%vreg691 [8432r,8464r:0)  0@8432r
%vreg692 [8448r,8464r:1)[8464r,8480r:0)  0@8464r 1@8448r
%vreg697 [8288r,8304r:0)  0@8288r
%vreg698 [8304r,8416r:0)  0@8304r
%vreg699 [8320r,8336r:0)  0@8320r
%vreg700 [8336r,8432r:0)  0@8336r
%vreg701 [8352r,8368r:0)  0@8352r
%vreg702 [8368r,8416r:0)  0@8368r
%vreg703 [8384r,8400r:0)  0@8384r
%vreg704 [8400r,8432r:0)  0@8400r
%vreg705 [7904r,7936r:0)  0@7904r
%vreg706 [7920r,7952r:0)  0@7920r
%vreg707 [7936r,7952r:1)[7952r,7968r:0)  0@7952r 1@7936r
%vreg712 [7776r,7792r:0)  0@7776r
%vreg713 [7792r,7904r:0)  0@7792r
%vreg714 [7808r,7824r:0)  0@7808r
%vreg715 [7824r,7920r:0)  0@7824r
%vreg716 [7840r,7856r:0)  0@7840r
%vreg717 [7856r,7904r:0)  0@7856r
%vreg718 [7872r,7888r:0)  0@7872r
%vreg719 [7888r,7920r:0)  0@7888r
%vreg720 [7392r,7424r:0)  0@7392r
%vreg721 [7408r,7440r:0)  0@7408r
%vreg722 [7424r,7440r:1)[7440r,7456r:0)  0@7440r 1@7424r
%vreg727 [7264r,7280r:0)  0@7264r
%vreg728 [7280r,7392r:0)  0@7280r
%vreg729 [7296r,7312r:0)  0@7296r
%vreg730 [7312r,7408r:0)  0@7312r
%vreg731 [7328r,7344r:0)  0@7328r
%vreg732 [7344r,7392r:0)  0@7344r
%vreg733 [7360r,7376r:0)  0@7360r
%vreg734 [7376r,7408r:0)  0@7376r
%vreg735 [6880r,6912r:0)  0@6880r
%vreg736 [6896r,6928r:0)  0@6896r
%vreg737 [6912r,6928r:1)[6928r,6944r:0)  0@6928r 1@6912r
%vreg742 [6752r,6768r:0)  0@6752r
%vreg743 [6768r,6880r:0)  0@6768r
%vreg744 [6784r,6800r:0)  0@6784r
%vreg745 [6800r,6896r:0)  0@6800r
%vreg746 [6816r,6832r:0)  0@6816r
%vreg747 [6832r,6880r:0)  0@6832r
%vreg748 [6848r,6864r:0)  0@6848r
%vreg749 [6864r,6896r:0)  0@6864r
%vreg750 [6368r,6400r:0)  0@6368r
%vreg751 [6384r,6416r:0)  0@6384r
%vreg752 [6400r,6416r:1)[6416r,6432r:0)  0@6416r 1@6400r
%vreg757 [6240r,6256r:0)  0@6240r
%vreg758 [6256r,6368r:0)  0@6256r
%vreg759 [6272r,6288r:0)  0@6272r
%vreg760 [6288r,6384r:0)  0@6288r
%vreg761 [6304r,6320r:0)  0@6304r
%vreg762 [6320r,6368r:0)  0@6320r
%vreg763 [6336r,6352r:0)  0@6336r
%vreg764 [6352r,6384r:0)  0@6352r
%vreg765 [5856r,5888r:0)  0@5856r
%vreg766 [5872r,5904r:0)  0@5872r
%vreg767 [5888r,5904r:1)[5904r,5920r:0)  0@5904r 1@5888r
%vreg772 [5728r,5744r:0)  0@5728r
%vreg773 [5744r,5856r:0)  0@5744r
%vreg774 [5760r,5776r:0)  0@5760r
%vreg775 [5776r,5872r:0)  0@5776r
%vreg776 [5792r,5808r:0)  0@5792r
%vreg777 [5808r,5856r:0)  0@5808r
%vreg778 [5824r,5840r:0)  0@5824r
%vreg779 [5840r,5872r:0)  0@5840r
%vreg780 [5344r,5376r:0)  0@5344r
%vreg781 [5360r,5392r:0)  0@5360r
%vreg782 [5376r,5392r:1)[5392r,5408r:0)  0@5392r 1@5376r
%vreg787 [5216r,5232r:0)  0@5216r
%vreg788 [5232r,5344r:0)  0@5232r
%vreg789 [5248r,5264r:0)  0@5248r
%vreg790 [5264r,5360r:0)  0@5264r
%vreg791 [5280r,5296r:0)  0@5280r
%vreg792 [5296r,5344r:0)  0@5296r
%vreg793 [5312r,5328r:0)  0@5312r
%vreg794 [5328r,5360r:0)  0@5328r
%vreg795 [4832r,4864r:0)  0@4832r
%vreg796 [4848r,4880r:0)  0@4848r
%vreg797 [4864r,4880r:1)[4880r,4896r:0)  0@4880r 1@4864r
%vreg802 [4704r,4720r:0)  0@4704r
%vreg803 [4720r,4832r:0)  0@4720r
%vreg804 [4736r,4752r:0)  0@4736r
%vreg805 [4752r,4848r:0)  0@4752r
%vreg806 [4768r,4784r:0)  0@4768r
%vreg807 [4784r,4832r:0)  0@4784r
%vreg808 [4800r,4816r:0)  0@4800r
%vreg809 [4816r,4848r:0)  0@4816r
%vreg810 [9312r,9360r:0)  0@9312r
%vreg811 [9360r,9408r:0)  0@9360r
%vreg812 [9408r,9424r:1)[9424r,9632r:0)  0@9424r 1@9408r
%vreg815 [9632r,9712r:0)  0@9632r
%vreg816 [9344r,9392r:0)  0@9344r
%vreg817 [9392r,9424r:0)  0@9392r
%vreg818 [9376r,9392r:0)  0@9376r
%vreg819 [9440r,9472r:0)  0@9440r
%vreg820 [9472r,9520r:0)  0@9472r
%vreg821 [9520r,9536r:1)[9536r,9648r:0)  0@9536r 1@9520r
%vreg824 [9648r,9728r:0)  0@9648r
%vreg825 [9456r,9504r:0)  0@9456r
%vreg826 [9504r,9536r:0)  0@9504r
%vreg827 [9488r,9504r:0)  0@9488r
%vreg828 [9984r,10032r:0)  0@9984r
%vreg829 [10032r,10080r:0)  0@10032r
%vreg830 [10080r,10096r:1)[10096r,10416r:0)  0@10096r 1@10080r
%vreg833 [10416r,10496r:0)  0@10416r
%vreg834 [10016r,10064r:0)  0@10016r
%vreg835 [10064r,10096r:0)  0@10064r
%vreg836 [10048r,10064r:0)  0@10048r
%vreg837 [10112r,10144r:0)  0@10112r
%vreg838 [10144r,10192r:0)  0@10144r
%vreg839 [10192r,10208r:1)[10208r,10432r:0)  0@10208r 1@10192r
%vreg842 [10432r,10512r:0)  0@10432r
%vreg843 [10128r,10176r:0)  0@10128r
%vreg844 [10176r,10208r:0)  0@10176r
%vreg845 [10160r,10176r:0)  0@10160r
%vreg847 [10816r,10848r:0)  0@10816r
%vreg848 [10832r,10864r:0)  0@10832r
%vreg849 [800r,864B:0)[2176r,2224B:1)[3408B,3440r:2)  0@800r 1@2176r 2@3408B-phi
%vreg850 [816r,864B:0)[2192r,2224B:1)[3408B,3424r:2)  0@816r 1@2192r 2@3408B-phi
%vreg851 [2000r,2096B:0)[3552B,3632r:2)[9696r,9808B:1)  0@2000r 1@9696r 2@3552B-phi
%vreg852 [2016r,2096B:0)[3552B,3616r:2)[9712r,9808B:1)  0@2016r 1@9712r 2@3552B-phi
%vreg853 [2032r,2096B:0)[3552B,3600r:2)[9728r,9808B:1)  0@2032r 1@9728r 2@3552B-phi
%vreg854 [2048r,2096B:0)[3552B,3584r:2)[9744r,9808B:1)  0@2048r 1@9744r 2@3552B-phi
%vreg855 [2064r,2096B:0)[3552B,3568r:2)[9760r,9808B:1)  0@2064r 1@9760r 2@3552B-phi
%vreg856 [2320r,2368B:0)[9808B,9824r:2)[10624r,10656B:1)  0@2320r 1@10624r 2@9808B-phi
%vreg857 [3312r,3408B:0)[9872B,9952r:2)[10480r,10592B:1)  0@3312r 1@10480r 2@9872B-phi
%vreg858 [3328r,3408B:0)[9872B,9936r:2)[10496r,10592B:1)  0@3328r 1@10496r 2@9872B-phi
%vreg859 [3344r,3408B:0)[9872B,9920r:2)[10512r,10592B:1)  0@3344r 1@10512r 2@9872B-phi
%vreg860 [3360r,3408B:0)[9872B,9904r:2)[10528r,10592B:1)  0@3360r 1@10528r 2@9872B-phi
%vreg861 [3376r,3408B:0)[9872B,9888r:2)[10544r,10592B:1)  0@3376r 1@10544r 2@9872B-phi
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
32B		%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
48B		%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
64B		%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
112B		%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg59, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg59
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
224B		%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg57, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg57
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
368B		%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
384B		%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
400B		%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
416B		%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
432B		%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
448B		%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
512B		%vreg442<def> = COPY %vreg57; VReg_32:%vreg442,%vreg57
528B		%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
544B		%vreg445<def> = COPY %vreg59; VReg_32:%vreg445,%vreg59
560B		%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
576B		%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
592B		%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
608B		%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
624B		%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
640B		%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
656B		%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
672B		%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
736B		%vreg448<def> = COPY %vreg90; VReg_32:%vreg448,%vreg90
752B		%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
768B		%vreg87<def> = COPY %vreg91; VGPR_32:%vreg87,%vreg91
784B		%vreg450<def> = COPY %vreg448; VReg_32:%vreg450,%vreg448
800B		%vreg849<def> = COPY %vreg87; VGPR_32:%vreg849,%vreg87
816B		%vreg850<def> = COPY %vreg450; VReg_32:%vreg850,%vreg450
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg443
944B		%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg101, %EXEC<imp-use>; VReg_32:%vreg497,%vreg101
960B		%vreg104:sub0<def,read-undef> = COPY %vreg101; VReg_64:%vreg104 VReg_32:%vreg101
976B		%vreg104:sub1<def> = COPY %vreg497; VReg_64:%vreg104 VReg_32:%vreg497
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1008B		%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
1024B		%vreg500<def> = COPY %vreg499:sub1; VReg_32:%vreg500 VReg_64:%vreg499
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
1072B		%vreg515<def> = V_ADD_I32_e32 %vreg516, %vreg514, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
1088B		%vreg501<def> = V_ADDC_U32_e32 %vreg500, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg501,%vreg500,%vreg517
1104B		%vreg503:sub0<def,read-undef> = COPY %vreg515; VReg_64:%vreg503 VReg_32:%vreg515
1120B		%vreg503:sub1<def> = COPY %vreg501; VReg_64:%vreg503 VReg_32:%vreg501
1136B		%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
1152B		%vreg506<def> = COPY %vreg503:sub1; VReg_32:%vreg506 VReg_64:%vreg503
1168B		%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
1184B		%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
1200B		%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
1216B		%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
1232B		%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
1248B		%vreg507<def> = V_ADDC_U32_e32 %vreg506, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg507,%vreg506,%vreg508
1264B		%vreg509:sub0<def,read-undef> = COPY %vreg513; VReg_64:%vreg509 VReg_32:%vreg513
1280B		%vreg509:sub1<def> = COPY %vreg507; VReg_64:%vreg509 VReg_32:%vreg507
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg127, %EXEC<imp-use>; VReg_32:%vreg520,%vreg127
1376B		%vreg130:sub0<def,read-undef> = COPY %vreg127; VReg_64:%vreg130 VReg_32:%vreg127
1392B		%vreg130:sub1<def> = COPY %vreg520; VReg_64:%vreg130 VReg_32:%vreg520
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1424B		%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
1440B		%vreg523<def> = COPY %vreg522:sub1; VReg_32:%vreg523 VReg_64:%vreg522
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
1488B		%vreg538<def> = V_ADD_I32_e32 %vreg539, %vreg537, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
1504B		%vreg524<def> = V_ADDC_U32_e32 %vreg523, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg524,%vreg523,%vreg540
1520B		%vreg526:sub0<def,read-undef> = COPY %vreg538; VReg_64:%vreg526 VReg_32:%vreg538
1536B		%vreg526:sub1<def> = COPY %vreg524; VReg_64:%vreg526 VReg_32:%vreg524
1552B		%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
1568B		%vreg529<def> = COPY %vreg526:sub1; VReg_32:%vreg529 VReg_64:%vreg526
1584B		%vreg536<def> = V_ADD_I32_e32 %vreg117, %vreg535, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
1600B		%vreg531<def> = COPY %vreg118; VReg_32:%vreg531 SReg_32:%vreg118
1616B		%vreg530<def> = V_ADDC_U32_e32 %vreg529, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg530,%vreg529,%vreg531
1632B		%vreg532:sub0<def,read-undef> = COPY %vreg536; VReg_64:%vreg532 VReg_32:%vreg536
1648B		%vreg532:sub1<def> = COPY %vreg530; VReg_64:%vreg532 VReg_32:%vreg530
1664B		%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
1680B		%vreg95<def> = COPY %vreg145; VGPR_32:%vreg95,%vreg145
1696B		%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
1712B		%vreg541<def> = COPY %vreg146; VReg_32:%vreg541,%vreg146
1728B		%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
1744B		%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
1760B		%vreg12<def> = COPY %vreg509; VReg_64:%vreg12,%vreg509
1776B		%vreg11<def> = COPY %vreg532; VReg_64:%vreg11,%vreg532
1792B		%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
1808B		%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
1824B		%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
1840B		%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
1856B		%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
1872B		%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
1888B		%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
1904B		%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
1920B		%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
1936B		%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
1952B		%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
1968B		%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
1984B		%vreg543<def> = COPY %vreg541; VReg_32:%vreg543,%vreg541
2000B		%vreg851<def> = COPY %vreg93; SReg_64:%vreg851 SGPR_64:%vreg93
2016B		%vreg852<def> = COPY %vreg12; VReg_64:%vreg852,%vreg12
2032B		%vreg853<def> = COPY %vreg11; VReg_64:%vreg853,%vreg11
2048B		%vreg854<def> = COPY %vreg543; VReg_32:%vreg854,%vreg543
2064B		%vreg855<def> = COPY %vreg95; VGPR_32:%vreg855,%vreg95
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg31, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg31
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg451<def> = COPY %vreg13; VReg_32:%vreg451 SReg_32:%vreg13
2176B		%vreg849<def> = COPY %vreg27; VGPR_32:%vreg849,%vreg27
2192B		%vreg850<def> = COPY %vreg451; VReg_32:%vreg850,%vreg451
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg453, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg453 VGPR_32:%vreg300
2320B		%vreg856<def> = COPY %vreg20; VGPR_32:%vreg856,%vreg20
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg309, %EXEC<imp-use>; VReg_32:%vreg548,%vreg309
2464B		%vreg312:sub0<def,read-undef> = COPY %vreg309; VReg_64:%vreg312 VReg_32:%vreg309
2480B		%vreg312:sub1<def> = COPY %vreg548; VReg_64:%vreg312 VReg_32:%vreg548
2496B		%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
2512B		%vreg550<def> = COPY %vreg312:sub1; VReg_32:%vreg550 VReg_64:%vreg312
2528B		%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg453, %EXEC<imp-use>; VReg_32:%vreg494,%vreg453
2544B		%vreg459:sub0<def,read-undef> = COPY %vreg453; VReg_64:%vreg459 VReg_32:%vreg453
2560B		%vreg459:sub1<def> = COPY %vreg494; VReg_64:%vreg459 VReg_32:%vreg494
2576B		%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
2592B		%vreg462<def> = COPY %vreg459:sub1; VReg_32:%vreg462 VReg_64:%vreg459
2608B		%vreg493<def> = V_ADD_I32_e32 %vreg549, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
2624B		%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg550, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg477,%vreg462,%vreg550
2640B		%vreg479:sub0<def,read-undef> = COPY %vreg493; VReg_64:%vreg479 VReg_32:%vreg493
2656B		%vreg479:sub1<def> = COPY %vreg477; VReg_64:%vreg479 VReg_32:%vreg477
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2688B		%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
2704B		%vreg483<def> = COPY %vreg482:sub1; VReg_32:%vreg483 VReg_64:%vreg482
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
2752B		%vreg490<def> = V_ADD_I32_e32 %vreg551, %vreg489, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
2768B		%vreg484<def> = V_ADDC_U32_e32 %vreg552, %vreg483, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg484,%vreg552,%vreg483
2784B		%vreg486:sub0<def,read-undef> = COPY %vreg490; VReg_64:%vreg486 VReg_32:%vreg490
2800B		%vreg486:sub1<def> = COPY %vreg484; VReg_64:%vreg486 VReg_32:%vreg484
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg335, %EXEC<imp-use>; VReg_32:%vreg555,%vreg335
2896B		%vreg338:sub0<def,read-undef> = COPY %vreg335; VReg_64:%vreg338 VReg_32:%vreg335
2912B		%vreg338:sub1<def> = COPY %vreg555; VReg_64:%vreg338 VReg_32:%vreg555
2928B		%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
2944B		%vreg557<def> = COPY %vreg338:sub1; VReg_32:%vreg557 VReg_64:%vreg338
2960B		%vreg492<def> = V_ADD_I32_e32 %vreg556, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
2976B		%vreg463<def> = V_ADDC_U32_e32 %vreg462, %vreg557, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg463,%vreg462,%vreg557
2992B		%vreg465:sub0<def,read-undef> = COPY %vreg492; VReg_64:%vreg465 VReg_32:%vreg492
3008B		%vreg465:sub1<def> = COPY %vreg463; VReg_64:%vreg465 VReg_32:%vreg463
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3040B		%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
3056B		%vreg469<def> = COPY %vreg468:sub1; VReg_32:%vreg469 VReg_64:%vreg468
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
3104B		%vreg476<def> = V_ADD_I32_e32 %vreg558, %vreg475, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
3120B		%vreg470<def> = V_ADDC_U32_e32 %vreg559, %vreg469, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg470,%vreg559,%vreg469
3136B		%vreg472:sub0<def,read-undef> = COPY %vreg476; VReg_64:%vreg472 VReg_32:%vreg476
3152B		%vreg472:sub1<def> = COPY %vreg470; VReg_64:%vreg472 VReg_32:%vreg470
3168B		%vreg454<def> = V_SUB_I32_e32 %vreg55, %vreg453, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg454,%vreg453 SReg_32:%vreg55
3184B		%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
3200B		%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
3216B		%vreg19<def> = COPY %vreg486; VReg_64:%vreg19,%vreg486
3232B		%vreg18<def> = COPY %vreg472; VReg_64:%vreg18,%vreg472
3248B		%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
3264B		%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
3280B		%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
3296B		%vreg456<def> = COPY %vreg454; VReg_32:%vreg456,%vreg454
3312B		%vreg857<def> = COPY %vreg303; SReg_64:%vreg857 SGPR_64:%vreg303
3328B		%vreg858<def> = COPY %vreg19; VReg_64:%vreg858,%vreg19
3344B		%vreg859<def> = COPY %vreg18; VReg_64:%vreg859,%vreg18
3360B		%vreg860<def> = COPY %vreg456; VReg_32:%vreg860,%vreg456
3376B		%vreg861<def> = COPY %vreg20; VGPR_32:%vreg861,%vreg20
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3424B		%vreg449<def> = COPY %vreg850; VReg_32:%vreg449,%vreg850
3440B		%vreg20<def> = COPY %vreg849; VGPR_32:%vreg20,%vreg849
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3472B		%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
3488B		%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3520B		%vreg453<def> = COPY %vreg449; VReg_32:%vreg453,%vreg449
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3568B		%vreg26<def> = COPY %vreg855; VGPR_32:%vreg26,%vreg855
3584B		%vreg542<def> = COPY %vreg854; VReg_32:%vreg542,%vreg854
3600B		%vreg24<def> = COPY %vreg853; VReg_64:%vreg24,%vreg853
3616B		%vreg23<def> = COPY %vreg852; VReg_64:%vreg23,%vreg852
3632B		%vreg22<def> = COPY %vreg851; SReg_64:%vreg22,%vreg851
3648B		%vreg399:sub0<def,read-undef> = COPY %vreg401; SGPR_64:%vreg399 SGPR_32:%vreg401
3664B		%vreg399:sub1<def> = COPY %vreg400; SGPR_64:%vreg399 SGPR_32:%vreg400
3680B		%vreg148:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg148 SGPR_64:%vreg147
3696B		%vreg148:sub2_sub3<def> = COPY %vreg399; SReg_128:%vreg148 SGPR_64:%vreg399
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
4224B		%vreg183:sub0<def,read-undef> = COPY %vreg182; SGPR_64:%vreg183 SReg_32:%vreg182
4240B		%vreg183:sub1<def> = COPY %vreg181; SGPR_64:%vreg183 SReg_32:%vreg181
4256B		%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
4272B		%vreg561<def> = COPY %vreg560; VReg_64:%vreg561,%vreg560
4288B		%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
4304B		%vreg562:sub0_sub1<def,read-undef> = COPY %vreg561; VReg_128:%vreg562 VReg_64:%vreg561
4320B		%vreg562:sub2_sub3<def> = COPY %vreg564; VReg_128:%vreg562 VReg_64:%vreg564
4336B		%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
4352B		%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
4368B		%vreg678<def> = COPY %vreg677:sub0; VReg_32:%vreg678 VReg_128:%vreg677
4384B		%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
4400B		%vreg680<def> = COPY %vreg679:sub1; VReg_32:%vreg680 VReg_128:%vreg679
4416B		%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
4432B		%vreg682<def> = COPY %vreg681:sub0; VReg_32:%vreg682 VReg_64:%vreg681
4448B		%vreg683<def> = COPY %vreg187; VReg_64:%vreg683,%vreg187
4464B		%vreg684<def> = COPY %vreg683:sub1; VReg_32:%vreg684 VReg_64:%vreg683
4480B		%vreg670<def> = V_ADD_I32_e32 %vreg678, %vreg682, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
4496B		%vreg671<def> = V_ADDC_U32_e32 %vreg680, %vreg684, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
4512B		%vreg672:sub0<def,read-undef> = COPY %vreg670; VReg_64:%vreg672 VReg_32:%vreg670
4528B		%vreg672:sub1<def> = COPY %vreg671; VReg_64:%vreg672 VReg_32:%vreg671
4544B		%vreg676:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg676 SGPR_64:%vreg147
4560B		%vreg676:sub2<def> = COPY %vreg401; SReg_128:%vreg676 SGPR_32:%vreg401
4576B		%vreg676:sub3<def> = COPY %vreg400; SReg_128:%vreg676 SGPR_32:%vreg400
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4608B		%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
4624B		%vreg686<def> = COPY %vreg685; VReg_64:%vreg686,%vreg685
4640B		%vreg689<def> = COPY %vreg399; VReg_64:%vreg689 SGPR_64:%vreg399
4656B		%vreg687:sub0_sub1<def,read-undef> = COPY %vreg686; VReg_128:%vreg687 VReg_64:%vreg686
4672B		%vreg687:sub2_sub3<def> = COPY %vreg689; VReg_128:%vreg687 VReg_64:%vreg689
4688B		%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
4704B		%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
4720B		%vreg803<def> = COPY %vreg802:sub0; VReg_32:%vreg803 VReg_128:%vreg802
4736B		%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
4752B		%vreg805<def> = COPY %vreg804:sub1; VReg_32:%vreg805 VReg_128:%vreg804
4768B		%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
4784B		%vreg807<def> = COPY %vreg806:sub0; VReg_32:%vreg807 VReg_64:%vreg806
4800B		%vreg808<def> = COPY %vreg191; VReg_64:%vreg808,%vreg191
4816B		%vreg809<def> = COPY %vreg808:sub1; VReg_32:%vreg809 VReg_64:%vreg808
4832B		%vreg795<def> = V_ADD_I32_e32 %vreg803, %vreg807, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
4848B		%vreg796<def> = V_ADDC_U32_e32 %vreg805, %vreg809, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
4864B		%vreg797:sub0<def,read-undef> = COPY %vreg795; VReg_64:%vreg797 VReg_32:%vreg795
4880B		%vreg797:sub1<def> = COPY %vreg796; VReg_64:%vreg797 VReg_32:%vreg796
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
4944B		%vreg195:sub0<def,read-undef> = COPY %vreg194; SGPR_64:%vreg195 SReg_32:%vreg194
4960B		%vreg195:sub1<def> = COPY %vreg181; SGPR_64:%vreg195 SReg_32:%vreg181
4976B		%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
4992B		%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
5008B		%vreg663<def> = COPY %vreg662:sub0; VReg_32:%vreg663 VReg_128:%vreg662
5024B		%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
5040B		%vreg665<def> = COPY %vreg664:sub1; VReg_32:%vreg665 VReg_128:%vreg664
5056B		%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
5072B		%vreg667<def> = COPY %vreg666:sub0; VReg_32:%vreg667 VReg_64:%vreg666
5088B		%vreg668<def> = COPY %vreg197; VReg_64:%vreg668,%vreg197
5104B		%vreg669<def> = COPY %vreg668:sub1; VReg_32:%vreg669 VReg_64:%vreg668
5120B		%vreg655<def> = V_ADD_I32_e32 %vreg663, %vreg667, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
5136B		%vreg656<def> = V_ADDC_U32_e32 %vreg665, %vreg669, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
5152B		%vreg657:sub0<def,read-undef> = COPY %vreg655; VReg_64:%vreg657 VReg_32:%vreg655
5168B		%vreg657:sub1<def> = COPY %vreg656; VReg_64:%vreg657 VReg_32:%vreg656
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
5216B		%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
5232B		%vreg788<def> = COPY %vreg787:sub0; VReg_32:%vreg788 VReg_128:%vreg787
5248B		%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
5264B		%vreg790<def> = COPY %vreg789:sub1; VReg_32:%vreg790 VReg_128:%vreg789
5280B		%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
5296B		%vreg792<def> = COPY %vreg791:sub0; VReg_32:%vreg792 VReg_64:%vreg791
5312B		%vreg793<def> = COPY %vreg199; VReg_64:%vreg793,%vreg199
5328B		%vreg794<def> = COPY %vreg793:sub1; VReg_32:%vreg794 VReg_64:%vreg793
5344B		%vreg780<def> = V_ADD_I32_e32 %vreg788, %vreg792, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
5360B		%vreg781<def> = V_ADDC_U32_e32 %vreg790, %vreg794, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
5376B		%vreg782:sub0<def,read-undef> = COPY %vreg780; VReg_64:%vreg782 VReg_32:%vreg780
5392B		%vreg782:sub1<def> = COPY %vreg781; VReg_64:%vreg782 VReg_32:%vreg781
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
5456B		%vreg203:sub0<def,read-undef> = COPY %vreg202; SGPR_64:%vreg203 SReg_32:%vreg202
5472B		%vreg203:sub1<def> = COPY %vreg181; SGPR_64:%vreg203 SReg_32:%vreg181
5488B		%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
5504B		%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
5520B		%vreg648<def> = COPY %vreg647:sub0; VReg_32:%vreg648 VReg_128:%vreg647
5536B		%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
5552B		%vreg650<def> = COPY %vreg649:sub1; VReg_32:%vreg650 VReg_128:%vreg649
5568B		%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
5584B		%vreg652<def> = COPY %vreg651:sub0; VReg_32:%vreg652 VReg_64:%vreg651
5600B		%vreg653<def> = COPY %vreg205; VReg_64:%vreg653,%vreg205
5616B		%vreg654<def> = COPY %vreg653:sub1; VReg_32:%vreg654 VReg_64:%vreg653
5632B		%vreg640<def> = V_ADD_I32_e32 %vreg648, %vreg652, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
5648B		%vreg641<def> = V_ADDC_U32_e32 %vreg650, %vreg654, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
5664B		%vreg642:sub0<def,read-undef> = COPY %vreg640; VReg_64:%vreg642 VReg_32:%vreg640
5680B		%vreg642:sub1<def> = COPY %vreg641; VReg_64:%vreg642 VReg_32:%vreg641
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
5728B		%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
5744B		%vreg773<def> = COPY %vreg772:sub0; VReg_32:%vreg773 VReg_128:%vreg772
5760B		%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
5776B		%vreg775<def> = COPY %vreg774:sub1; VReg_32:%vreg775 VReg_128:%vreg774
5792B		%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
5808B		%vreg777<def> = COPY %vreg776:sub0; VReg_32:%vreg777 VReg_64:%vreg776
5824B		%vreg778<def> = COPY %vreg207; VReg_64:%vreg778,%vreg207
5840B		%vreg779<def> = COPY %vreg778:sub1; VReg_32:%vreg779 VReg_64:%vreg778
5856B		%vreg765<def> = V_ADD_I32_e32 %vreg773, %vreg777, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
5872B		%vreg766<def> = V_ADDC_U32_e32 %vreg775, %vreg779, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
5888B		%vreg767:sub0<def,read-undef> = COPY %vreg765; VReg_64:%vreg767 VReg_32:%vreg765
5904B		%vreg767:sub1<def> = COPY %vreg766; VReg_64:%vreg767 VReg_32:%vreg766
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
5968B		%vreg211:sub0<def,read-undef> = COPY %vreg210; SGPR_64:%vreg211 SReg_32:%vreg210
5984B		%vreg211:sub1<def> = COPY %vreg181; SGPR_64:%vreg211 SReg_32:%vreg181
6000B		%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
6016B		%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
6032B		%vreg633<def> = COPY %vreg632:sub0; VReg_32:%vreg633 VReg_128:%vreg632
6048B		%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
6064B		%vreg635<def> = COPY %vreg634:sub1; VReg_32:%vreg635 VReg_128:%vreg634
6080B		%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
6096B		%vreg637<def> = COPY %vreg636:sub0; VReg_32:%vreg637 VReg_64:%vreg636
6112B		%vreg638<def> = COPY %vreg213; VReg_64:%vreg638,%vreg213
6128B		%vreg639<def> = COPY %vreg638:sub1; VReg_32:%vreg639 VReg_64:%vreg638
6144B		%vreg625<def> = V_ADD_I32_e32 %vreg633, %vreg637, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
6160B		%vreg626<def> = V_ADDC_U32_e32 %vreg635, %vreg639, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
6176B		%vreg627:sub0<def,read-undef> = COPY %vreg625; VReg_64:%vreg627 VReg_32:%vreg625
6192B		%vreg627:sub1<def> = COPY %vreg626; VReg_64:%vreg627 VReg_32:%vreg626
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
6240B		%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
6256B		%vreg758<def> = COPY %vreg757:sub0; VReg_32:%vreg758 VReg_128:%vreg757
6272B		%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
6288B		%vreg760<def> = COPY %vreg759:sub1; VReg_32:%vreg760 VReg_128:%vreg759
6304B		%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
6320B		%vreg762<def> = COPY %vreg761:sub0; VReg_32:%vreg762 VReg_64:%vreg761
6336B		%vreg763<def> = COPY %vreg215; VReg_64:%vreg763,%vreg215
6352B		%vreg764<def> = COPY %vreg763:sub1; VReg_32:%vreg764 VReg_64:%vreg763
6368B		%vreg750<def> = V_ADD_I32_e32 %vreg758, %vreg762, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
6384B		%vreg751<def> = V_ADDC_U32_e32 %vreg760, %vreg764, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
6400B		%vreg752:sub0<def,read-undef> = COPY %vreg750; VReg_64:%vreg752 VReg_32:%vreg750
6416B		%vreg752:sub1<def> = COPY %vreg751; VReg_64:%vreg752 VReg_32:%vreg751
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
6480B		%vreg219:sub0<def,read-undef> = COPY %vreg218; SGPR_64:%vreg219 SReg_32:%vreg218
6496B		%vreg219:sub1<def> = COPY %vreg181; SGPR_64:%vreg219 SReg_32:%vreg181
6512B		%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
6528B		%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
6544B		%vreg618<def> = COPY %vreg617:sub0; VReg_32:%vreg618 VReg_128:%vreg617
6560B		%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
6576B		%vreg620<def> = COPY %vreg619:sub1; VReg_32:%vreg620 VReg_128:%vreg619
6592B		%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
6608B		%vreg622<def> = COPY %vreg621:sub0; VReg_32:%vreg622 VReg_64:%vreg621
6624B		%vreg623<def> = COPY %vreg221; VReg_64:%vreg623,%vreg221
6640B		%vreg624<def> = COPY %vreg623:sub1; VReg_32:%vreg624 VReg_64:%vreg623
6656B		%vreg610<def> = V_ADD_I32_e32 %vreg618, %vreg622, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
6672B		%vreg611<def> = V_ADDC_U32_e32 %vreg620, %vreg624, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
6688B		%vreg612:sub0<def,read-undef> = COPY %vreg610; VReg_64:%vreg612 VReg_32:%vreg610
6704B		%vreg612:sub1<def> = COPY %vreg611; VReg_64:%vreg612 VReg_32:%vreg611
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
6752B		%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
6768B		%vreg743<def> = COPY %vreg742:sub0; VReg_32:%vreg743 VReg_128:%vreg742
6784B		%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
6800B		%vreg745<def> = COPY %vreg744:sub1; VReg_32:%vreg745 VReg_128:%vreg744
6816B		%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
6832B		%vreg747<def> = COPY %vreg746:sub0; VReg_32:%vreg747 VReg_64:%vreg746
6848B		%vreg748<def> = COPY %vreg223; VReg_64:%vreg748,%vreg223
6864B		%vreg749<def> = COPY %vreg748:sub1; VReg_32:%vreg749 VReg_64:%vreg748
6880B		%vreg735<def> = V_ADD_I32_e32 %vreg743, %vreg747, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
6896B		%vreg736<def> = V_ADDC_U32_e32 %vreg745, %vreg749, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
6912B		%vreg737:sub0<def,read-undef> = COPY %vreg735; VReg_64:%vreg737 VReg_32:%vreg735
6928B		%vreg737:sub1<def> = COPY %vreg736; VReg_64:%vreg737 VReg_32:%vreg736
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
6992B		%vreg227:sub0<def,read-undef> = COPY %vreg226; SGPR_64:%vreg227 SReg_32:%vreg226
7008B		%vreg227:sub1<def> = COPY %vreg181; SGPR_64:%vreg227 SReg_32:%vreg181
7024B		%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
7040B		%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
7056B		%vreg603<def> = COPY %vreg602:sub0; VReg_32:%vreg603 VReg_128:%vreg602
7072B		%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
7088B		%vreg605<def> = COPY %vreg604:sub1; VReg_32:%vreg605 VReg_128:%vreg604
7104B		%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
7120B		%vreg607<def> = COPY %vreg606:sub0; VReg_32:%vreg607 VReg_64:%vreg606
7136B		%vreg608<def> = COPY %vreg229; VReg_64:%vreg608,%vreg229
7152B		%vreg609<def> = COPY %vreg608:sub1; VReg_32:%vreg609 VReg_64:%vreg608
7168B		%vreg595<def> = V_ADD_I32_e32 %vreg603, %vreg607, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
7184B		%vreg596<def> = V_ADDC_U32_e32 %vreg605, %vreg609, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
7200B		%vreg597:sub0<def,read-undef> = COPY %vreg595; VReg_64:%vreg597 VReg_32:%vreg595
7216B		%vreg597:sub1<def> = COPY %vreg596; VReg_64:%vreg597 VReg_32:%vreg596
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
7264B		%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
7280B		%vreg728<def> = COPY %vreg727:sub0; VReg_32:%vreg728 VReg_128:%vreg727
7296B		%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
7312B		%vreg730<def> = COPY %vreg729:sub1; VReg_32:%vreg730 VReg_128:%vreg729
7328B		%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
7344B		%vreg732<def> = COPY %vreg731:sub0; VReg_32:%vreg732 VReg_64:%vreg731
7360B		%vreg733<def> = COPY %vreg231; VReg_64:%vreg733,%vreg231
7376B		%vreg734<def> = COPY %vreg733:sub1; VReg_32:%vreg734 VReg_64:%vreg733
7392B		%vreg720<def> = V_ADD_I32_e32 %vreg728, %vreg732, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
7408B		%vreg721<def> = V_ADDC_U32_e32 %vreg730, %vreg734, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
7424B		%vreg722:sub0<def,read-undef> = COPY %vreg720; VReg_64:%vreg722 VReg_32:%vreg720
7440B		%vreg722:sub1<def> = COPY %vreg721; VReg_64:%vreg722 VReg_32:%vreg721
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
7504B		%vreg235:sub0<def,read-undef> = COPY %vreg234; SGPR_64:%vreg235 SReg_32:%vreg234
7520B		%vreg235:sub1<def> = COPY %vreg181; SGPR_64:%vreg235 SReg_32:%vreg181
7536B		%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
7552B		%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
7568B		%vreg588<def> = COPY %vreg587:sub0; VReg_32:%vreg588 VReg_128:%vreg587
7584B		%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
7600B		%vreg590<def> = COPY %vreg589:sub1; VReg_32:%vreg590 VReg_128:%vreg589
7616B		%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
7632B		%vreg592<def> = COPY %vreg591:sub0; VReg_32:%vreg592 VReg_64:%vreg591
7648B		%vreg593<def> = COPY %vreg237; VReg_64:%vreg593,%vreg237
7664B		%vreg594<def> = COPY %vreg593:sub1; VReg_32:%vreg594 VReg_64:%vreg593
7680B		%vreg580<def> = V_ADD_I32_e32 %vreg588, %vreg592, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
7696B		%vreg581<def> = V_ADDC_U32_e32 %vreg590, %vreg594, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
7712B		%vreg582:sub0<def,read-undef> = COPY %vreg580; VReg_64:%vreg582 VReg_32:%vreg580
7728B		%vreg582:sub1<def> = COPY %vreg581; VReg_64:%vreg582 VReg_32:%vreg581
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
7776B		%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
7792B		%vreg713<def> = COPY %vreg712:sub0; VReg_32:%vreg713 VReg_128:%vreg712
7808B		%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
7824B		%vreg715<def> = COPY %vreg714:sub1; VReg_32:%vreg715 VReg_128:%vreg714
7840B		%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
7856B		%vreg717<def> = COPY %vreg716:sub0; VReg_32:%vreg717 VReg_64:%vreg716
7872B		%vreg718<def> = COPY %vreg239; VReg_64:%vreg718,%vreg239
7888B		%vreg719<def> = COPY %vreg718:sub1; VReg_32:%vreg719 VReg_64:%vreg718
7904B		%vreg705<def> = V_ADD_I32_e32 %vreg713, %vreg717, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
7920B		%vreg706<def> = V_ADDC_U32_e32 %vreg715, %vreg719, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
7936B		%vreg707:sub0<def,read-undef> = COPY %vreg705; VReg_64:%vreg707 VReg_32:%vreg705
7952B		%vreg707:sub1<def> = COPY %vreg706; VReg_64:%vreg707 VReg_32:%vreg706
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
8016B		%vreg243:sub0<def,read-undef> = COPY %vreg242; SGPR_64:%vreg243 SReg_32:%vreg242
8032B		%vreg243:sub1<def> = COPY %vreg181; SGPR_64:%vreg243 SReg_32:%vreg181
8048B		%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
8064B		%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
8080B		%vreg573<def> = COPY %vreg572:sub0; VReg_32:%vreg573 VReg_128:%vreg572
8096B		%vreg574<def> = COPY %vreg562; VReg_128:%vreg574,%vreg562
8112B		%vreg575<def> = COPY %vreg574:sub1; VReg_32:%vreg575 VReg_128:%vreg574
8128B		%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
8144B		%vreg577<def> = COPY %vreg576:sub0; VReg_32:%vreg577 VReg_64:%vreg576
8160B		%vreg578<def> = COPY %vreg245; VReg_64:%vreg578,%vreg245
8176B		%vreg579<def> = COPY %vreg578:sub1; VReg_32:%vreg579 VReg_64:%vreg578
8192B		%vreg565<def> = V_ADD_I32_e32 %vreg573, %vreg577, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
8208B		%vreg566<def> = V_ADDC_U32_e32 %vreg575, %vreg579, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
8224B		%vreg567:sub0<def,read-undef> = COPY %vreg565; VReg_64:%vreg567 VReg_32:%vreg565
8240B		%vreg567:sub1<def> = COPY %vreg566; VReg_64:%vreg567 VReg_32:%vreg566
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
8288B		%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
8304B		%vreg698<def> = COPY %vreg697:sub0; VReg_32:%vreg698 VReg_128:%vreg697
8320B		%vreg699<def> = COPY %vreg687; VReg_128:%vreg699,%vreg687
8336B		%vreg700<def> = COPY %vreg699:sub1; VReg_32:%vreg700 VReg_128:%vreg699
8352B		%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
8368B		%vreg702<def> = COPY %vreg701:sub0; VReg_32:%vreg702 VReg_64:%vreg701
8384B		%vreg703<def> = COPY %vreg247; VReg_64:%vreg703,%vreg247
8400B		%vreg704<def> = COPY %vreg703:sub1; VReg_32:%vreg704 VReg_64:%vreg703
8416B		%vreg690<def> = V_ADD_I32_e32 %vreg698, %vreg702, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
8432B		%vreg691<def> = V_ADDC_U32_e32 %vreg700, %vreg704, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
8448B		%vreg692:sub0<def,read-undef> = COPY %vreg690; VReg_64:%vreg692 VReg_32:%vreg690
8464B		%vreg692:sub1<def> = COPY %vreg691; VReg_64:%vreg692 VReg_32:%vreg691
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
8528B		%vreg250:sub0<def,read-undef> = COPY %vreg249; VReg_512:%vreg250 VGPR_32:%vreg249
8544B		%vreg250:sub1<def> = COPY %vreg241; VReg_512:%vreg250 VGPR_32:%vreg241
8560B		%vreg250:sub2<def> = COPY %vreg233; VReg_512:%vreg250 VGPR_32:%vreg233
8576B		%vreg250:sub3<def> = COPY %vreg225; VReg_512:%vreg250 VGPR_32:%vreg225
8592B		%vreg250:sub4<def> = COPY %vreg217; VReg_512:%vreg250 VGPR_32:%vreg217
8608B		%vreg250:sub5<def> = COPY %vreg209; VReg_512:%vreg250 VGPR_32:%vreg209
8624B		%vreg250:sub6<def> = COPY %vreg201; VReg_512:%vreg250 VGPR_32:%vreg201
8640B		%vreg250:sub7<def> = COPY %vreg193; VReg_512:%vreg250 VGPR_32:%vreg193
8656B		%vreg250:sub8<def> = COPY %vreg180; VReg_512:%vreg250 VGPR_32:%vreg180
8672B		%vreg250:sub9<def> = COPY %vreg176; VReg_512:%vreg250 VGPR_32:%vreg176
8688B		%vreg250:sub10<def> = COPY %vreg172; VReg_512:%vreg250 VGPR_32:%vreg172
8704B		%vreg250:sub11<def> = COPY %vreg168; VReg_512:%vreg250 VGPR_32:%vreg168
8720B		%vreg250:sub12<def> = COPY %vreg164; VReg_512:%vreg250 VGPR_32:%vreg164
8736B		%vreg250:sub13<def> = COPY %vreg160; VReg_512:%vreg250 VGPR_32:%vreg160
8752B		%vreg250:sub14<def> = COPY %vreg156; VReg_512:%vreg250 VGPR_32:%vreg156
8768B		%vreg250:sub15<def> = COPY %vreg152; VReg_512:%vreg250 VGPR_32:%vreg152
8784B		%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
8800B		%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg252, %vreg251, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
8832B		%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg254, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
8864B		%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg256, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
8896B		%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg258, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
8928B		%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg260, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
8960B		%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg262, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
8992B		%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg264, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
9024B		%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg266, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
9056B		%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg268, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
9088B		%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg270, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
9120B		%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg272, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
9152B		%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg274, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
9184B		%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg276, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
9216B		%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg278, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
9248B		%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg280, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
9280B		%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
9296B		%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
9312B		%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
9328B		%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
9344B		%vreg816<def> = COPY %vreg23:sub1; VReg_32:%vreg816 VReg_64:%vreg23
9360B		%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
9376B		%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
9392B		%vreg817<def> = V_ADDC_U32_e32 %vreg816, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg817,%vreg816,%vreg818
9408B		%vreg812:sub0<def,read-undef> = COPY %vreg811; VReg_64:%vreg812 VReg_32:%vreg811
9424B		%vreg812:sub1<def> = COPY %vreg817; VReg_64:%vreg812 VReg_32:%vreg817
9440B		%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
9456B		%vreg825<def> = COPY %vreg24:sub1; VReg_32:%vreg825 VReg_64:%vreg24
9472B		%vreg820<def> = V_ADD_I32_e32 %vreg284, %vreg819, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
9488B		%vreg827<def> = COPY %vreg286; VReg_32:%vreg827 SReg_32:%vreg286
9504B		%vreg826<def> = V_ADDC_U32_e32 %vreg825, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg826,%vreg825,%vreg827
9520B		%vreg821:sub0<def,read-undef> = COPY %vreg820; VReg_64:%vreg821 VReg_32:%vreg820
9536B		%vreg821:sub1<def> = COPY %vreg826; VReg_64:%vreg821 VReg_32:%vreg826
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg545<def> = V_ADD_I32_e32 16, %vreg542, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg545,%vreg542
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
9600B		%vreg298<def> = SI_IF_BREAK %vreg297, %vreg22, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
9616B		%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
9632B		%vreg815<def> = COPY %vreg812; VReg_64:%vreg815,%vreg812
9648B		%vreg824<def> = COPY %vreg821; VReg_64:%vreg824,%vreg821
9664B		%vreg27<def> = COPY %vreg282; VGPR_32:%vreg27,%vreg282
9680B		%vreg544<def> = COPY %vreg545; VReg_32:%vreg544,%vreg545
9696B		%vreg851<def> = COPY %vreg31; SReg_64:%vreg851,%vreg31
9712B		%vreg852<def> = COPY %vreg815; VReg_64:%vreg852,%vreg815
9728B		%vreg853<def> = COPY %vreg824; VReg_64:%vreg853,%vreg824
9744B		%vreg854<def> = COPY %vreg544; VReg_32:%vreg854,%vreg544
9760B		%vreg855<def> = COPY %vreg27; VGPR_32:%vreg855,%vreg27
9776B		SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9824B		%vreg32<def> = COPY %vreg856; VGPR_32:%vreg32,%vreg856
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
9888B		%vreg37<def> = COPY %vreg861; VGPR_32:%vreg37,%vreg861
9904B		%vreg455<def> = COPY %vreg860; VReg_32:%vreg455,%vreg860
9920B		%vreg35<def> = COPY %vreg859; VReg_64:%vreg35,%vreg859
9936B		%vreg34<def> = COPY %vreg858; VReg_64:%vreg34,%vreg858
9952B		%vreg33<def> = COPY %vreg857; SReg_64:%vreg33,%vreg857
9968B		%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
9984B		%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
10000B		%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
10016B		%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
10032B		%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
10048B		%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
10064B		%vreg835<def> = V_ADDC_U32_e32 %vreg834, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg835,%vreg834,%vreg836
10080B		%vreg830:sub0<def,read-undef> = COPY %vreg829; VReg_64:%vreg830 VReg_32:%vreg829
10096B		%vreg830:sub1<def> = COPY %vreg835; VReg_64:%vreg830 VReg_32:%vreg835
10112B		%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
10128B		%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
10144B		%vreg838<def> = V_ADD_I32_e32 %vreg354, %vreg837, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
10160B		%vreg845<def> = COPY %vreg356; VReg_32:%vreg845 SReg_32:%vreg356
10176B		%vreg844<def> = V_ADDC_U32_e32 %vreg843, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg844,%vreg843,%vreg845
10192B		%vreg839:sub0<def,read-undef> = COPY %vreg838; VReg_64:%vreg839 VReg_32:%vreg838
10208B		%vreg839:sub1<def> = COPY %vreg844; VReg_64:%vreg839 VReg_32:%vreg844
10224B		%vreg411:sub0<def,read-undef> = COPY %vreg413; SGPR_64:%vreg411 SGPR_32:%vreg413
10240B		%vreg411:sub1<def> = COPY %vreg412; SGPR_64:%vreg411 SGPR_32:%vreg412
10256B		%vreg366:sub0_sub1<def,read-undef> = COPY %vreg352; SReg_128:%vreg366 SGPR_64:%vreg352
10272B		%vreg366:sub2_sub3<def> = COPY %vreg411; SReg_128:%vreg366 SGPR_64:%vreg411
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
10352B		%vreg458<def> = V_ADD_I32_e32 -1, %vreg455, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg458,%vreg455
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
10384B		%vreg372<def> = SI_IF_BREAK %vreg371, %vreg33, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
10400B		%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
10416B		%vreg833<def> = COPY %vreg830; VReg_64:%vreg833,%vreg830
10432B		%vreg842<def> = COPY %vreg839; VReg_64:%vreg842,%vreg839
10448B		%vreg38<def> = COPY %vreg370; VGPR_32:%vreg38,%vreg370
10464B		%vreg457<def> = COPY %vreg458; VReg_32:%vreg457,%vreg458
10480B		%vreg857<def> = COPY %vreg42; SReg_64:%vreg857,%vreg42
10496B		%vreg858<def> = COPY %vreg833; VReg_64:%vreg858,%vreg833
10512B		%vreg859<def> = COPY %vreg842; VReg_64:%vreg859,%vreg842
10528B		%vreg860<def> = COPY %vreg457; VReg_32:%vreg860,%vreg457
10544B		%vreg861<def> = COPY %vreg38; VGPR_32:%vreg861,%vreg38
10560B		SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg42, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg42
10624B		%vreg856<def> = COPY %vreg38; VGPR_32:%vreg856,%vreg38
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg424<def> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg424,%vreg374,%vreg423
10720B		%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
10736B		%vreg425:sub0<def,read-undef> = COPY %vreg424; VReg_64:%vreg425 VReg_32:%vreg424
10752B		%vreg425:sub1<def> = COPY %vreg437; VReg_64:%vreg425 VReg_32:%vreg437
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10784B		%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
10800B		%vreg429<def> = COPY %vreg428:sub1; VReg_32:%vreg429 VReg_64:%vreg428
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
10848B		%vreg436<def> = V_ADD_I32_e32 %vreg847, %vreg435, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
10864B		%vreg430<def> = V_ADDC_U32_e32 %vreg848, %vreg429, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg430,%vreg848,%vreg429
10880B		%vreg432:sub0<def,read-undef> = COPY %vreg436; VReg_64:%vreg432 VReg_32:%vreg436
10896B		%vreg432:sub1<def> = COPY %vreg430; VReg_64:%vreg432 VReg_32:%vreg430
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg32, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg32,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
10992B		%vreg45<def> = COPY %vreg432; VReg_64:%vreg45,%vreg432
11008B		%vreg393<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11056B		%vreg395<def> = COPY %vreg393; SReg_64:%vreg395,%vreg393
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
11136B		%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
11152B		%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
11168B		%vreg415:sub0<def,read-undef> = COPY %vreg417; SGPR_64:%vreg415 SGPR_32:%vreg417
11184B		%vreg415:sub1<def> = COPY %vreg416; SGPR_64:%vreg415 SGPR_32:%vreg416
11200B		%vreg396:sub0_sub1<def,read-undef> = COPY %vreg414; SReg_128:%vreg396 SGPR_64:%vreg414
11216B		%vreg396:sub2_sub3<def> = COPY %vreg415; SReg_128:%vreg396 SGPR_64:%vreg415
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11296B		%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
11312B		%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
11328B		%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
11344B		%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
11360B		%vreg419:sub0<def,read-undef> = COPY %vreg421; SGPR_64:%vreg419 SGPR_32:%vreg421
11376B		%vreg419:sub1<def> = COPY %vreg420; SGPR_64:%vreg419 SGPR_32:%vreg420
11392B		%vreg394:sub0_sub1<def,read-undef> = COPY %vreg418; SReg_128:%vreg394 SGPR_64:%vreg418
11408B		%vreg394:sub2_sub3<def> = COPY %vreg419; SReg_128:%vreg394 SGPR_64:%vreg419
11424B		BUFFER_STORE_DWORD %vreg44, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Simple Register Coalescing ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg60<def> = COPY %SGPR2; SReg_32:%vreg60
32B		%vreg59<def> = COPY %VGPR0; VReg_32:%vreg59
48B		%vreg58<def> = COPY %SGPR3; SReg_32:%vreg58
64B		%vreg57<def> = COPY %VGPR1; VReg_32:%vreg57
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg60; VGPR_32:%vreg61 SReg_32:%vreg60
112B		%vreg62<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg62 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg62, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg62 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg59, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg59
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg58; VGPR_32:%vreg69 SReg_32:%vreg58
224B		%vreg70<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg70 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg70, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg70 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg57, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg57
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg79<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg79 SReg_64:%vreg48
368B		%vreg80<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg80 SReg_64:%vreg48
384B		%vreg81<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64:%vreg81,%vreg48
400B		%vreg82<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg82 SReg_64:%vreg48
416B		%vreg83<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64:%vreg83,%vreg48
432B		%vreg84<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg84 SReg_64:%vreg48
448B		%vreg85<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64:%vreg85,%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
512B		%vreg442<def> = COPY %vreg57; VReg_32:%vreg442,%vreg57
528B		%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
544B		%vreg445<def> = COPY %vreg59; VReg_32:%vreg445,%vreg59
560B		%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
576B		%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
592B		%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
608B		%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
624B		%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
640B		%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
656B		%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
672B		%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9,%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg90<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg90
736B		%vreg448<def> = COPY %vreg90; VReg_32:%vreg448,%vreg90
752B		%vreg91<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg91
768B		%vreg87<def> = COPY %vreg91; VGPR_32:%vreg87,%vreg91
784B		%vreg450<def> = COPY %vreg448; VReg_32:%vreg450,%vreg448
800B		%vreg849<def> = COPY %vreg87; VGPR_32:%vreg849,%vreg87
816B		%vreg850<def> = COPY %vreg450; VReg_32:%vreg850,%vreg450
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SReg_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg101<def> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg101 SReg_32:%vreg50 VGPR_32:%vreg443
944B		%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg101, %EXEC<imp-use>; VReg_32:%vreg497,%vreg101
960B		%vreg104:sub0<def,read-undef> = COPY %vreg101; VReg_64:%vreg104 VReg_32:%vreg101
976B		%vreg104:sub1<def> = COPY %vreg497; VReg_64:%vreg104 VReg_32:%vreg497
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1008B		%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
1024B		%vreg500<def> = COPY %vreg499:sub1; VReg_32:%vreg500 VReg_64:%vreg499
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 VSrc_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 VSrc_64_with_sub0:%vreg49
1072B		%vreg515<def> = V_ADD_I32_e32 %vreg516, %vreg514, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516,%vreg514
1088B		%vreg501<def> = V_ADDC_U32_e32 %vreg500, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg501,%vreg500,%vreg517
1104B		%vreg503:sub0<def,read-undef> = COPY %vreg515; VReg_64:%vreg503 VReg_32:%vreg515
1120B		%vreg503:sub1<def> = COPY %vreg501; VReg_64:%vreg503 VReg_32:%vreg501
1136B		%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
1152B		%vreg506<def> = COPY %vreg503:sub1; VReg_32:%vreg506 VReg_64:%vreg503
1168B		%vreg116<def> = S_MOV_B64 32; SReg_64_with_sub0:%vreg116
1184B		%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
1200B		%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
1216B		%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg512, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513,%vreg512 SReg_32:%vreg117
1232B		%vreg508<def> = COPY %vreg118; VReg_32:%vreg508 SReg_32:%vreg118
1248B		%vreg507<def> = V_ADDC_U32_e32 %vreg506, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg507,%vreg506,%vreg508
1264B		%vreg509:sub0<def,read-undef> = COPY %vreg513; VReg_64:%vreg509 VReg_32:%vreg513
1280B		%vreg509:sub1<def> = COPY %vreg507; VReg_64:%vreg509 VReg_32:%vreg507
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SReg_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg127<def> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg127 SReg_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg127, %EXEC<imp-use>; VReg_32:%vreg520,%vreg127
1376B		%vreg130:sub0<def,read-undef> = COPY %vreg127; VReg_64:%vreg130 VReg_32:%vreg127
1392B		%vreg130:sub1<def> = COPY %vreg520; VReg_64:%vreg130 VReg_32:%vreg520
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1424B		%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
1440B		%vreg523<def> = COPY %vreg522:sub1; VReg_32:%vreg523 VReg_64:%vreg522
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 VSrc_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 VSrc_64_with_sub0:%vreg51
1488B		%vreg538<def> = V_ADD_I32_e32 %vreg539, %vreg537, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539,%vreg537
1504B		%vreg524<def> = V_ADDC_U32_e32 %vreg523, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg524,%vreg523,%vreg540
1520B		%vreg526:sub0<def,read-undef> = COPY %vreg538; VReg_64:%vreg526 VReg_32:%vreg538
1536B		%vreg526:sub1<def> = COPY %vreg524; VReg_64:%vreg526 VReg_32:%vreg524
1552B		%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
1568B		%vreg529<def> = COPY %vreg526:sub1; VReg_32:%vreg529 VReg_64:%vreg526
1584B		%vreg536<def> = V_ADD_I32_e32 %vreg117, %vreg535, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_32:%vreg117
1600B		%vreg531<def> = COPY %vreg118; VReg_32:%vreg531 SReg_32:%vreg118
1616B		%vreg530<def> = V_ADDC_U32_e32 %vreg529, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg530,%vreg529,%vreg531
1632B		%vreg532:sub0<def,read-undef> = COPY %vreg536; VReg_64:%vreg532 VReg_32:%vreg536
1648B		%vreg532:sub1<def> = COPY %vreg530; VReg_64:%vreg532 VReg_32:%vreg530
1664B		%vreg145<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg145
1680B		%vreg95<def> = COPY %vreg145; VGPR_32:%vreg95,%vreg145
1696B		%vreg146<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg146
1712B		%vreg541<def> = COPY %vreg146; VReg_32:%vreg541,%vreg146
1728B		%vreg147<def> = S_MOV_B64 0; SGPR_64:%vreg147
1744B		%vreg93<def> = COPY %vreg147; SGPR_64:%vreg93,%vreg147
1760B		%vreg12<def> = COPY %vreg509; VReg_64:%vreg12,%vreg509
1776B		%vreg11<def> = COPY %vreg532; VReg_64:%vreg11,%vreg532
1792B		%vreg401<def> = S_MOV_B32 0; SGPR_32:%vreg401
1808B		%vreg400<def> = S_MOV_B32 61440; SGPR_32:%vreg400
1824B		%vreg181<def> = S_MOV_B32 -1; SReg_32:%vreg181
1840B		%vreg182<def> = S_MOV_B32 -4; SReg_32:%vreg182
1856B		%vreg194<def> = S_MOV_B32 -8; SReg_32:%vreg194
1872B		%vreg202<def> = S_MOV_B32 -12; SReg_32:%vreg202
1888B		%vreg210<def> = S_MOV_B32 -16; SReg_32:%vreg210
1904B		%vreg218<def> = S_MOV_B32 -20; SReg_32:%vreg218
1920B		%vreg226<def> = S_MOV_B32 -24; SReg_32:%vreg226
1936B		%vreg234<def> = S_MOV_B32 -28; SReg_32:%vreg234
1952B		%vreg242<def> = S_MOV_B32 -32; SReg_32:%vreg242
1968B		%vreg283<def> = S_MOV_B64 64; SReg_64_with_sub0:%vreg283
1984B		%vreg543<def> = COPY %vreg541; VReg_32:%vreg543,%vreg541
2000B		%vreg851<def> = COPY %vreg93; SReg_64:%vreg851 SGPR_64:%vreg93
2016B		%vreg852<def> = COPY %vreg12; VReg_64:%vreg852,%vreg12
2032B		%vreg853<def> = COPY %vreg11; VReg_64:%vreg853,%vreg11
2048B		%vreg854<def> = COPY %vreg543; VReg_32:%vreg854,%vreg543
2064B		%vreg855<def> = COPY %vreg95; VGPR_32:%vreg855,%vreg95
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg31, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg31
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299,%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg451<def> = COPY %vreg13; VReg_32:%vreg451 SReg_32:%vreg13
2176B		%vreg849<def> = COPY %vreg27; VGPR_32:%vreg849,%vreg27
2192B		%vreg850<def> = COPY %vreg451; VReg_32:%vreg850,%vreg451
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SReg_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg453, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg453 VGPR_32:%vreg300
2320B		%vreg856<def> = COPY %vreg20; VGPR_32:%vreg856,%vreg20
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SReg_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg309<def> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg309 SReg_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg309, %EXEC<imp-use>; VReg_32:%vreg548,%vreg309
2464B		%vreg312:sub0<def,read-undef> = COPY %vreg309; VReg_64:%vreg312 VReg_32:%vreg309
2480B		%vreg312:sub1<def> = COPY %vreg548; VReg_64:%vreg312 VReg_32:%vreg548
2496B		%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
2512B		%vreg550<def> = COPY %vreg312:sub1; VReg_32:%vreg550 VReg_64:%vreg312
2528B		%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg453, %EXEC<imp-use>; VReg_32:%vreg494,%vreg453
2544B		%vreg459:sub0<def,read-undef> = COPY %vreg453; VReg_64:%vreg459 VReg_32:%vreg453
2560B		%vreg459:sub1<def> = COPY %vreg494; VReg_64:%vreg459 VReg_32:%vreg494
2576B		%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
2592B		%vreg462<def> = COPY %vreg459:sub1; VReg_32:%vreg462 VReg_64:%vreg459
2608B		%vreg493<def> = V_ADD_I32_e32 %vreg549, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg549,%vreg491
2624B		%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg550, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg477,%vreg462,%vreg550
2640B		%vreg479:sub0<def,read-undef> = COPY %vreg493; VReg_64:%vreg479 VReg_32:%vreg493
2656B		%vreg479:sub1<def> = COPY %vreg477; VReg_64:%vreg479 VReg_32:%vreg477
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2688B		%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
2704B		%vreg483<def> = COPY %vreg482:sub1; VReg_32:%vreg483 VReg_64:%vreg482
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 VSrc_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 VSrc_64_with_sub0:%vreg49
2752B		%vreg490<def> = V_ADD_I32_e32 %vreg551, %vreg489, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551,%vreg489
2768B		%vreg484<def> = V_ADDC_U32_e32 %vreg552, %vreg483, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg484,%vreg552,%vreg483
2784B		%vreg486:sub0<def,read-undef> = COPY %vreg490; VReg_64:%vreg486 VReg_32:%vreg490
2800B		%vreg486:sub1<def> = COPY %vreg484; VReg_64:%vreg486 VReg_32:%vreg484
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SReg_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg335<def> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg335 SReg_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg335, %EXEC<imp-use>; VReg_32:%vreg555,%vreg335
2896B		%vreg338:sub0<def,read-undef> = COPY %vreg335; VReg_64:%vreg338 VReg_32:%vreg335
2912B		%vreg338:sub1<def> = COPY %vreg555; VReg_64:%vreg338 VReg_32:%vreg555
2928B		%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
2944B		%vreg557<def> = COPY %vreg338:sub1; VReg_32:%vreg557 VReg_64:%vreg338
2960B		%vreg492<def> = V_ADD_I32_e32 %vreg556, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556,%vreg491
2976B		%vreg463<def> = V_ADDC_U32_e32 %vreg462, %vreg557, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg463,%vreg462,%vreg557
2992B		%vreg465:sub0<def,read-undef> = COPY %vreg492; VReg_64:%vreg465 VReg_32:%vreg492
3008B		%vreg465:sub1<def> = COPY %vreg463; VReg_64:%vreg465 VReg_32:%vreg463
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3040B		%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
3056B		%vreg469<def> = COPY %vreg468:sub1; VReg_32:%vreg469 VReg_64:%vreg468
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 VSrc_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 VSrc_64_with_sub0:%vreg51
3104B		%vreg476<def> = V_ADD_I32_e32 %vreg558, %vreg475, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558,%vreg475
3120B		%vreg470<def> = V_ADDC_U32_e32 %vreg559, %vreg469, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg470,%vreg559,%vreg469
3136B		%vreg472:sub0<def,read-undef> = COPY %vreg476; VReg_64:%vreg472 VReg_32:%vreg476
3152B		%vreg472:sub1<def> = COPY %vreg470; VReg_64:%vreg472 VReg_32:%vreg470
3168B		%vreg454<def> = V_SUB_I32_e32 %vreg55, %vreg453, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg454,%vreg453 SReg_32:%vreg55
3184B		%vreg352<def> = S_MOV_B64 0; SGPR_64:%vreg352
3200B		%vreg303<def> = COPY %vreg352; SGPR_64:%vreg303,%vreg352
3216B		%vreg19<def> = COPY %vreg486; VReg_64:%vreg19,%vreg486
3232B		%vreg18<def> = COPY %vreg472; VReg_64:%vreg18,%vreg472
3248B		%vreg353<def> = S_MOV_B64 4; SReg_64_with_sub0:%vreg353
3264B		%vreg413<def> = S_MOV_B32 0; SGPR_32:%vreg413
3280B		%vreg412<def> = S_MOV_B32 61440; SGPR_32:%vreg412
3296B		%vreg456<def> = COPY %vreg454; VReg_32:%vreg456,%vreg454
3312B		%vreg857<def> = COPY %vreg303; SReg_64:%vreg857 SGPR_64:%vreg303
3328B		%vreg858<def> = COPY %vreg19; VReg_64:%vreg858,%vreg19
3344B		%vreg859<def> = COPY %vreg18; VReg_64:%vreg859,%vreg18
3360B		%vreg860<def> = COPY %vreg456; VReg_32:%vreg860,%vreg456
3376B		%vreg861<def> = COPY %vreg20; VGPR_32:%vreg861,%vreg20
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3424B		%vreg449<def> = COPY %vreg850; VReg_32:%vreg449,%vreg850
3440B		%vreg20<def> = COPY %vreg849; VGPR_32:%vreg20,%vreg849
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3472B		%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
3488B		%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3520B		%vreg453<def> = COPY %vreg449; VReg_32:%vreg453,%vreg449
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3568B		%vreg26<def> = COPY %vreg855; VGPR_32:%vreg26,%vreg855
3584B		%vreg542<def> = COPY %vreg854; VReg_32:%vreg542,%vreg854
3600B		%vreg24<def> = COPY %vreg853; VReg_64:%vreg24,%vreg853
3616B		%vreg23<def> = COPY %vreg852; VReg_64:%vreg23,%vreg852
3632B		%vreg22<def> = COPY %vreg851; SReg_64:%vreg22,%vreg851
3648B		%vreg399:sub0<def,read-undef> = COPY %vreg401; SGPR_64:%vreg399 SGPR_32:%vreg401
3664B		%vreg399:sub1<def> = COPY %vreg400; SGPR_64:%vreg399 SGPR_32:%vreg400
3680B		%vreg148:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg148 SGPR_64:%vreg147
3696B		%vreg148:sub2_sub3<def> = COPY %vreg399; SReg_128:%vreg148 SGPR_64:%vreg399
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg24
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg23
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg152<def> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VGPR_32:%vreg152,%vreg151,%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg24
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg23
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg156<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VGPR_32:%vreg156,%vreg155,%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg24
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg23
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg160<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VGPR_32:%vreg160,%vreg159,%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg24
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg23
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg164<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VGPR_32:%vreg164,%vreg163,%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg24
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg23
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg168<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VGPR_32:%vreg168,%vreg167,%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg24
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg23
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg172<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VGPR_32:%vreg172,%vreg171,%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg24
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg23
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg176<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VGPR_32:%vreg176,%vreg175,%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg24, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg24
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg23, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg23
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg180<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VGPR_32:%vreg180,%vreg179,%vreg179
4224B		%vreg183:sub0<def,read-undef> = COPY %vreg182; SGPR_64:%vreg183 SReg_32:%vreg182
4240B		%vreg183:sub1<def> = COPY %vreg181; SGPR_64:%vreg183 SReg_32:%vreg181
4256B		%vreg560<def> = COPY %vreg24; VReg_64:%vreg560,%vreg24
4272B		%vreg561<def> = COPY %vreg560; VReg_64:%vreg561,%vreg560
4288B		%vreg564<def> = COPY %vreg399; VReg_64:%vreg564 SGPR_64:%vreg399
4304B		%vreg562:sub0_sub1<def,read-undef> = COPY %vreg561; VReg_128:%vreg562 VReg_64:%vreg561
4320B		%vreg562:sub2_sub3<def> = COPY %vreg564; VReg_128:%vreg562 VReg_64:%vreg564
4336B		%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
4352B		%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
4368B		%vreg678<def> = COPY %vreg677:sub0; VReg_32:%vreg678 VReg_128:%vreg677
4384B		%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
4400B		%vreg680<def> = COPY %vreg679:sub1; VReg_32:%vreg680 VReg_128:%vreg679
4416B		%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
4432B		%vreg682<def> = COPY %vreg681:sub0; VReg_32:%vreg682 VReg_64:%vreg681
4448B		%vreg683<def> = COPY %vreg187; VReg_64:%vreg683,%vreg187
4464B		%vreg684<def> = COPY %vreg683:sub1; VReg_32:%vreg684 VReg_64:%vreg683
4480B		%vreg670<def> = V_ADD_I32_e32 %vreg678, %vreg682, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg678,%vreg682
4496B		%vreg671<def> = V_ADDC_U32_e32 %vreg680, %vreg684, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg671,%vreg680,%vreg684
4512B		%vreg672:sub0<def,read-undef> = COPY %vreg670; VReg_64:%vreg672 VReg_32:%vreg670
4528B		%vreg672:sub1<def> = COPY %vreg671; VReg_64:%vreg672 VReg_32:%vreg671
4544B		%vreg676:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg676 SGPR_64:%vreg147
4560B		%vreg676:sub2<def> = COPY %vreg401; SReg_128:%vreg676 SGPR_32:%vreg401
4576B		%vreg676:sub3<def> = COPY %vreg400; SReg_128:%vreg676 SGPR_32:%vreg400
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4608B		%vreg685<def> = COPY %vreg23; VReg_64:%vreg685,%vreg23
4624B		%vreg686<def> = COPY %vreg685; VReg_64:%vreg686,%vreg685
4640B		%vreg689<def> = COPY %vreg399; VReg_64:%vreg689 SGPR_64:%vreg399
4656B		%vreg687:sub0_sub1<def,read-undef> = COPY %vreg686; VReg_128:%vreg687 VReg_64:%vreg686
4672B		%vreg687:sub2_sub3<def> = COPY %vreg689; VReg_128:%vreg687 VReg_64:%vreg689
4688B		%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
4704B		%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
4720B		%vreg803<def> = COPY %vreg802:sub0; VReg_32:%vreg803 VReg_128:%vreg802
4736B		%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
4752B		%vreg805<def> = COPY %vreg804:sub1; VReg_32:%vreg805 VReg_128:%vreg804
4768B		%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
4784B		%vreg807<def> = COPY %vreg806:sub0; VReg_32:%vreg807 VReg_64:%vreg806
4800B		%vreg808<def> = COPY %vreg191; VReg_64:%vreg808,%vreg191
4816B		%vreg809<def> = COPY %vreg808:sub1; VReg_32:%vreg809 VReg_64:%vreg808
4832B		%vreg795<def> = V_ADD_I32_e32 %vreg803, %vreg807, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg803,%vreg807
4848B		%vreg796<def> = V_ADDC_U32_e32 %vreg805, %vreg809, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg796,%vreg805,%vreg809
4864B		%vreg797:sub0<def,read-undef> = COPY %vreg795; VReg_64:%vreg797 VReg_32:%vreg795
4880B		%vreg797:sub1<def> = COPY %vreg796; VReg_64:%vreg797 VReg_32:%vreg796
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg193<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VGPR_32:%vreg193,%vreg192,%vreg192
4944B		%vreg195:sub0<def,read-undef> = COPY %vreg194; SGPR_64:%vreg195 SReg_32:%vreg194
4960B		%vreg195:sub1<def> = COPY %vreg181; SGPR_64:%vreg195 SReg_32:%vreg181
4976B		%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
4992B		%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
5008B		%vreg663<def> = COPY %vreg662:sub0; VReg_32:%vreg663 VReg_128:%vreg662
5024B		%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
5040B		%vreg665<def> = COPY %vreg664:sub1; VReg_32:%vreg665 VReg_128:%vreg664
5056B		%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
5072B		%vreg667<def> = COPY %vreg666:sub0; VReg_32:%vreg667 VReg_64:%vreg666
5088B		%vreg668<def> = COPY %vreg197; VReg_64:%vreg668,%vreg197
5104B		%vreg669<def> = COPY %vreg668:sub1; VReg_32:%vreg669 VReg_64:%vreg668
5120B		%vreg655<def> = V_ADD_I32_e32 %vreg663, %vreg667, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg663,%vreg667
5136B		%vreg656<def> = V_ADDC_U32_e32 %vreg665, %vreg669, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg656,%vreg665,%vreg669
5152B		%vreg657:sub0<def,read-undef> = COPY %vreg655; VReg_64:%vreg657 VReg_32:%vreg655
5168B		%vreg657:sub1<def> = COPY %vreg656; VReg_64:%vreg657 VReg_32:%vreg656
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
5216B		%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
5232B		%vreg788<def> = COPY %vreg787:sub0; VReg_32:%vreg788 VReg_128:%vreg787
5248B		%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
5264B		%vreg790<def> = COPY %vreg789:sub1; VReg_32:%vreg790 VReg_128:%vreg789
5280B		%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
5296B		%vreg792<def> = COPY %vreg791:sub0; VReg_32:%vreg792 VReg_64:%vreg791
5312B		%vreg793<def> = COPY %vreg199; VReg_64:%vreg793,%vreg199
5328B		%vreg794<def> = COPY %vreg793:sub1; VReg_32:%vreg794 VReg_64:%vreg793
5344B		%vreg780<def> = V_ADD_I32_e32 %vreg788, %vreg792, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg788,%vreg792
5360B		%vreg781<def> = V_ADDC_U32_e32 %vreg790, %vreg794, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg781,%vreg790,%vreg794
5376B		%vreg782:sub0<def,read-undef> = COPY %vreg780; VReg_64:%vreg782 VReg_32:%vreg780
5392B		%vreg782:sub1<def> = COPY %vreg781; VReg_64:%vreg782 VReg_32:%vreg781
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg201<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VGPR_32:%vreg201,%vreg200,%vreg200
5456B		%vreg203:sub0<def,read-undef> = COPY %vreg202; SGPR_64:%vreg203 SReg_32:%vreg202
5472B		%vreg203:sub1<def> = COPY %vreg181; SGPR_64:%vreg203 SReg_32:%vreg181
5488B		%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
5504B		%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
5520B		%vreg648<def> = COPY %vreg647:sub0; VReg_32:%vreg648 VReg_128:%vreg647
5536B		%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
5552B		%vreg650<def> = COPY %vreg649:sub1; VReg_32:%vreg650 VReg_128:%vreg649
5568B		%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
5584B		%vreg652<def> = COPY %vreg651:sub0; VReg_32:%vreg652 VReg_64:%vreg651
5600B		%vreg653<def> = COPY %vreg205; VReg_64:%vreg653,%vreg205
5616B		%vreg654<def> = COPY %vreg653:sub1; VReg_32:%vreg654 VReg_64:%vreg653
5632B		%vreg640<def> = V_ADD_I32_e32 %vreg648, %vreg652, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg648,%vreg652
5648B		%vreg641<def> = V_ADDC_U32_e32 %vreg650, %vreg654, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg641,%vreg650,%vreg654
5664B		%vreg642:sub0<def,read-undef> = COPY %vreg640; VReg_64:%vreg642 VReg_32:%vreg640
5680B		%vreg642:sub1<def> = COPY %vreg641; VReg_64:%vreg642 VReg_32:%vreg641
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
5728B		%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
5744B		%vreg773<def> = COPY %vreg772:sub0; VReg_32:%vreg773 VReg_128:%vreg772
5760B		%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
5776B		%vreg775<def> = COPY %vreg774:sub1; VReg_32:%vreg775 VReg_128:%vreg774
5792B		%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
5808B		%vreg777<def> = COPY %vreg776:sub0; VReg_32:%vreg777 VReg_64:%vreg776
5824B		%vreg778<def> = COPY %vreg207; VReg_64:%vreg778,%vreg207
5840B		%vreg779<def> = COPY %vreg778:sub1; VReg_32:%vreg779 VReg_64:%vreg778
5856B		%vreg765<def> = V_ADD_I32_e32 %vreg773, %vreg777, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg773,%vreg777
5872B		%vreg766<def> = V_ADDC_U32_e32 %vreg775, %vreg779, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg766,%vreg775,%vreg779
5888B		%vreg767:sub0<def,read-undef> = COPY %vreg765; VReg_64:%vreg767 VReg_32:%vreg765
5904B		%vreg767:sub1<def> = COPY %vreg766; VReg_64:%vreg767 VReg_32:%vreg766
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg209<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VGPR_32:%vreg209,%vreg208,%vreg208
5968B		%vreg211:sub0<def,read-undef> = COPY %vreg210; SGPR_64:%vreg211 SReg_32:%vreg210
5984B		%vreg211:sub1<def> = COPY %vreg181; SGPR_64:%vreg211 SReg_32:%vreg181
6000B		%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
6016B		%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
6032B		%vreg633<def> = COPY %vreg632:sub0; VReg_32:%vreg633 VReg_128:%vreg632
6048B		%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
6064B		%vreg635<def> = COPY %vreg634:sub1; VReg_32:%vreg635 VReg_128:%vreg634
6080B		%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
6096B		%vreg637<def> = COPY %vreg636:sub0; VReg_32:%vreg637 VReg_64:%vreg636
6112B		%vreg638<def> = COPY %vreg213; VReg_64:%vreg638,%vreg213
6128B		%vreg639<def> = COPY %vreg638:sub1; VReg_32:%vreg639 VReg_64:%vreg638
6144B		%vreg625<def> = V_ADD_I32_e32 %vreg633, %vreg637, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg633,%vreg637
6160B		%vreg626<def> = V_ADDC_U32_e32 %vreg635, %vreg639, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg626,%vreg635,%vreg639
6176B		%vreg627:sub0<def,read-undef> = COPY %vreg625; VReg_64:%vreg627 VReg_32:%vreg625
6192B		%vreg627:sub1<def> = COPY %vreg626; VReg_64:%vreg627 VReg_32:%vreg626
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
6240B		%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
6256B		%vreg758<def> = COPY %vreg757:sub0; VReg_32:%vreg758 VReg_128:%vreg757
6272B		%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
6288B		%vreg760<def> = COPY %vreg759:sub1; VReg_32:%vreg760 VReg_128:%vreg759
6304B		%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
6320B		%vreg762<def> = COPY %vreg761:sub0; VReg_32:%vreg762 VReg_64:%vreg761
6336B		%vreg763<def> = COPY %vreg215; VReg_64:%vreg763,%vreg215
6352B		%vreg764<def> = COPY %vreg763:sub1; VReg_32:%vreg764 VReg_64:%vreg763
6368B		%vreg750<def> = V_ADD_I32_e32 %vreg758, %vreg762, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg758,%vreg762
6384B		%vreg751<def> = V_ADDC_U32_e32 %vreg760, %vreg764, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg751,%vreg760,%vreg764
6400B		%vreg752:sub0<def,read-undef> = COPY %vreg750; VReg_64:%vreg752 VReg_32:%vreg750
6416B		%vreg752:sub1<def> = COPY %vreg751; VReg_64:%vreg752 VReg_32:%vreg751
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg217<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VGPR_32:%vreg217,%vreg216,%vreg216
6480B		%vreg219:sub0<def,read-undef> = COPY %vreg218; SGPR_64:%vreg219 SReg_32:%vreg218
6496B		%vreg219:sub1<def> = COPY %vreg181; SGPR_64:%vreg219 SReg_32:%vreg181
6512B		%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
6528B		%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
6544B		%vreg618<def> = COPY %vreg617:sub0; VReg_32:%vreg618 VReg_128:%vreg617
6560B		%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
6576B		%vreg620<def> = COPY %vreg619:sub1; VReg_32:%vreg620 VReg_128:%vreg619
6592B		%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
6608B		%vreg622<def> = COPY %vreg621:sub0; VReg_32:%vreg622 VReg_64:%vreg621
6624B		%vreg623<def> = COPY %vreg221; VReg_64:%vreg623,%vreg221
6640B		%vreg624<def> = COPY %vreg623:sub1; VReg_32:%vreg624 VReg_64:%vreg623
6656B		%vreg610<def> = V_ADD_I32_e32 %vreg618, %vreg622, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg618,%vreg622
6672B		%vreg611<def> = V_ADDC_U32_e32 %vreg620, %vreg624, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg611,%vreg620,%vreg624
6688B		%vreg612:sub0<def,read-undef> = COPY %vreg610; VReg_64:%vreg612 VReg_32:%vreg610
6704B		%vreg612:sub1<def> = COPY %vreg611; VReg_64:%vreg612 VReg_32:%vreg611
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
6752B		%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
6768B		%vreg743<def> = COPY %vreg742:sub0; VReg_32:%vreg743 VReg_128:%vreg742
6784B		%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
6800B		%vreg745<def> = COPY %vreg744:sub1; VReg_32:%vreg745 VReg_128:%vreg744
6816B		%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
6832B		%vreg747<def> = COPY %vreg746:sub0; VReg_32:%vreg747 VReg_64:%vreg746
6848B		%vreg748<def> = COPY %vreg223; VReg_64:%vreg748,%vreg223
6864B		%vreg749<def> = COPY %vreg748:sub1; VReg_32:%vreg749 VReg_64:%vreg748
6880B		%vreg735<def> = V_ADD_I32_e32 %vreg743, %vreg747, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg743,%vreg747
6896B		%vreg736<def> = V_ADDC_U32_e32 %vreg745, %vreg749, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg736,%vreg745,%vreg749
6912B		%vreg737:sub0<def,read-undef> = COPY %vreg735; VReg_64:%vreg737 VReg_32:%vreg735
6928B		%vreg737:sub1<def> = COPY %vreg736; VReg_64:%vreg737 VReg_32:%vreg736
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg225<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VGPR_32:%vreg225,%vreg224,%vreg224
6992B		%vreg227:sub0<def,read-undef> = COPY %vreg226; SGPR_64:%vreg227 SReg_32:%vreg226
7008B		%vreg227:sub1<def> = COPY %vreg181; SGPR_64:%vreg227 SReg_32:%vreg181
7024B		%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
7040B		%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
7056B		%vreg603<def> = COPY %vreg602:sub0; VReg_32:%vreg603 VReg_128:%vreg602
7072B		%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
7088B		%vreg605<def> = COPY %vreg604:sub1; VReg_32:%vreg605 VReg_128:%vreg604
7104B		%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
7120B		%vreg607<def> = COPY %vreg606:sub0; VReg_32:%vreg607 VReg_64:%vreg606
7136B		%vreg608<def> = COPY %vreg229; VReg_64:%vreg608,%vreg229
7152B		%vreg609<def> = COPY %vreg608:sub1; VReg_32:%vreg609 VReg_64:%vreg608
7168B		%vreg595<def> = V_ADD_I32_e32 %vreg603, %vreg607, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg603,%vreg607
7184B		%vreg596<def> = V_ADDC_U32_e32 %vreg605, %vreg609, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg596,%vreg605,%vreg609
7200B		%vreg597:sub0<def,read-undef> = COPY %vreg595; VReg_64:%vreg597 VReg_32:%vreg595
7216B		%vreg597:sub1<def> = COPY %vreg596; VReg_64:%vreg597 VReg_32:%vreg596
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
7264B		%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
7280B		%vreg728<def> = COPY %vreg727:sub0; VReg_32:%vreg728 VReg_128:%vreg727
7296B		%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
7312B		%vreg730<def> = COPY %vreg729:sub1; VReg_32:%vreg730 VReg_128:%vreg729
7328B		%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
7344B		%vreg732<def> = COPY %vreg731:sub0; VReg_32:%vreg732 VReg_64:%vreg731
7360B		%vreg733<def> = COPY %vreg231; VReg_64:%vreg733,%vreg231
7376B		%vreg734<def> = COPY %vreg733:sub1; VReg_32:%vreg734 VReg_64:%vreg733
7392B		%vreg720<def> = V_ADD_I32_e32 %vreg728, %vreg732, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg728,%vreg732
7408B		%vreg721<def> = V_ADDC_U32_e32 %vreg730, %vreg734, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg721,%vreg730,%vreg734
7424B		%vreg722:sub0<def,read-undef> = COPY %vreg720; VReg_64:%vreg722 VReg_32:%vreg720
7440B		%vreg722:sub1<def> = COPY %vreg721; VReg_64:%vreg722 VReg_32:%vreg721
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg233<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VGPR_32:%vreg233,%vreg232,%vreg232
7504B		%vreg235:sub0<def,read-undef> = COPY %vreg234; SGPR_64:%vreg235 SReg_32:%vreg234
7520B		%vreg235:sub1<def> = COPY %vreg181; SGPR_64:%vreg235 SReg_32:%vreg181
7536B		%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
7552B		%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
7568B		%vreg588<def> = COPY %vreg587:sub0; VReg_32:%vreg588 VReg_128:%vreg587
7584B		%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
7600B		%vreg590<def> = COPY %vreg589:sub1; VReg_32:%vreg590 VReg_128:%vreg589
7616B		%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
7632B		%vreg592<def> = COPY %vreg591:sub0; VReg_32:%vreg592 VReg_64:%vreg591
7648B		%vreg593<def> = COPY %vreg237; VReg_64:%vreg593,%vreg237
7664B		%vreg594<def> = COPY %vreg593:sub1; VReg_32:%vreg594 VReg_64:%vreg593
7680B		%vreg580<def> = V_ADD_I32_e32 %vreg588, %vreg592, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg588,%vreg592
7696B		%vreg581<def> = V_ADDC_U32_e32 %vreg590, %vreg594, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg581,%vreg590,%vreg594
7712B		%vreg582:sub0<def,read-undef> = COPY %vreg580; VReg_64:%vreg582 VReg_32:%vreg580
7728B		%vreg582:sub1<def> = COPY %vreg581; VReg_64:%vreg582 VReg_32:%vreg581
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
7776B		%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
7792B		%vreg713<def> = COPY %vreg712:sub0; VReg_32:%vreg713 VReg_128:%vreg712
7808B		%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
7824B		%vreg715<def> = COPY %vreg714:sub1; VReg_32:%vreg715 VReg_128:%vreg714
7840B		%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
7856B		%vreg717<def> = COPY %vreg716:sub0; VReg_32:%vreg717 VReg_64:%vreg716
7872B		%vreg718<def> = COPY %vreg239; VReg_64:%vreg718,%vreg239
7888B		%vreg719<def> = COPY %vreg718:sub1; VReg_32:%vreg719 VReg_64:%vreg718
7904B		%vreg705<def> = V_ADD_I32_e32 %vreg713, %vreg717, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg713,%vreg717
7920B		%vreg706<def> = V_ADDC_U32_e32 %vreg715, %vreg719, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg706,%vreg715,%vreg719
7936B		%vreg707:sub0<def,read-undef> = COPY %vreg705; VReg_64:%vreg707 VReg_32:%vreg705
7952B		%vreg707:sub1<def> = COPY %vreg706; VReg_64:%vreg707 VReg_32:%vreg706
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg241<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VGPR_32:%vreg241,%vreg240,%vreg240
8016B		%vreg243:sub0<def,read-undef> = COPY %vreg242; SGPR_64:%vreg243 SReg_32:%vreg242
8032B		%vreg243:sub1<def> = COPY %vreg181; SGPR_64:%vreg243 SReg_32:%vreg181
8048B		%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
8064B		%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
8080B		%vreg573<def> = COPY %vreg572:sub0; VReg_32:%vreg573 VReg_128:%vreg572
8096B		%vreg574<def> = COPY %vreg562; VReg_128:%vreg574,%vreg562
8112B		%vreg575<def> = COPY %vreg574:sub1; VReg_32:%vreg575 VReg_128:%vreg574
8128B		%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
8144B		%vreg577<def> = COPY %vreg576:sub0; VReg_32:%vreg577 VReg_64:%vreg576
8160B		%vreg578<def> = COPY %vreg245; VReg_64:%vreg578,%vreg245
8176B		%vreg579<def> = COPY %vreg578:sub1; VReg_32:%vreg579 VReg_64:%vreg578
8192B		%vreg565<def> = V_ADD_I32_e32 %vreg573, %vreg577, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg573,%vreg577
8208B		%vreg566<def> = V_ADDC_U32_e32 %vreg575, %vreg579, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg566,%vreg575,%vreg579
8224B		%vreg567:sub0<def,read-undef> = COPY %vreg565; VReg_64:%vreg567 VReg_32:%vreg565
8240B		%vreg567:sub1<def> = COPY %vreg566; VReg_64:%vreg567 VReg_32:%vreg566
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
8288B		%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
8304B		%vreg698<def> = COPY %vreg697:sub0; VReg_32:%vreg698 VReg_128:%vreg697
8320B		%vreg699<def> = COPY %vreg687; VReg_128:%vreg699,%vreg687
8336B		%vreg700<def> = COPY %vreg699:sub1; VReg_32:%vreg700 VReg_128:%vreg699
8352B		%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
8368B		%vreg702<def> = COPY %vreg701:sub0; VReg_32:%vreg702 VReg_64:%vreg701
8384B		%vreg703<def> = COPY %vreg247; VReg_64:%vreg703,%vreg247
8400B		%vreg704<def> = COPY %vreg703:sub1; VReg_32:%vreg704 VReg_64:%vreg703
8416B		%vreg690<def> = V_ADD_I32_e32 %vreg698, %vreg702, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg698,%vreg702
8432B		%vreg691<def> = V_ADDC_U32_e32 %vreg700, %vreg704, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg691,%vreg700,%vreg704
8448B		%vreg692:sub0<def,read-undef> = COPY %vreg690; VReg_64:%vreg692 VReg_32:%vreg690
8464B		%vreg692:sub1<def> = COPY %vreg691; VReg_64:%vreg692 VReg_32:%vreg691
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg249<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VGPR_32:%vreg249,%vreg248,%vreg248
8528B		%vreg250:sub0<def,read-undef> = COPY %vreg249; VReg_512:%vreg250 VGPR_32:%vreg249
8544B		%vreg250:sub1<def> = COPY %vreg241; VReg_512:%vreg250 VGPR_32:%vreg241
8560B		%vreg250:sub2<def> = COPY %vreg233; VReg_512:%vreg250 VGPR_32:%vreg233
8576B		%vreg250:sub3<def> = COPY %vreg225; VReg_512:%vreg250 VGPR_32:%vreg225
8592B		%vreg250:sub4<def> = COPY %vreg217; VReg_512:%vreg250 VGPR_32:%vreg217
8608B		%vreg250:sub5<def> = COPY %vreg209; VReg_512:%vreg250 VGPR_32:%vreg209
8624B		%vreg250:sub6<def> = COPY %vreg201; VReg_512:%vreg250 VGPR_32:%vreg201
8640B		%vreg250:sub7<def> = COPY %vreg193; VReg_512:%vreg250 VGPR_32:%vreg193
8656B		%vreg250:sub8<def> = COPY %vreg180; VReg_512:%vreg250 VGPR_32:%vreg180
8672B		%vreg250:sub9<def> = COPY %vreg176; VReg_512:%vreg250 VGPR_32:%vreg176
8688B		%vreg250:sub10<def> = COPY %vreg172; VReg_512:%vreg250 VGPR_32:%vreg172
8704B		%vreg250:sub11<def> = COPY %vreg168; VReg_512:%vreg250 VGPR_32:%vreg168
8720B		%vreg250:sub12<def> = COPY %vreg164; VReg_512:%vreg250 VGPR_32:%vreg164
8736B		%vreg250:sub13<def> = COPY %vreg160; VReg_512:%vreg250 VGPR_32:%vreg160
8752B		%vreg250:sub14<def> = COPY %vreg156; VReg_512:%vreg250 VGPR_32:%vreg156
8768B		%vreg250:sub15<def> = COPY %vreg152; VReg_512:%vreg250 VGPR_32:%vreg152
8784B		%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
8800B		%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg252, %vreg251, %EXEC<imp-use>; VGPR_32:%vreg253,%vreg251 VSrc_32:%vreg252
8832B		%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg254, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VSrc_32:%vreg254
8864B		%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg256, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VSrc_32:%vreg256
8896B		%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg258, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VSrc_32:%vreg258
8928B		%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg260, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VSrc_32:%vreg260
8960B		%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg262, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VSrc_32:%vreg262
8992B		%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg264, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VSrc_32:%vreg264
9024B		%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg266, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VSrc_32:%vreg266
9056B		%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg268, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VSrc_32:%vreg268
9088B		%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg270, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VSrc_32:%vreg270
9120B		%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg272, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VSrc_32:%vreg272
9152B		%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg274, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VSrc_32:%vreg274
9184B		%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg276, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VSrc_32:%vreg276
9216B		%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg278, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VSrc_32:%vreg278
9248B		%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg280, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VSrc_32:%vreg280
9280B		%vreg282<def> = V_ADD_F32_e32 %vreg26, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg26,%vreg281
9296B		%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
9312B		%vreg810<def> = COPY %vreg23:sub0; VReg_32:%vreg810 VReg_64:%vreg23
9328B		%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
9344B		%vreg816<def> = COPY %vreg23:sub1; VReg_32:%vreg816 VReg_64:%vreg23
9360B		%vreg811<def> = V_ADD_I32_e32 %vreg284, %vreg810, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_32:%vreg284
9376B		%vreg818<def> = COPY %vreg286; VReg_32:%vreg818 SReg_32:%vreg286
9392B		%vreg817<def> = V_ADDC_U32_e32 %vreg816, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg817,%vreg816,%vreg818
9408B		%vreg812:sub0<def,read-undef> = COPY %vreg811; VReg_64:%vreg812 VReg_32:%vreg811
9424B		%vreg812:sub1<def> = COPY %vreg817; VReg_64:%vreg812 VReg_32:%vreg817
9440B		%vreg819<def> = COPY %vreg24:sub0; VReg_32:%vreg819 VReg_64:%vreg24
9456B		%vreg825<def> = COPY %vreg24:sub1; VReg_32:%vreg825 VReg_64:%vreg24
9472B		%vreg820<def> = V_ADD_I32_e32 %vreg284, %vreg819, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_32:%vreg284
9488B		%vreg827<def> = COPY %vreg286; VReg_32:%vreg827 SReg_32:%vreg286
9504B		%vreg826<def> = V_ADDC_U32_e32 %vreg825, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg826,%vreg825,%vreg827
9520B		%vreg821:sub0<def,read-undef> = COPY %vreg820; VReg_64:%vreg821 VReg_32:%vreg820
9536B		%vreg821:sub1<def> = COPY %vreg826; VReg_64:%vreg821 VReg_32:%vreg826
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg545<def> = V_ADD_I32_e32 16, %vreg542, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg545,%vreg542
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg545, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg545 VGPR_32:%vreg296
9600B		%vreg298<def> = SI_IF_BREAK %vreg297, %vreg22, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg22
9616B		%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
9632B		%vreg815<def> = COPY %vreg812; VReg_64:%vreg815,%vreg812
9648B		%vreg824<def> = COPY %vreg821; VReg_64:%vreg824,%vreg821
9664B		%vreg27<def> = COPY %vreg282; VGPR_32:%vreg27,%vreg282
9680B		%vreg544<def> = COPY %vreg545; VReg_32:%vreg544,%vreg545
9696B		%vreg851<def> = COPY %vreg31; SReg_64:%vreg851,%vreg31
9712B		%vreg852<def> = COPY %vreg815; VReg_64:%vreg852,%vreg815
9728B		%vreg853<def> = COPY %vreg824; VReg_64:%vreg853,%vreg824
9744B		%vreg854<def> = COPY %vreg544; VReg_32:%vreg854,%vreg544
9760B		%vreg855<def> = COPY %vreg27; VGPR_32:%vreg855,%vreg27
9776B		SI_LOOP %vreg298, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9824B		%vreg32<def> = COPY %vreg856; VGPR_32:%vreg32,%vreg856
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
9888B		%vreg37<def> = COPY %vreg861; VGPR_32:%vreg37,%vreg861
9904B		%vreg455<def> = COPY %vreg860; VReg_32:%vreg455,%vreg860
9920B		%vreg35<def> = COPY %vreg859; VReg_64:%vreg35,%vreg859
9936B		%vreg34<def> = COPY %vreg858; VReg_64:%vreg34,%vreg858
9952B		%vreg33<def> = COPY %vreg857; SReg_64:%vreg33,%vreg857
9968B		%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
9984B		%vreg828<def> = COPY %vreg34:sub0; VReg_32:%vreg828 VReg_64:%vreg34
10000B		%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
10016B		%vreg834<def> = COPY %vreg34:sub1; VReg_32:%vreg834 VReg_64:%vreg34
10032B		%vreg829<def> = V_ADD_I32_e32 %vreg354, %vreg828, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_32:%vreg354
10048B		%vreg836<def> = COPY %vreg356; VReg_32:%vreg836 SReg_32:%vreg356
10064B		%vreg835<def> = V_ADDC_U32_e32 %vreg834, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg835,%vreg834,%vreg836
10080B		%vreg830:sub0<def,read-undef> = COPY %vreg829; VReg_64:%vreg830 VReg_32:%vreg829
10096B		%vreg830:sub1<def> = COPY %vreg835; VReg_64:%vreg830 VReg_32:%vreg835
10112B		%vreg837<def> = COPY %vreg35:sub0; VReg_32:%vreg837 VReg_64:%vreg35
10128B		%vreg843<def> = COPY %vreg35:sub1; VReg_32:%vreg843 VReg_64:%vreg35
10144B		%vreg838<def> = V_ADD_I32_e32 %vreg354, %vreg837, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_32:%vreg354
10160B		%vreg845<def> = COPY %vreg356; VReg_32:%vreg845 SReg_32:%vreg356
10176B		%vreg844<def> = V_ADDC_U32_e32 %vreg843, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg844,%vreg843,%vreg845
10192B		%vreg839:sub0<def,read-undef> = COPY %vreg838; VReg_64:%vreg839 VReg_32:%vreg838
10208B		%vreg839:sub1<def> = COPY %vreg844; VReg_64:%vreg839 VReg_32:%vreg844
10224B		%vreg411:sub0<def,read-undef> = COPY %vreg413; SGPR_64:%vreg411 SGPR_32:%vreg413
10240B		%vreg411:sub1<def> = COPY %vreg412; SGPR_64:%vreg411 SGPR_32:%vreg412
10256B		%vreg366:sub0_sub1<def,read-undef> = COPY %vreg352; SReg_128:%vreg366 SGPR_64:%vreg352
10272B		%vreg366:sub2_sub3<def> = COPY %vreg411; SReg_128:%vreg366 SGPR_64:%vreg411
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg35, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg35
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg34, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg34
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg37, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg37
10352B		%vreg458<def> = V_ADD_I32_e32 -1, %vreg455, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg458,%vreg455
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg458, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg458
10384B		%vreg372<def> = SI_IF_BREAK %vreg371, %vreg33, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg33
10400B		%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
10416B		%vreg833<def> = COPY %vreg830; VReg_64:%vreg833,%vreg830
10432B		%vreg842<def> = COPY %vreg839; VReg_64:%vreg842,%vreg839
10448B		%vreg38<def> = COPY %vreg370; VGPR_32:%vreg38,%vreg370
10464B		%vreg457<def> = COPY %vreg458; VReg_32:%vreg457,%vreg458
10480B		%vreg857<def> = COPY %vreg42; SReg_64:%vreg857,%vreg42
10496B		%vreg858<def> = COPY %vreg833; VReg_64:%vreg858,%vreg833
10512B		%vreg859<def> = COPY %vreg842; VReg_64:%vreg859,%vreg842
10528B		%vreg860<def> = COPY %vreg457; VReg_32:%vreg860,%vreg457
10544B		%vreg861<def> = COPY %vreg38; VGPR_32:%vreg861,%vreg38
10560B		SI_LOOP %vreg372, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg42, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg42
10624B		%vreg856<def> = COPY %vreg38; VGPR_32:%vreg856,%vreg38
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SReg_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg424<def> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg424,%vreg374,%vreg423
10720B		%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg424, %EXEC<imp-use>; VReg_32:%vreg437,%vreg424
10736B		%vreg425:sub0<def,read-undef> = COPY %vreg424; VReg_64:%vreg425 VReg_32:%vreg424
10752B		%vreg425:sub1<def> = COPY %vreg437; VReg_64:%vreg425 VReg_32:%vreg437
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10784B		%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
10800B		%vreg429<def> = COPY %vreg428:sub1; VReg_32:%vreg429 VReg_64:%vreg428
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 VSrc_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 VSrc_64_with_sub0:%vreg53
10848B		%vreg436<def> = V_ADD_I32_e32 %vreg847, %vreg435, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847,%vreg435
10864B		%vreg430<def> = V_ADDC_U32_e32 %vreg848, %vreg429, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg430,%vreg848,%vreg429
10880B		%vreg432:sub0<def,read-undef> = COPY %vreg436; VReg_64:%vreg432 VReg_32:%vreg436
10896B		%vreg432:sub1<def> = COPY %vreg430; VReg_64:%vreg432 VReg_32:%vreg430
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg32, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg32,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
10992B		%vreg45<def> = COPY %vreg432; VReg_64:%vreg45,%vreg432
11008B		%vreg393<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg393,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11056B		%vreg395<def> = COPY %vreg393; SReg_64:%vreg395,%vreg393
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg414<def> = S_MOV_B64 0; SGPR_64:%vreg414
11136B		%vreg417<def> = S_MOV_B32 0; SGPR_32:%vreg417
11152B		%vreg416<def> = S_MOV_B32 61440; SGPR_32:%vreg416
11168B		%vreg415:sub0<def,read-undef> = COPY %vreg417; SGPR_64:%vreg415 SGPR_32:%vreg417
11184B		%vreg415:sub1<def> = COPY %vreg416; SGPR_64:%vreg415 SGPR_32:%vreg416
11200B		%vreg396:sub0_sub1<def,read-undef> = COPY %vreg414; SReg_128:%vreg396 SGPR_64:%vreg414
11216B		%vreg396:sub2_sub3<def> = COPY %vreg415; SReg_128:%vreg396 SGPR_64:%vreg415
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11296B		%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
11312B		%vreg418<def> = S_MOV_B64 0; SGPR_64:%vreg418
11328B		%vreg421<def> = S_MOV_B32 0; SGPR_32:%vreg421
11344B		%vreg420<def> = S_MOV_B32 61440; SGPR_32:%vreg420
11360B		%vreg419:sub0<def,read-undef> = COPY %vreg421; SGPR_64:%vreg419 SGPR_32:%vreg421
11376B		%vreg419:sub1<def> = COPY %vreg420; SGPR_64:%vreg419 SGPR_32:%vreg420
11392B		%vreg394:sub0_sub1<def,read-undef> = COPY %vreg418; SReg_128:%vreg394 SGPR_64:%vreg418
11408B		%vreg394:sub2_sub3<def> = COPY %vreg419; SReg_128:%vreg394 SGPR_64:%vreg419
11424B		BUFFER_STORE_DWORD %vreg44, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg44 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

********** SIMPLE REGISTER COALESCING **********
********** Function: svm_rbf
********** JOINING INTERVALS ***********
for.body:
3568B	%vreg26<def> = COPY %vreg855; VGPR_32:%vreg26,%vreg855
	Considering merging to VGPR_32 with %vreg855 in %vreg26
		RHS = %vreg26 [3568r,9280r:0)  0@3568r
		LHS = %vreg855 [2064r,2096B:0)[3552B,3568r:2)[9760r,9808B:1)  0@2064r 1@9760r 2@3552B-phi
		merge %vreg26:0@3568r into %vreg855:2@3552B --> @3552B
		erased:	3568r	%vreg26<def> = COPY %vreg855; VGPR_32:%vreg26,%vreg855
AllocationOrder(VGPR_32) = [ %VGPR0 %VGPR1 %VGPR2 %VGPR3 %VGPR4 %VGPR5 %VGPR6 %VGPR7 %VGPR8 %VGPR9 %VGPR10 %VGPR11 %VGPR12 %VGPR13 %VGPR14 %VGPR15 %VGPR16 %VGPR17 %VGPR18 %VGPR19 %VGPR20 %VGPR21 %VGPR22 %VGPR23 %VGPR24 %VGPR25 %VGPR26 %VGPR27 %VGPR28 %VGPR29 %VGPR30 %VGPR31 %VGPR32 %VGPR33 %VGPR34 %VGPR35 %VGPR36 %VGPR37 %VGPR38 %VGPR39 %VGPR40 %VGPR41 %VGPR42 %VGPR43 %VGPR44 %VGPR45 %VGPR46 %VGPR47 %VGPR48 %VGPR49 %VGPR50 %VGPR51 %VGPR52 %VGPR53 %VGPR54 %VGPR55 %VGPR56 %VGPR57 %VGPR58 %VGPR59 %VGPR60 %VGPR61 %VGPR62 %VGPR63 %VGPR64 %VGPR65 %VGPR66 %VGPR67 %VGPR68 %VGPR69 %VGPR70 %VGPR71 %VGPR72 %VGPR73 %VGPR74 %VGPR75 %VGPR76 %VGPR77 %VGPR78 %VGPR79 %VGPR80 %VGPR81 %VGPR82 %VGPR83 %VGPR84 %VGPR85 %VGPR86 %VGPR87 %VGPR88 %VGPR89 %VGPR90 %VGPR91 %VGPR92 %VGPR93 %VGPR94 %VGPR95 %VGPR96 %VGPR97 %VGPR98 %VGPR99 %VGPR100 %VGPR101 %VGPR102 %VGPR103 %VGPR104 %VGPR105 %VGPR106 %VGPR107 %VGPR108 %VGPR109 %VGPR110 %VGPR111 %VGPR112 %VGPR113 %VGPR114 %VGPR115 %VGPR116 %VGPR117 %VGPR118 %VGPR119 %VGPR120 %VGPR121 %VGPR122 %VGPR123 %VGPR124 %VGPR125 %VGPR126 %VGPR127 %VGPR128 %VGPR129 %VGPR130 %VGPR131 %VGPR132 %VGPR133 %VGPR134 %VGPR135 %VGPR136 %VGPR137 %VGPR138 %VGPR139 %VGPR140 %VGPR141 %VGPR142 %VGPR143 %VGPR144 %VGPR145 %VGPR146 %VGPR147 %VGPR148 %VGPR149 %VGPR150 %VGPR151 %VGPR152 %VGPR153 %VGPR154 %VGPR155 %VGPR156 %VGPR157 %VGPR158 %VGPR159 %VGPR160 %VGPR161 %VGPR162 %VGPR163 %VGPR164 %VGPR165 %VGPR166 %VGPR167 %VGPR168 %VGPR169 %VGPR170 %VGPR171 %VGPR172 %VGPR173 %VGPR174 %VGPR175 %VGPR176 %VGPR177 %VGPR178 %VGPR179 %VGPR180 %VGPR181 %VGPR182 %VGPR183 %VGPR184 %VGPR185 %VGPR186 %VGPR187 %VGPR188 %VGPR189 %VGPR190 %VGPR191 %VGPR192 %VGPR193 %VGPR194 %VGPR195 %VGPR196 %VGPR197 %VGPR198 %VGPR199 %VGPR200 %VGPR201 %VGPR202 %VGPR203 %VGPR204 %VGPR205 %VGPR206 %VGPR207 %VGPR208 %VGPR209 %VGPR210 %VGPR211 %VGPR212 %VGPR213 %VGPR214 %VGPR215 %VGPR216 %VGPR217 %VGPR218 %VGPR219 %VGPR220 %VGPR221 %VGPR222 %VGPR223 %VGPR224 %VGPR225 %VGPR226 %VGPR227 %VGPR228 %VGPR229 %VGPR230 %VGPR231 %VGPR232 %VGPR233 %VGPR234 %VGPR235 %VGPR236 %VGPR237 %VGPR238 %VGPR239 %VGPR240 %VGPR241 %VGPR242 %VGPR243 %VGPR244 %VGPR245 %VGPR246 %VGPR247 %VGPR248 %VGPR249 %VGPR250 %VGPR251 %VGPR252 %VGPR253 %VGPR254 %VGPR255 ]
		updated: 9280B	%vreg282<def> = V_ADD_F32_e32 %vreg855, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg282,%vreg855,%vreg281
	Joined. Result = %vreg855 [2064r,2096B:0)[3552B,9280r:2)[9760r,9808B:1)  0@2064r 1@9760r 2@3552B-phi
3584B	%vreg542<def> = COPY %vreg854; VReg_32:%vreg542,%vreg854
	Considering merging to VReg_32 with %vreg854 in %vreg542
		RHS = %vreg542 [3584r,9568r:0)  0@3584r
		LHS = %vreg854 [2048r,2096B:0)[3552B,3584r:2)[9744r,9808B:1)  0@2048r 1@9744r 2@3552B-phi
		merge %vreg542:0@3584r into %vreg854:2@3552B --> @3552B
		erased:	3584r	%vreg542<def> = COPY %vreg854; VReg_32:%vreg542,%vreg854
AllocationOrder(VReg_32) = [ %VGPR0 %VGPR1 %VGPR2 %VGPR3 %VGPR4 %VGPR5 %VGPR6 %VGPR7 %VGPR8 %VGPR9 %VGPR10 %VGPR11 %VGPR12 %VGPR13 %VGPR14 %VGPR15 %VGPR16 %VGPR17 %VGPR18 %VGPR19 %VGPR20 %VGPR21 %VGPR22 %VGPR23 %VGPR24 %VGPR25 %VGPR26 %VGPR27 %VGPR28 %VGPR29 %VGPR30 %VGPR31 %VGPR32 %VGPR33 %VGPR34 %VGPR35 %VGPR36 %VGPR37 %VGPR38 %VGPR39 %VGPR40 %VGPR41 %VGPR42 %VGPR43 %VGPR44 %VGPR45 %VGPR46 %VGPR47 %VGPR48 %VGPR49 %VGPR50 %VGPR51 %VGPR52 %VGPR53 %VGPR54 %VGPR55 %VGPR56 %VGPR57 %VGPR58 %VGPR59 %VGPR60 %VGPR61 %VGPR62 %VGPR63 %VGPR64 %VGPR65 %VGPR66 %VGPR67 %VGPR68 %VGPR69 %VGPR70 %VGPR71 %VGPR72 %VGPR73 %VGPR74 %VGPR75 %VGPR76 %VGPR77 %VGPR78 %VGPR79 %VGPR80 %VGPR81 %VGPR82 %VGPR83 %VGPR84 %VGPR85 %VGPR86 %VGPR87 %VGPR88 %VGPR89 %VGPR90 %VGPR91 %VGPR92 %VGPR93 %VGPR94 %VGPR95 %VGPR96 %VGPR97 %VGPR98 %VGPR99 %VGPR100 %VGPR101 %VGPR102 %VGPR103 %VGPR104 %VGPR105 %VGPR106 %VGPR107 %VGPR108 %VGPR109 %VGPR110 %VGPR111 %VGPR112 %VGPR113 %VGPR114 %VGPR115 %VGPR116 %VGPR117 %VGPR118 %VGPR119 %VGPR120 %VGPR121 %VGPR122 %VGPR123 %VGPR124 %VGPR125 %VGPR126 %VGPR127 %VGPR128 %VGPR129 %VGPR130 %VGPR131 %VGPR132 %VGPR133 %VGPR134 %VGPR135 %VGPR136 %VGPR137 %VGPR138 %VGPR139 %VGPR140 %VGPR141 %VGPR142 %VGPR143 %VGPR144 %VGPR145 %VGPR146 %VGPR147 %VGPR148 %VGPR149 %VGPR150 %VGPR151 %VGPR152 %VGPR153 %VGPR154 %VGPR155 %VGPR156 %VGPR157 %VGPR158 %VGPR159 %VGPR160 %VGPR161 %VGPR162 %VGPR163 %VGPR164 %VGPR165 %VGPR166 %VGPR167 %VGPR168 %VGPR169 %VGPR170 %VGPR171 %VGPR172 %VGPR173 %VGPR174 %VGPR175 %VGPR176 %VGPR177 %VGPR178 %VGPR179 %VGPR180 %VGPR181 %VGPR182 %VGPR183 %VGPR184 %VGPR185 %VGPR186 %VGPR187 %VGPR188 %VGPR189 %VGPR190 %VGPR191 %VGPR192 %VGPR193 %VGPR194 %VGPR195 %VGPR196 %VGPR197 %VGPR198 %VGPR199 %VGPR200 %VGPR201 %VGPR202 %VGPR203 %VGPR204 %VGPR205 %VGPR206 %VGPR207 %VGPR208 %VGPR209 %VGPR210 %VGPR211 %VGPR212 %VGPR213 %VGPR214 %VGPR215 %VGPR216 %VGPR217 %VGPR218 %VGPR219 %VGPR220 %VGPR221 %VGPR222 %VGPR223 %VGPR224 %VGPR225 %VGPR226 %VGPR227 %VGPR228 %VGPR229 %VGPR230 %VGPR231 %VGPR232 %VGPR233 %VGPR234 %VGPR235 %VGPR236 %VGPR237 %VGPR238 %VGPR239 %VGPR240 %VGPR241 %VGPR242 %VGPR243 %VGPR244 %VGPR245 %VGPR246 %VGPR247 %VGPR248 %VGPR249 %VGPR250 %VGPR251 %VGPR252 %VGPR253 %VGPR254 %VGPR255 ]
		updated: 9568B	%vreg545<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg545,%vreg854
	Joined. Result = %vreg854 [2048r,2096B:0)[3552B,9568r:2)[9744r,9808B:1)  0@2048r 1@9744r 2@3552B-phi
3600B	%vreg24<def> = COPY %vreg853; VReg_64:%vreg24,%vreg853
	Considering merging to VReg_64 with %vreg853 in %vreg24
		RHS = %vreg24 [3600r,9456r:0)  0@3600r
		LHS = %vreg853 [2032r,2096B:0)[3552B,3600r:2)[9728r,9808B:1)  0@2032r 1@9728r 2@3552B-phi
		merge %vreg24:0@3600r into %vreg853:2@3552B --> @3552B
		erased:	3600r	%vreg24<def> = COPY %vreg853; VReg_64:%vreg24,%vreg853
AllocationOrder(VReg_64) = [ %VGPR0_VGPR1 %VGPR1_VGPR2 %VGPR2_VGPR3 %VGPR3_VGPR4 %VGPR4_VGPR5 %VGPR5_VGPR6 %VGPR6_VGPR7 %VGPR7_VGPR8 %VGPR8_VGPR9 %VGPR9_VGPR10 %VGPR10_VGPR11 %VGPR11_VGPR12 %VGPR12_VGPR13 %VGPR13_VGPR14 %VGPR14_VGPR15 %VGPR15_VGPR16 %VGPR16_VGPR17 %VGPR17_VGPR18 %VGPR18_VGPR19 %VGPR19_VGPR20 %VGPR20_VGPR21 %VGPR21_VGPR22 %VGPR22_VGPR23 %VGPR23_VGPR24 %VGPR24_VGPR25 %VGPR25_VGPR26 %VGPR26_VGPR27 %VGPR27_VGPR28 %VGPR28_VGPR29 %VGPR29_VGPR30 %VGPR30_VGPR31 %VGPR31_VGPR32 %VGPR32_VGPR33 %VGPR33_VGPR34 %VGPR34_VGPR35 %VGPR35_VGPR36 %VGPR36_VGPR37 %VGPR37_VGPR38 %VGPR38_VGPR39 %VGPR39_VGPR40 %VGPR40_VGPR41 %VGPR41_VGPR42 %VGPR42_VGPR43 %VGPR43_VGPR44 %VGPR44_VGPR45 %VGPR45_VGPR46 %VGPR46_VGPR47 %VGPR47_VGPR48 %VGPR48_VGPR49 %VGPR49_VGPR50 %VGPR50_VGPR51 %VGPR51_VGPR52 %VGPR52_VGPR53 %VGPR53_VGPR54 %VGPR54_VGPR55 %VGPR55_VGPR56 %VGPR56_VGPR57 %VGPR57_VGPR58 %VGPR58_VGPR59 %VGPR59_VGPR60 %VGPR60_VGPR61 %VGPR61_VGPR62 %VGPR62_VGPR63 %VGPR63_VGPR64 %VGPR64_VGPR65 %VGPR65_VGPR66 %VGPR66_VGPR67 %VGPR67_VGPR68 %VGPR68_VGPR69 %VGPR69_VGPR70 %VGPR70_VGPR71 %VGPR71_VGPR72 %VGPR72_VGPR73 %VGPR73_VGPR74 %VGPR74_VGPR75 %VGPR75_VGPR76 %VGPR76_VGPR77 %VGPR77_VGPR78 %VGPR78_VGPR79 %VGPR79_VGPR80 %VGPR80_VGPR81 %VGPR81_VGPR82 %VGPR82_VGPR83 %VGPR83_VGPR84 %VGPR84_VGPR85 %VGPR85_VGPR86 %VGPR86_VGPR87 %VGPR87_VGPR88 %VGPR88_VGPR89 %VGPR89_VGPR90 %VGPR90_VGPR91 %VGPR91_VGPR92 %VGPR92_VGPR93 %VGPR93_VGPR94 %VGPR94_VGPR95 %VGPR95_VGPR96 %VGPR96_VGPR97 %VGPR97_VGPR98 %VGPR98_VGPR99 %VGPR99_VGPR100 %VGPR100_VGPR101 %VGPR101_VGPR102 %VGPR102_VGPR103 %VGPR103_VGPR104 %VGPR104_VGPR105 %VGPR105_VGPR106 %VGPR106_VGPR107 %VGPR107_VGPR108 %VGPR108_VGPR109 %VGPR109_VGPR110 %VGPR110_VGPR111 %VGPR111_VGPR112 %VGPR112_VGPR113 %VGPR113_VGPR114 %VGPR114_VGPR115 %VGPR115_VGPR116 %VGPR116_VGPR117 %VGPR117_VGPR118 %VGPR118_VGPR119 %VGPR119_VGPR120 %VGPR120_VGPR121 %VGPR121_VGPR122 %VGPR122_VGPR123 %VGPR123_VGPR124 %VGPR124_VGPR125 %VGPR125_VGPR126 %VGPR126_VGPR127 %VGPR127_VGPR128 %VGPR128_VGPR129 %VGPR129_VGPR130 %VGPR130_VGPR131 %VGPR131_VGPR132 %VGPR132_VGPR133 %VGPR133_VGPR134 %VGPR134_VGPR135 %VGPR135_VGPR136 %VGPR136_VGPR137 %VGPR137_VGPR138 %VGPR138_VGPR139 %VGPR139_VGPR140 %VGPR140_VGPR141 %VGPR141_VGPR142 %VGPR142_VGPR143 %VGPR143_VGPR144 %VGPR144_VGPR145 %VGPR145_VGPR146 %VGPR146_VGPR147 %VGPR147_VGPR148 %VGPR148_VGPR149 %VGPR149_VGPR150 %VGPR150_VGPR151 %VGPR151_VGPR152 %VGPR152_VGPR153 %VGPR153_VGPR154 %VGPR154_VGPR155 %VGPR155_VGPR156 %VGPR156_VGPR157 %VGPR157_VGPR158 %VGPR158_VGPR159 %VGPR159_VGPR160 %VGPR160_VGPR161 %VGPR161_VGPR162 %VGPR162_VGPR163 %VGPR163_VGPR164 %VGPR164_VGPR165 %VGPR165_VGPR166 %VGPR166_VGPR167 %VGPR167_VGPR168 %VGPR168_VGPR169 %VGPR169_VGPR170 %VGPR170_VGPR171 %VGPR171_VGPR172 %VGPR172_VGPR173 %VGPR173_VGPR174 %VGPR174_VGPR175 %VGPR175_VGPR176 %VGPR176_VGPR177 %VGPR177_VGPR178 %VGPR178_VGPR179 %VGPR179_VGPR180 %VGPR180_VGPR181 %VGPR181_VGPR182 %VGPR182_VGPR183 %VGPR183_VGPR184 %VGPR184_VGPR185 %VGPR185_VGPR186 %VGPR186_VGPR187 %VGPR187_VGPR188 %VGPR188_VGPR189 %VGPR189_VGPR190 %VGPR190_VGPR191 %VGPR191_VGPR192 %VGPR192_VGPR193 %VGPR193_VGPR194 %VGPR194_VGPR195 %VGPR195_VGPR196 %VGPR196_VGPR197 %VGPR197_VGPR198 %VGPR198_VGPR199 %VGPR199_VGPR200 %VGPR200_VGPR201 %VGPR201_VGPR202 %VGPR202_VGPR203 %VGPR203_VGPR204 %VGPR204_VGPR205 %VGPR205_VGPR206 %VGPR206_VGPR207 %VGPR207_VGPR208 %VGPR208_VGPR209 %VGPR209_VGPR210 %VGPR210_VGPR211 %VGPR211_VGPR212 %VGPR212_VGPR213 %VGPR213_VGPR214 %VGPR214_VGPR215 %VGPR215_VGPR216 %VGPR216_VGPR217 %VGPR217_VGPR218 %VGPR218_VGPR219 %VGPR219_VGPR220 %VGPR220_VGPR221 %VGPR221_VGPR222 %VGPR222_VGPR223 %VGPR223_VGPR224 %VGPR224_VGPR225 %VGPR225_VGPR226 %VGPR226_VGPR227 %VGPR227_VGPR228 %VGPR228_VGPR229 %VGPR229_VGPR230 %VGPR230_VGPR231 %VGPR231_VGPR232 %VGPR232_VGPR233 %VGPR233_VGPR234 %VGPR234_VGPR235 %VGPR235_VGPR236 %VGPR236_VGPR237 %VGPR237_VGPR238 %VGPR238_VGPR239 %VGPR239_VGPR240 %VGPR240_VGPR241 %VGPR241_VGPR242 %VGPR242_VGPR243 %VGPR243_VGPR244 %VGPR244_VGPR245 %VGPR245_VGPR246 %VGPR246_VGPR247 %VGPR247_VGPR248 %VGPR248_VGPR249 %VGPR249_VGPR250 %VGPR250_VGPR251 %VGPR251_VGPR252 %VGPR252_VGPR253 %VGPR253_VGPR254 %VGPR254_VGPR255 ]
		updated: 3712B	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg853, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_64:%vreg853
		updated: 3776B	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg853, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_64:%vreg853
		updated: 3840B	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg853, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_64:%vreg853
		updated: 3904B	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg853, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_64:%vreg853
		updated: 3968B	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg853, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_64:%vreg853
		updated: 4032B	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg853, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_64:%vreg853
		updated: 4096B	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg853, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_64:%vreg853
		updated: 4160B	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg853, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_64:%vreg853
		updated: 4256B	%vreg560<def> = COPY %vreg853; VReg_64:%vreg560,%vreg853
		updated: 9440B	%vreg819<def> = COPY %vreg853:sub0; VReg_32:%vreg819 VReg_64:%vreg853
		updated: 9456B	%vreg825<def> = COPY %vreg853:sub1; VReg_32:%vreg825 VReg_64:%vreg853
	Joined. Result = %vreg853 [2032r,2096B:0)[3552B,9456r:2)[9728r,9808B:1)  0@2032r 1@9728r 2@3552B-phi
3616B	%vreg23<def> = COPY %vreg852; VReg_64:%vreg23,%vreg852
	Considering merging to VReg_64 with %vreg852 in %vreg23
		RHS = %vreg23 [3616r,9344r:0)  0@3616r
		LHS = %vreg852 [2016r,2096B:0)[3552B,3616r:2)[9712r,9808B:1)  0@2016r 1@9712r 2@3552B-phi
		merge %vreg23:0@3616r into %vreg852:2@3552B --> @3552B
		erased:	3616r	%vreg23<def> = COPY %vreg852; VReg_64:%vreg23,%vreg852
		updated: 3728B	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg852, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg148 VReg_64:%vreg852
		updated: 3792B	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg852, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg148 VReg_64:%vreg852
		updated: 3856B	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg852, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg148 VReg_64:%vreg852
		updated: 3920B	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg852, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg148 VReg_64:%vreg852
		updated: 3984B	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg852, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg148 VReg_64:%vreg852
		updated: 4048B	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg852, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg148 VReg_64:%vreg852
		updated: 4112B	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg852, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg148 VReg_64:%vreg852
		updated: 4176B	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg852, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg148 VReg_64:%vreg852
		updated: 4608B	%vreg685<def> = COPY %vreg852; VReg_64:%vreg685,%vreg852
		updated: 9312B	%vreg810<def> = COPY %vreg852:sub0; VReg_32:%vreg810 VReg_64:%vreg852
		updated: 9344B	%vreg816<def> = COPY %vreg852:sub1; VReg_32:%vreg816 VReg_64:%vreg852
	Joined. Result = %vreg852 [2016r,2096B:0)[3552B,9344r:2)[9712r,9808B:1)  0@2016r 1@9712r 2@3552B-phi
3632B	%vreg22<def> = COPY %vreg851; SReg_64:%vreg22,%vreg851
	Considering merging to SReg_64 with %vreg851 in %vreg22
		RHS = %vreg22 [3632r,9600r:0)  0@3632r
		LHS = %vreg851 [2000r,2096B:0)[3552B,3632r:2)[9696r,9808B:1)  0@2000r 1@9696r 2@3552B-phi
		merge %vreg22:0@3632r into %vreg851:2@3552B --> @3552B
		erased:	3632r	%vreg22<def> = COPY %vreg851; SReg_64:%vreg22,%vreg851
AllocationOrder(SReg_64) = [ %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR10_SGPR11 %SGPR12_SGPR13 %SGPR14_SGPR15 %SGPR16_SGPR17 %SGPR18_SGPR19 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %SGPR42_SGPR43 %SGPR44_SGPR45 %SGPR46_SGPR47 %SGPR48_SGPR49 %SGPR50_SGPR51 %SGPR52_SGPR53 %SGPR54_SGPR55 %SGPR56_SGPR57 %SGPR58_SGPR59 %SGPR60_SGPR61 %SGPR62_SGPR63 %SGPR64_SGPR65 %SGPR66_SGPR67 %SGPR68_SGPR69 %SGPR70_SGPR71 %SGPR72_SGPR73 %SGPR74_SGPR75 %SGPR76_SGPR77 %SGPR78_SGPR79 %SGPR80_SGPR81 %SGPR82_SGPR83 %SGPR84_SGPR85 %SGPR86_SGPR87 %SGPR88_SGPR89 %SGPR90_SGPR91 %SGPR92_SGPR93 %SGPR94_SGPR95 %SGPR96_SGPR97 %SGPR98_SGPR99 %SGPR100_SGPR101 %VCC ]
		updated: 9600B	%vreg298<def> = SI_IF_BREAK %vreg297, %vreg851, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg298,%vreg297,%vreg851
	Joined. Result = %vreg851 [2000r,2096B:0)[3552B,9600r:2)[9696r,9808B:1)  0@2000r 1@9696r 2@3552B-phi
3648B	%vreg399:sub0<def,read-undef> = COPY %vreg401; SGPR_64:%vreg399 SGPR_32:%vreg401
	Considering merging to SGPR_64 with %vreg401 in %vreg399:sub0
		RHS = %vreg401 [1792r,2096B:0)[3552B,9808B:0)  0@1792r
		LHS = %vreg399 [3648r,3664r:1)[3664r,4640r:0)  0@3664r 1@3648r
		merge %vreg399:1@3648r into %vreg401:0@1792r --> @1792r
		pruned %vreg401 at 3664r: %vreg401 [1792r,2096B:0)  0@1792r
		pruned all of %vreg399 at 3648r: %vreg399 [3664r,4640r:0)  0@3664r 1@3648r
		erased:	3648r	%vreg399:sub0<def,read-undef> = COPY %vreg401; SGPR_64:%vreg399 SGPR_32:%vreg401
		restoring liveness to 4 points: %vreg399 [1792r,2096B:0)[3664r,4640r:1)  0@1792r 1@3664r
AllocationOrder(SGPR_64) = [ %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR10_SGPR11 %SGPR12_SGPR13 %SGPR14_SGPR15 %SGPR16_SGPR17 %SGPR18_SGPR19 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %SGPR42_SGPR43 %SGPR44_SGPR45 %SGPR46_SGPR47 %SGPR48_SGPR49 %SGPR50_SGPR51 %SGPR52_SGPR53 %SGPR54_SGPR55 %SGPR56_SGPR57 %SGPR58_SGPR59 %SGPR60_SGPR61 %SGPR62_SGPR63 %SGPR64_SGPR65 %SGPR66_SGPR67 %SGPR68_SGPR69 %SGPR70_SGPR71 %SGPR72_SGPR73 %SGPR74_SGPR75 %SGPR76_SGPR77 %SGPR78_SGPR79 %SGPR80_SGPR81 %SGPR82_SGPR83 %SGPR84_SGPR85 %SGPR86_SGPR87 %SGPR88_SGPR89 %SGPR90_SGPR91 %SGPR92_SGPR93 %SGPR94_SGPR95 %SGPR96_SGPR97 %SGPR98_SGPR99 %SGPR100_SGPR101 ]
		updated: 1792B	%vreg399:sub0<def,read-undef> = S_MOV_B32 0; SGPR_64:%vreg399
		updated: 4560B	%vreg676:sub2<def> = COPY %vreg399:sub0; SReg_128:%vreg676 SGPR_64:%vreg399
	Joined. Result = %vreg399 [1792r,2096B:0)[3552B,3664r:2)[3664r,9808B:1)  0@1792r 1@3664r 2@3552B-phi
3664B	%vreg399:sub1<def> = COPY %vreg400; SGPR_64:%vreg399 SGPR_32:%vreg400
	Considering merging to SGPR_64 with %vreg400 in %vreg399:sub1
		RHS = %vreg400 [1808r,2096B:0)[3552B,9808B:0)  0@1808r
		LHS = %vreg399 [1792r,2096B:0)[3552B,3664r:2)[3664r,9808B:1)  0@1792r 1@3664r 2@3552B-phi
		merge %vreg399:1@3664r into %vreg400:0@1808r --> @1808r
		pruned all of %vreg399 at 3664r: %vreg399 [1792r,2096B:0)[3552B,3664r:2)  0@1792r 1@3664r 2@3552B-phi
		pruned %vreg400 at 3552B: %vreg400 [1808r,2096B:0)  0@1808r
		pruned %vreg399 at 1808r: %vreg399 [1792r,1808r:0)[3552B,3664r:2)  0@1792r 1@3664r 2@3552B-phi
		erased:	3664r	%vreg399:sub1<def> = COPY %vreg400; SGPR_64:%vreg399 SGPR_32:%vreg400
		restoring liveness to 4 points: %vreg399 [1792r,1808r:0)[1808r,2096B:1)[3552B,3664r:2)  0@1792r 1@1808r 2@3552B-phi
		updated: 1808B	%vreg399:sub1<def> = S_MOV_B32 61440; SGPR_64:%vreg399
		updated: 4576B	%vreg676:sub3<def> = COPY %vreg399:sub1; SReg_128:%vreg676 SGPR_64:%vreg399
	Joined. Result = %vreg399 [1792r,1808r:0)[1808r,2096B:1)[3552B,9808B:2)  0@1792r 1@1808r 2@3552B-phi
3680B	%vreg148:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg148 SGPR_64:%vreg147
	Considering merging to SReg_128 with %vreg147 in %vreg148:sub0_sub1
		RHS = %vreg147 [1728r,2096B:0)[3552B,9808B:0)  0@1728r
		LHS = %vreg148 [3680r,3696r:1)[3696r,4176r:0)  0@3696r 1@3680r
		merge %vreg148:1@3680r into %vreg147:0@1728r --> @1728r
		pruned %vreg147 at 3696r: %vreg147 [1728r,2096B:0)  0@1728r
		pruned all of %vreg148 at 3680r: %vreg148 [3696r,4176r:0)  0@3696r 1@3680r
		erased:	3680r	%vreg148:sub0_sub1<def,read-undef> = COPY %vreg147; SReg_128:%vreg148 SGPR_64:%vreg147
		restoring liveness to 4 points: %vreg148 [1728r,2096B:0)[3696r,4176r:1)  0@1728r 1@3696r
AllocationOrder(SReg_128) = [ %SGPR0_SGPR1_SGPR2_SGPR3 %SGPR4_SGPR5_SGPR6_SGPR7 %SGPR8_SGPR9_SGPR10_SGPR11 %SGPR12_SGPR13_SGPR14_SGPR15 %SGPR16_SGPR17_SGPR18_SGPR19 %SGPR20_SGPR21_SGPR22_SGPR23 %SGPR24_SGPR25_SGPR26_SGPR27 %SGPR28_SGPR29_SGPR30_SGPR31 %SGPR32_SGPR33_SGPR34_SGPR35 %SGPR36_SGPR37_SGPR38_SGPR39 %SGPR40_SGPR41_SGPR42_SGPR43 %SGPR44_SGPR45_SGPR46_SGPR47 %SGPR48_SGPR49_SGPR50_SGPR51 %SGPR52_SGPR53_SGPR54_SGPR55 %SGPR56_SGPR57_SGPR58_SGPR59 %SGPR60_SGPR61_SGPR62_SGPR63 %SGPR64_SGPR65_SGPR66_SGPR67 %SGPR68_SGPR69_SGPR70_SGPR71 %SGPR72_SGPR73_SGPR74_SGPR75 %SGPR76_SGPR77_SGPR78_SGPR79 %SGPR80_SGPR81_SGPR82_SGPR83 %SGPR84_SGPR85_SGPR86_SGPR87 %SGPR88_SGPR89_SGPR90_SGPR91 %SGPR92_SGPR93_SGPR94_SGPR95 %SGPR96_SGPR97_SGPR98_SGPR99 ]
		updated: 1728B	%vreg148:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg148
		updated: 1744B	%vreg93<def> = COPY %vreg148:sub0_sub1; SGPR_64:%vreg93 SReg_128:%vreg148
		updated: 4544B	%vreg676:sub0_sub1<def,read-undef> = COPY %vreg148:sub0_sub1; SReg_128:%vreg676,%vreg148
	Joined. Result = %vreg148 [1728r,2096B:0)[3552B,3696r:2)[3696r,9808B:1)  0@1728r 1@3696r 2@3552B-phi
3696B	%vreg148:sub2_sub3<def> = COPY %vreg399; SReg_128:%vreg148 SGPR_64:%vreg399
	Considering merging to SReg_128 with %vreg399 in %vreg148:sub2_sub3
		RHS = %vreg399 [1792r,1808r:0)[1808r,2096B:1)[3552B,9808B:2)  0@1792r 1@1808r 2@3552B-phi
		LHS = %vreg148 [1728r,2096B:0)[3552B,3696r:2)[3696r,9808B:1)  0@1728r 1@3696r 2@3552B-phi
		merge %vreg399:2@3552B into %vreg148:2@3552B --> @3552B
		merge %vreg148:1@3696r into %vreg399:2@3552B --> @3552B
		pruned %vreg148 at 1792r: %vreg148 [1728r,1792r:0)[3552B,3696r:2)[3696r,9808B:1)  0@1728r 1@3696r 2@3552B-phi
		pruned %vreg148 at 1808r: %vreg148 [1728r,1792r:0)[3552B,3696r:2)[3696r,9808B:1)  0@1728r 1@3696r 2@3552B-phi
		erased:	3696r	%vreg148:sub2_sub3<def> = COPY %vreg399; SReg_128:%vreg148 SGPR_64:%vreg399
		restoring liveness to 3 points: %vreg148 [1728r,1792r:0)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:1)  0@1728r 1@3552B-phi 2@1792r 3@1808r
		updated: 1808B	%vreg148:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg148
		updated: 1792B	%vreg148:sub2<def> = S_MOV_B32 0; SReg_128:%vreg148
		updated: 4288B	%vreg564<def> = COPY %vreg148:sub2_sub3; VReg_64:%vreg564 SReg_128:%vreg148
		updated: 4640B	%vreg689<def> = COPY %vreg148:sub2_sub3; VReg_64:%vreg689 SReg_128:%vreg148
		updated: 4560B	%vreg676:sub2<def> = COPY %vreg148:sub2; SReg_128:%vreg676,%vreg148
		updated: 4576B	%vreg676:sub3<def> = COPY %vreg148:sub3; SReg_128:%vreg676,%vreg148
	Joined. Result = %vreg148 [1728r,1792r:0)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:1)  0@1728r 1@3552B-phi 2@1792r 3@1808r
4224B	%vreg183:sub0<def,read-undef> = COPY %vreg182; SGPR_64:%vreg183 SReg_32:%vreg182
	Considering merging to SGPR_64 with %vreg182 in %vreg183:sub0
		RHS = %vreg182 [1840r,2096B:0)[3552B,9808B:0)  0@1840r
		LHS = %vreg183 [4224r,4240r:1)[4240r,4688r:0)  0@4240r 1@4224r
		merge %vreg183:1@4224r into %vreg182:0@1840r --> @1840r
		pruned %vreg182 at 4240r: %vreg182 [1840r,2096B:0)  0@1840r
		pruned all of %vreg183 at 4224r: %vreg183 [4240r,4688r:0)  0@4240r 1@4224r
		erased:	4224r	%vreg183:sub0<def,read-undef> = COPY %vreg182; SGPR_64:%vreg183 SReg_32:%vreg182
		restoring liveness to 4 points: %vreg183 [1840r,2096B:0)[4240r,4688r:1)  0@1840r 1@4240r
		updated: 1840B	%vreg183:sub0<def,read-undef> = S_MOV_B32 -4; SGPR_64:%vreg183
	Joined. Result = %vreg183 [1840r,2096B:0)[3552B,4240r:2)[4240r,9808B:1)  0@1840r 1@4240r 2@3552B-phi
4240B	%vreg183:sub1<def> = COPY %vreg181; SGPR_64:%vreg183 SReg_32:%vreg181
	Considering merging to SGPR_64 with %vreg181 in %vreg183:sub1
		RHS = %vreg181 [1824r,2096B:0)[3552B,9808B:0)  0@1824r
		LHS = %vreg183 [1840r,2096B:0)[3552B,4240r:2)[4240r,9808B:1)  0@1840r 1@4240r 2@3552B-phi
		merge %vreg183:1@4240r into %vreg181:0@1824r --> @1824r
		pruned %vreg181 at 1840r: %vreg181 [1824r,1840r:0)  0@1824r
		pruned all of %vreg183 at 4240r: %vreg183 [1840r,2096B:0)[3552B,4240r:2)  0@1840r 1@4240r 2@3552B-phi
		pruned %vreg181 at 3552B: %vreg181 [1824r,1840r:0)  0@1824r
		erased:	4240r	%vreg183:sub1<def> = COPY %vreg181; SGPR_64:%vreg183 SReg_32:%vreg181
		restoring liveness to 4 points: %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,4240r:2)  0@1824r 1@1840r 2@3552B-phi
		updated: 1824B	%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
		updated: 4960B	%vreg195:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg195,%vreg183
		updated: 5472B	%vreg203:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg203,%vreg183
		updated: 5984B	%vreg211:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg211,%vreg183
		updated: 6496B	%vreg219:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg219,%vreg183
		updated: 7008B	%vreg227:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg227,%vreg183
		updated: 7520B	%vreg235:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg235,%vreg183
		updated: 8032B	%vreg243:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg243,%vreg183
	Joined. Result = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
4256B	%vreg560<def> = COPY %vreg853; VReg_64:%vreg560,%vreg853
	Considering merging to VReg_64 with %vreg853 in %vreg560
		RHS = %vreg560 [4256r,4272r:0)  0@4256r
		LHS = %vreg853 [2032r,2096B:0)[3552B,9456r:2)[9728r,9808B:1)  0@2032r 1@9728r 2@3552B-phi
		merge %vreg560:0@4256r into %vreg853:2@3552B --> @3552B
		erased:	4256r	%vreg560<def> = COPY %vreg853; VReg_64:%vreg560,%vreg853
		updated: 4272B	%vreg561<def> = COPY %vreg853; VReg_64:%vreg561,%vreg853
	Joined. Result = %vreg853 [2032r,2096B:0)[3552B,9456r:2)[9728r,9808B:1)  0@2032r 1@9728r 2@3552B-phi
4272B	%vreg561<def> = COPY %vreg853; VReg_64:%vreg561,%vreg853
	Considering merging to VReg_64 with %vreg853 in %vreg561
		RHS = %vreg561 [4272r,4304r:0)  0@4272r
		LHS = %vreg853 [2032r,2096B:0)[3552B,9456r:2)[9728r,9808B:1)  0@2032r 1@9728r 2@3552B-phi
		merge %vreg561:0@4272r into %vreg853:2@3552B --> @3552B
		erased:	4272r	%vreg561<def> = COPY %vreg853; VReg_64:%vreg561,%vreg853
		updated: 4304B	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg853; VReg_128:%vreg562 VReg_64:%vreg853
	Joined. Result = %vreg853 [2032r,2096B:0)[3552B,9456r:2)[9728r,9808B:1)  0@2032r 1@9728r 2@3552B-phi
4288B	%vreg564<def> = COPY %vreg148:sub2_sub3; VReg_64:%vreg564 SReg_128:%vreg148
	Not coalescable.
4304B	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg853; VReg_128:%vreg562 VReg_64:%vreg853
	Considering merging to VReg_128 with %vreg853 in %vreg562:sub0_sub1
		RHS = %vreg853 [2032r,2096B:0)[3552B,9456r:2)[9728r,9808B:1)  0@2032r 1@9728r 2@3552B-phi
		LHS = %vreg562 [4304r,4320r:1)[4320r,8096r:0)  0@4320r 1@4304r
		merge %vreg562:1@4304r into %vreg853:2@3552B --> @3552B
		pruned %vreg853 at 4320r: %vreg853 [2032r,2096B:0)[3552B,4320r:2)[9728r,9808B:1)  0@2032r 1@9728r 2@3552B-phi
		pruned all of %vreg562 at 4304r: %vreg562 [4320r,8096r:0)  0@4320r 1@4304r
		erased:	4304r	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg853; VReg_128:%vreg562 VReg_64:%vreg853
		restoring liveness to 3 points: %vreg562 [2032r,2096B:2)[3552B,4320r:0)[4320r,8096r:1)[9728r,9808B:3)  0@3552B-phi 1@4320r 2@2032r 3@9728r
AllocationOrder(VReg_128) = [ %VGPR0_VGPR1_VGPR2_VGPR3 %VGPR1_VGPR2_VGPR3_VGPR4 %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR3_VGPR4_VGPR5_VGPR6 %VGPR4_VGPR5_VGPR6_VGPR7 %VGPR5_VGPR6_VGPR7_VGPR8 %VGPR6_VGPR7_VGPR8_VGPR9 %VGPR7_VGPR8_VGPR9_VGPR10 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR9_VGPR10_VGPR11_VGPR12 %VGPR10_VGPR11_VGPR12_VGPR13 %VGPR11_VGPR12_VGPR13_VGPR14 %VGPR12_VGPR13_VGPR14_VGPR15 %VGPR13_VGPR14_VGPR15_VGPR16 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR15_VGPR16_VGPR17_VGPR18 %VGPR16_VGPR17_VGPR18_VGPR19 %VGPR17_VGPR18_VGPR19_VGPR20 %VGPR18_VGPR19_VGPR20_VGPR21 %VGPR19_VGPR20_VGPR21_VGPR22 %VGPR20_VGPR21_VGPR22_VGPR23 %VGPR21_VGPR22_VGPR23_VGPR24 %VGPR22_VGPR23_VGPR24_VGPR25 %VGPR23_VGPR24_VGPR25_VGPR26 %VGPR24_VGPR25_VGPR26_VGPR27 %VGPR25_VGPR26_VGPR27_VGPR28 %VGPR26_VGPR27_VGPR28_VGPR29 %VGPR27_VGPR28_VGPR29_VGPR30 %VGPR28_VGPR29_VGPR30_VGPR31 %VGPR29_VGPR30_VGPR31_VGPR32 %VGPR30_VGPR31_VGPR32_VGPR33 %VGPR31_VGPR32_VGPR33_VGPR34 %VGPR32_VGPR33_VGPR34_VGPR35 %VGPR33_VGPR34_VGPR35_VGPR36 %VGPR34_VGPR35_VGPR36_VGPR37 %VGPR35_VGPR36_VGPR37_VGPR38 %VGPR36_VGPR37_VGPR38_VGPR39 %VGPR37_VGPR38_VGPR39_VGPR40 %VGPR38_VGPR39_VGPR40_VGPR41 %VGPR39_VGPR40_VGPR41_VGPR42 %VGPR40_VGPR41_VGPR42_VGPR43 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR42_VGPR43_VGPR44_VGPR45 %VGPR43_VGPR44_VGPR45_VGPR46 %VGPR44_VGPR45_VGPR46_VGPR47 %VGPR45_VGPR46_VGPR47_VGPR48 %VGPR46_VGPR47_VGPR48_VGPR49 %VGPR47_VGPR48_VGPR49_VGPR50 %VGPR48_VGPR49_VGPR50_VGPR51 %VGPR49_VGPR50_VGPR51_VGPR52 %VGPR50_VGPR51_VGPR52_VGPR53 %VGPR51_VGPR52_VGPR53_VGPR54 %VGPR52_VGPR53_VGPR54_VGPR55 %VGPR53_VGPR54_VGPR55_VGPR56 %VGPR54_VGPR55_VGPR56_VGPR57 %VGPR55_VGPR56_VGPR57_VGPR58 %VGPR56_VGPR57_VGPR58_VGPR59 %VGPR57_VGPR58_VGPR59_VGPR60 %VGPR58_VGPR59_VGPR60_VGPR61 %VGPR59_VGPR60_VGPR61_VGPR62 %VGPR60_VGPR61_VGPR62_VGPR63 %VGPR61_VGPR62_VGPR63_VGPR64 %VGPR62_VGPR63_VGPR64_VGPR65 %VGPR63_VGPR64_VGPR65_VGPR66 %VGPR64_VGPR65_VGPR66_VGPR67 %VGPR65_VGPR66_VGPR67_VGPR68 %VGPR66_VGPR67_VGPR68_VGPR69 %VGPR67_VGPR68_VGPR69_VGPR70 %VGPR68_VGPR69_VGPR70_VGPR71 %VGPR69_VGPR70_VGPR71_VGPR72 %VGPR70_VGPR71_VGPR72_VGPR73 %VGPR71_VGPR72_VGPR73_VGPR74 %VGPR72_VGPR73_VGPR74_VGPR75 %VGPR73_VGPR74_VGPR75_VGPR76 %VGPR74_VGPR75_VGPR76_VGPR77 %VGPR75_VGPR76_VGPR77_VGPR78 %VGPR76_VGPR77_VGPR78_VGPR79 %VGPR77_VGPR78_VGPR79_VGPR80 %VGPR78_VGPR79_VGPR80_VGPR81 %VGPR79_VGPR80_VGPR81_VGPR82 %VGPR80_VGPR81_VGPR82_VGPR83 %VGPR81_VGPR82_VGPR83_VGPR84 %VGPR82_VGPR83_VGPR84_VGPR85 %VGPR83_VGPR84_VGPR85_VGPR86 %VGPR84_VGPR85_VGPR86_VGPR87 %VGPR85_VGPR86_VGPR87_VGPR88 %VGPR86_VGPR87_VGPR88_VGPR89 %VGPR87_VGPR88_VGPR89_VGPR90 %VGPR88_VGPR89_VGPR90_VGPR91 %VGPR89_VGPR90_VGPR91_VGPR92 %VGPR90_VGPR91_VGPR92_VGPR93 %VGPR91_VGPR92_VGPR93_VGPR94 %VGPR92_VGPR93_VGPR94_VGPR95 %VGPR93_VGPR94_VGPR95_VGPR96 %VGPR94_VGPR95_VGPR96_VGPR97 %VGPR95_VGPR96_VGPR97_VGPR98 %VGPR96_VGPR97_VGPR98_VGPR99 %VGPR97_VGPR98_VGPR99_VGPR100 %VGPR98_VGPR99_VGPR100_VGPR101 %VGPR99_VGPR100_VGPR101_VGPR102 %VGPR100_VGPR101_VGPR102_VGPR103 %VGPR101_VGPR102_VGPR103_VGPR104 %VGPR102_VGPR103_VGPR104_VGPR105 %VGPR103_VGPR104_VGPR105_VGPR106 %VGPR104_VGPR105_VGPR106_VGPR107 %VGPR105_VGPR106_VGPR107_VGPR108 %VGPR106_VGPR107_VGPR108_VGPR109 %VGPR107_VGPR108_VGPR109_VGPR110 %VGPR108_VGPR109_VGPR110_VGPR111 %VGPR109_VGPR110_VGPR111_VGPR112 %VGPR110_VGPR111_VGPR112_VGPR113 %VGPR111_VGPR112_VGPR113_VGPR114 %VGPR112_VGPR113_VGPR114_VGPR115 %VGPR113_VGPR114_VGPR115_VGPR116 %VGPR114_VGPR115_VGPR116_VGPR117 %VGPR115_VGPR116_VGPR117_VGPR118 %VGPR116_VGPR117_VGPR118_VGPR119 %VGPR117_VGPR118_VGPR119_VGPR120 %VGPR118_VGPR119_VGPR120_VGPR121 %VGPR119_VGPR120_VGPR121_VGPR122 %VGPR120_VGPR121_VGPR122_VGPR123 %VGPR121_VGPR122_VGPR123_VGPR124 %VGPR122_VGPR123_VGPR124_VGPR125 %VGPR123_VGPR124_VGPR125_VGPR126 %VGPR124_VGPR125_VGPR126_VGPR127 %VGPR125_VGPR126_VGPR127_VGPR128 %VGPR126_VGPR127_VGPR128_VGPR129 %VGPR127_VGPR128_VGPR129_VGPR130 %VGPR128_VGPR129_VGPR130_VGPR131 %VGPR129_VGPR130_VGPR131_VGPR132 %VGPR130_VGPR131_VGPR132_VGPR133 %VGPR131_VGPR132_VGPR133_VGPR134 %VGPR132_VGPR133_VGPR134_VGPR135 %VGPR133_VGPR134_VGPR135_VGPR136 %VGPR134_VGPR135_VGPR136_VGPR137 %VGPR135_VGPR136_VGPR137_VGPR138 %VGPR136_VGPR137_VGPR138_VGPR139 %VGPR137_VGPR138_VGPR139_VGPR140 %VGPR138_VGPR139_VGPR140_VGPR141 %VGPR139_VGPR140_VGPR141_VGPR142 %VGPR140_VGPR141_VGPR142_VGPR143 %VGPR141_VGPR142_VGPR143_VGPR144 %VGPR142_VGPR143_VGPR144_VGPR145 %VGPR143_VGPR144_VGPR145_VGPR146 %VGPR144_VGPR145_VGPR146_VGPR147 %VGPR145_VGPR146_VGPR147_VGPR148 %VGPR146_VGPR147_VGPR148_VGPR149 %VGPR147_VGPR148_VGPR149_VGPR150 %VGPR148_VGPR149_VGPR150_VGPR151 %VGPR149_VGPR150_VGPR151_VGPR152 %VGPR150_VGPR151_VGPR152_VGPR153 %VGPR151_VGPR152_VGPR153_VGPR154 %VGPR152_VGPR153_VGPR154_VGPR155 %VGPR153_VGPR154_VGPR155_VGPR156 %VGPR154_VGPR155_VGPR156_VGPR157 %VGPR155_VGPR156_VGPR157_VGPR158 %VGPR156_VGPR157_VGPR158_VGPR159 %VGPR157_VGPR158_VGPR159_VGPR160 %VGPR158_VGPR159_VGPR160_VGPR161 %VGPR159_VGPR160_VGPR161_VGPR162 %VGPR160_VGPR161_VGPR162_VGPR163 %VGPR161_VGPR162_VGPR163_VGPR164 %VGPR162_VGPR163_VGPR164_VGPR165 %VGPR163_VGPR164_VGPR165_VGPR166 %VGPR164_VGPR165_VGPR166_VGPR167 %VGPR165_VGPR166_VGPR167_VGPR168 %VGPR166_VGPR167_VGPR168_VGPR169 %VGPR167_VGPR168_VGPR169_VGPR170 %VGPR168_VGPR169_VGPR170_VGPR171 %VGPR169_VGPR170_VGPR171_VGPR172 %VGPR170_VGPR171_VGPR172_VGPR173 %VGPR171_VGPR172_VGPR173_VGPR174 %VGPR172_VGPR173_VGPR174_VGPR175 %VGPR173_VGPR174_VGPR175_VGPR176 %VGPR174_VGPR175_VGPR176_VGPR177 %VGPR175_VGPR176_VGPR177_VGPR178 %VGPR176_VGPR177_VGPR178_VGPR179 %VGPR177_VGPR178_VGPR179_VGPR180 %VGPR178_VGPR179_VGPR180_VGPR181 %VGPR179_VGPR180_VGPR181_VGPR182 %VGPR180_VGPR181_VGPR182_VGPR183 %VGPR181_VGPR182_VGPR183_VGPR184 %VGPR182_VGPR183_VGPR184_VGPR185 %VGPR183_VGPR184_VGPR185_VGPR186 %VGPR184_VGPR185_VGPR186_VGPR187 %VGPR185_VGPR186_VGPR187_VGPR188 %VGPR186_VGPR187_VGPR188_VGPR189 %VGPR187_VGPR188_VGPR189_VGPR190 %VGPR188_VGPR189_VGPR190_VGPR191 %VGPR189_VGPR190_VGPR191_VGPR192 %VGPR190_VGPR191_VGPR192_VGPR193 %VGPR191_VGPR192_VGPR193_VGPR194 %VGPR192_VGPR193_VGPR194_VGPR195 %VGPR193_VGPR194_VGPR195_VGPR196 %VGPR194_VGPR195_VGPR196_VGPR197 %VGPR195_VGPR196_VGPR197_VGPR198 %VGPR196_VGPR197_VGPR198_VGPR199 %VGPR197_VGPR198_VGPR199_VGPR200 %VGPR198_VGPR199_VGPR200_VGPR201 %VGPR199_VGPR200_VGPR201_VGPR202 %VGPR200_VGPR201_VGPR202_VGPR203 %VGPR201_VGPR202_VGPR203_VGPR204 %VGPR202_VGPR203_VGPR204_VGPR205 %VGPR203_VGPR204_VGPR205_VGPR206 %VGPR204_VGPR205_VGPR206_VGPR207 %VGPR205_VGPR206_VGPR207_VGPR208 %VGPR206_VGPR207_VGPR208_VGPR209 %VGPR207_VGPR208_VGPR209_VGPR210 %VGPR208_VGPR209_VGPR210_VGPR211 %VGPR209_VGPR210_VGPR211_VGPR212 %VGPR210_VGPR211_VGPR212_VGPR213 %VGPR211_VGPR212_VGPR213_VGPR214 %VGPR212_VGPR213_VGPR214_VGPR215 %VGPR213_VGPR214_VGPR215_VGPR216 %VGPR214_VGPR215_VGPR216_VGPR217 %VGPR215_VGPR216_VGPR217_VGPR218 %VGPR216_VGPR217_VGPR218_VGPR219 %VGPR217_VGPR218_VGPR219_VGPR220 %VGPR218_VGPR219_VGPR220_VGPR221 %VGPR219_VGPR220_VGPR221_VGPR222 %VGPR220_VGPR221_VGPR222_VGPR223 %VGPR221_VGPR222_VGPR223_VGPR224 %VGPR222_VGPR223_VGPR224_VGPR225 %VGPR223_VGPR224_VGPR225_VGPR226 %VGPR224_VGPR225_VGPR226_VGPR227 %VGPR225_VGPR226_VGPR227_VGPR228 %VGPR226_VGPR227_VGPR228_VGPR229 %VGPR227_VGPR228_VGPR229_VGPR230 %VGPR228_VGPR229_VGPR230_VGPR231 %VGPR229_VGPR230_VGPR231_VGPR232 %VGPR230_VGPR231_VGPR232_VGPR233 %VGPR231_VGPR232_VGPR233_VGPR234 %VGPR232_VGPR233_VGPR234_VGPR235 %VGPR233_VGPR234_VGPR235_VGPR236 %VGPR234_VGPR235_VGPR236_VGPR237 %VGPR235_VGPR236_VGPR237_VGPR238 %VGPR236_VGPR237_VGPR238_VGPR239 %VGPR237_VGPR238_VGPR239_VGPR240 %VGPR238_VGPR239_VGPR240_VGPR241 %VGPR239_VGPR240_VGPR241_VGPR242 %VGPR240_VGPR241_VGPR242_VGPR243 %VGPR241_VGPR242_VGPR243_VGPR244 %VGPR242_VGPR243_VGPR244_VGPR245 %VGPR243_VGPR244_VGPR245_VGPR246 %VGPR244_VGPR245_VGPR246_VGPR247 %VGPR245_VGPR246_VGPR247_VGPR248 %VGPR246_VGPR247_VGPR248_VGPR249 %VGPR247_VGPR248_VGPR249_VGPR250 %VGPR248_VGPR249_VGPR250_VGPR251 %VGPR249_VGPR250_VGPR251_VGPR252 %VGPR250_VGPR251_VGPR252_VGPR253 %VGPR251_VGPR252_VGPR253_VGPR254 %VGPR252_VGPR253_VGPR254_VGPR255 ]
		updated: 2032B	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg11; VReg_128:%vreg562 VReg_64:%vreg11
		updated: 9728B	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg824; VReg_128:%vreg562 VReg_64:%vreg824
		updated: 3712B	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg148 VReg_128:%vreg562
		updated: 3776B	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg148 VReg_128:%vreg562
		updated: 3840B	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg148 VReg_128:%vreg562
		updated: 3904B	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg148 VReg_128:%vreg562
		updated: 3968B	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg148 VReg_128:%vreg562
		updated: 4032B	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg148 VReg_128:%vreg562
		updated: 4096B	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg148 VReg_128:%vreg562
		updated: 4160B	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg148, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg148 VReg_128:%vreg562
		updated: 9440B	%vreg819<def> = COPY %vreg562:sub0; VReg_32:%vreg819 VReg_128:%vreg562
		updated: 9456B	%vreg825<def> = COPY %vreg562:sub1; VReg_32:%vreg825 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4320r:0)[4320r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4320r 2@2032r 3@9728r
4320B	%vreg562:sub2_sub3<def> = COPY %vreg564; VReg_128:%vreg562 VReg_64:%vreg564
	Considering merging to VReg_128 with %vreg564 in %vreg562:sub2_sub3
		RHS = %vreg564 [4288r,4320r:0)  0@4288r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4320r:0)[4320r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4320r 2@2032r 3@9728r
		merge %vreg562:1@4320r into %vreg564:0@4288r --> @4288r
		conflict at %vreg564:0@4288r
		taints local %vreg562:0@3552B to 4320r
		pruned %vreg562 at 4288r: %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4320r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4320r 2@2032r 3@9728r
		erased:	4320r	%vreg562:sub2_sub3<def> = COPY %vreg564; VReg_128:%vreg562 VReg_64:%vreg564
		restoring liveness to 2 points: %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		updated: 4288B	%vreg562:sub2_sub3<def> = COPY %vreg148:sub2_sub3; VReg_128:%vreg562 SReg_128:%vreg148
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
4336B	%vreg187<def> = COPY %vreg183; VReg_64:%vreg187 SGPR_64:%vreg183
	Not coalescable.
4352B	%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg677
		RHS = %vreg677 [4352r,4368r:0)  0@4352r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg677:0@4352r into %vreg562:1@4288r --> @4288r
		erased:	4352r	%vreg677<def> = COPY %vreg562; VReg_128:%vreg677,%vreg562
		updated: 4368B	%vreg678<def> = COPY %vreg562:sub0; VReg_32:%vreg678 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
4368B	%vreg678<def> = COPY %vreg562:sub0; VReg_32:%vreg678 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg678 in %vreg562:sub0
		RHS = %vreg678 [4368r,4480r:0)  0@4368r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg678:0@4368r into %vreg562:1@4288r --> @4288r
		erased:	4368r	%vreg678<def> = COPY %vreg562:sub0; VReg_32:%vreg678 VReg_128:%vreg562
		updated: 4480B	%vreg670<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg682, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670,%vreg682 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
4384B	%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg679
		RHS = %vreg679 [4384r,4400r:0)  0@4384r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg679:0@4384r into %vreg562:1@4288r --> @4288r
		erased:	4384r	%vreg679<def> = COPY %vreg562; VReg_128:%vreg679,%vreg562
		updated: 4400B	%vreg680<def> = COPY %vreg562:sub1; VReg_32:%vreg680 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
4400B	%vreg680<def> = COPY %vreg562:sub1; VReg_32:%vreg680 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg680 in %vreg562:sub1
		RHS = %vreg680 [4400r,4496r:0)  0@4400r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg680:0@4400r into %vreg562:1@4288r --> @4288r
		erased:	4400r	%vreg680<def> = COPY %vreg562:sub1; VReg_32:%vreg680 VReg_128:%vreg562
		updated: 4496B	%vreg671<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg684, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg671,%vreg684 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
4416B	%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
	Considering merging to VReg_64 with %vreg187 in %vreg681
		RHS = %vreg187 [4336r,4448r:0)  0@4336r
		LHS = %vreg681 [4416r,4432r:0)  0@4416r
		merge %vreg681:0@4416r into %vreg187:0@4336r --> @4336r
		erased:	4416r	%vreg681<def> = COPY %vreg187; VReg_64:%vreg681,%vreg187
		updated: 4336B	%vreg681<def> = COPY %vreg183; VReg_64:%vreg681 SGPR_64:%vreg183
		updated: 4448B	%vreg683<def> = COPY %vreg681; VReg_64:%vreg683,%vreg681
	Joined. Result = %vreg681 [4336r,4448r:0)  0@4336r
4432B	%vreg682<def> = COPY %vreg681:sub0; VReg_32:%vreg682 VReg_64:%vreg681
	Considering merging to VReg_64 with %vreg682 in %vreg681:sub0
		RHS = %vreg682 [4432r,4480r:0)  0@4432r
		LHS = %vreg681 [4336r,4448r:0)  0@4336r
		merge %vreg682:0@4432r into %vreg681:0@4336r --> @4336r
		erased:	4432r	%vreg682<def> = COPY %vreg681:sub0; VReg_32:%vreg682 VReg_64:%vreg681
		updated: 4480B	%vreg670<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg681:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670 VReg_128:%vreg562 VReg_64:%vreg681
	Joined. Result = %vreg681 [4336r,4480r:0)  0@4336r
4448B	%vreg683<def> = COPY %vreg681; VReg_64:%vreg683,%vreg681
	Considering merging to VReg_64 with %vreg681 in %vreg683
		RHS = %vreg681 [4336r,4480r:0)  0@4336r
		LHS = %vreg683 [4448r,4464r:0)  0@4448r
		merge %vreg683:0@4448r into %vreg681:0@4336r --> @4336r
		erased:	4448r	%vreg683<def> = COPY %vreg681; VReg_64:%vreg683,%vreg681
		updated: 4336B	%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
		updated: 4480B	%vreg670<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg670 VReg_128:%vreg562 VReg_64:%vreg683
	Joined. Result = %vreg683 [4336r,4480r:0)  0@4336r
4464B	%vreg684<def> = COPY %vreg683:sub1; VReg_32:%vreg684 VReg_64:%vreg683
	Considering merging to VReg_64 with %vreg684 in %vreg683:sub1
		RHS = %vreg684 [4464r,4496r:0)  0@4464r
		LHS = %vreg683 [4336r,4480r:0)  0@4336r
		merge %vreg684:0@4464r into %vreg683:0@4336r --> @4336r
		erased:	4464r	%vreg684<def> = COPY %vreg683:sub1; VReg_32:%vreg684 VReg_64:%vreg683
		updated: 4496B	%vreg671<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg671 VReg_128:%vreg562 VReg_64:%vreg683
	Joined. Result = %vreg683 [4336r,4496r:0)  0@4336r
4512B	%vreg672:sub0<def,read-undef> = COPY %vreg670; VReg_64:%vreg672 VReg_32:%vreg670
	Considering merging to VReg_64 with %vreg670 in %vreg672:sub0
		RHS = %vreg670 [4480r,4512r:0)  0@4480r
		LHS = %vreg672 [4512r,4528r:1)[4528r,4592r:0)  0@4528r 1@4512r
		merge %vreg672:1@4512r into %vreg670:0@4480r --> @4480r
		erased:	4512r	%vreg672:sub0<def,read-undef> = COPY %vreg670; VReg_64:%vreg672 VReg_32:%vreg670
		updated: 4480B	%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
	Joined. Result = %vreg672 [4480r,4528r:0)[4528r,4592r:1)  0@4480r 1@4528r
4528B	%vreg672:sub1<def> = COPY %vreg671; VReg_64:%vreg672 VReg_32:%vreg671
	Considering merging to VReg_64 with %vreg671 in %vreg672:sub1
		RHS = %vreg671 [4496r,4528r:0)  0@4496r
		LHS = %vreg672 [4480r,4528r:0)[4528r,4592r:1)  0@4480r 1@4528r
		merge %vreg672:1@4528r into %vreg671:0@4496r --> @4496r
		pruned %vreg672 at 4496r: %vreg672 [4480r,4496r:0)[4528r,4592r:1)  0@4480r 1@4528r
		erased:	4528r	%vreg672:sub1<def> = COPY %vreg671; VReg_64:%vreg672 VReg_32:%vreg671
		restoring liveness to 2 points: %vreg672 [4480r,4496r:0)[4496r,4592r:1)  0@4480r 1@4496r
		updated: 4496B	%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
	Joined. Result = %vreg672 [4480r,4496r:0)[4496r,4592r:1)  0@4480r 1@4496r
4544B	%vreg676:sub0_sub1<def,read-undef> = COPY %vreg148:sub0_sub1; SReg_128:%vreg676,%vreg148
	Considering merging to SReg_128 with %vreg148 in %vreg676
		RHS = %vreg148 [1728r,1792r:0)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:1)  0@1728r 1@3552B-phi 2@1792r 3@1808r
		LHS = %vreg676 [4544r,4560r:2)[4560r,4576r:1)[4576r,8480r:0)  0@4576r 1@4560r 2@4544r
		merge %vreg676:2@4544r into %vreg148:1@3552B --> @3552B
		merge %vreg676:1@4560r into %vreg148:1@3552B --> @3552B
		merge %vreg676:0@4576r into %vreg148:1@3552B --> @3552B
		erased:	4576r	%vreg676:sub3<def> = COPY %vreg148:sub3; SReg_128:%vreg676,%vreg148
		erased:	4560r	%vreg676:sub2<def> = COPY %vreg148:sub2; SReg_128:%vreg676,%vreg148
		erased:	4544r	%vreg676:sub0_sub1<def,read-undef> = COPY %vreg148:sub0_sub1; SReg_128:%vreg676,%vreg148
		updated: 1792B	%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
		updated: 1808B	%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
		updated: 1728B	%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
		updated: 3712B	%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
		updated: 3728B	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg852, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_64:%vreg852
		updated: 3776B	%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
		updated: 3792B	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg852, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_64:%vreg852
		updated: 3840B	%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
		updated: 3856B	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg852, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_64:%vreg852
		updated: 3904B	%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
		updated: 3920B	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg852, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_64:%vreg852
		updated: 3968B	%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
		updated: 3984B	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg852, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_64:%vreg852
		updated: 4032B	%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
		updated: 4048B	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg852, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_64:%vreg852
		updated: 4096B	%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
		updated: 4112B	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg852, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_64:%vreg852
		updated: 4160B	%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
		updated: 4176B	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg852, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_64:%vreg852
		updated: 1744B	%vreg93<def> = COPY %vreg676:sub0_sub1; SGPR_64:%vreg93 SReg_128:%vreg676
		updated: 4288B	%vreg562:sub2_sub3<def> = COPY %vreg676:sub2_sub3; VReg_128:%vreg562 SReg_128:%vreg676
		updated: 4640B	%vreg689<def> = COPY %vreg676:sub2_sub3; VReg_64:%vreg689 SReg_128:%vreg676
	Joined. Result = %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
4608B	%vreg685<def> = COPY %vreg852; VReg_64:%vreg685,%vreg852
	Considering merging to VReg_64 with %vreg852 in %vreg685
		RHS = %vreg685 [4608r,4624r:0)  0@4608r
		LHS = %vreg852 [2016r,2096B:0)[3552B,9344r:2)[9712r,9808B:1)  0@2016r 1@9712r 2@3552B-phi
		merge %vreg685:0@4608r into %vreg852:2@3552B --> @3552B
		erased:	4608r	%vreg685<def> = COPY %vreg852; VReg_64:%vreg685,%vreg852
		updated: 4624B	%vreg686<def> = COPY %vreg852; VReg_64:%vreg686,%vreg852
	Joined. Result = %vreg852 [2016r,2096B:0)[3552B,9344r:2)[9712r,9808B:1)  0@2016r 1@9712r 2@3552B-phi
4624B	%vreg686<def> = COPY %vreg852; VReg_64:%vreg686,%vreg852
	Considering merging to VReg_64 with %vreg852 in %vreg686
		RHS = %vreg686 [4624r,4656r:0)  0@4624r
		LHS = %vreg852 [2016r,2096B:0)[3552B,9344r:2)[9712r,9808B:1)  0@2016r 1@9712r 2@3552B-phi
		merge %vreg686:0@4624r into %vreg852:2@3552B --> @3552B
		erased:	4624r	%vreg686<def> = COPY %vreg852; VReg_64:%vreg686,%vreg852
		updated: 4656B	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg852; VReg_128:%vreg687 VReg_64:%vreg852
	Joined. Result = %vreg852 [2016r,2096B:0)[3552B,9344r:2)[9712r,9808B:1)  0@2016r 1@9712r 2@3552B-phi
4640B	%vreg689<def> = COPY %vreg676:sub2_sub3; VReg_64:%vreg689 SReg_128:%vreg676
	Not coalescable.
4656B	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg852; VReg_128:%vreg687 VReg_64:%vreg852
	Considering merging to VReg_128 with %vreg852 in %vreg687:sub0_sub1
		RHS = %vreg852 [2016r,2096B:0)[3552B,9344r:2)[9712r,9808B:1)  0@2016r 1@9712r 2@3552B-phi
		LHS = %vreg687 [4656r,4672r:1)[4672r,8320r:0)  0@4672r 1@4656r
		merge %vreg687:1@4656r into %vreg852:2@3552B --> @3552B
		pruned %vreg852 at 4672r: %vreg852 [2016r,2096B:0)[3552B,4672r:2)[9712r,9808B:1)  0@2016r 1@9712r 2@3552B-phi
		pruned all of %vreg687 at 4656r: %vreg687 [4672r,8320r:0)  0@4672r 1@4656r
		erased:	4656r	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg852; VReg_128:%vreg687 VReg_64:%vreg852
		restoring liveness to 3 points: %vreg687 [2016r,2096B:2)[3552B,4672r:0)[4672r,8320r:1)[9712r,9808B:3)  0@3552B-phi 1@4672r 2@2016r 3@9712r
		updated: 2016B	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg12; VReg_128:%vreg687 VReg_64:%vreg12
		updated: 9712B	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg815; VReg_128:%vreg687 VReg_64:%vreg815
		updated: 3728B	%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
		updated: 3792B	%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
		updated: 3856B	%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
		updated: 3920B	%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
		updated: 3984B	%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
		updated: 4048B	%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
		updated: 4112B	%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
		updated: 4176B	%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
		updated: 9312B	%vreg810<def> = COPY %vreg687:sub0; VReg_32:%vreg810 VReg_128:%vreg687
		updated: 9344B	%vreg816<def> = COPY %vreg687:sub1; VReg_32:%vreg816 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4672r:0)[4672r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4672r 2@2016r 3@9712r
4672B	%vreg687:sub2_sub3<def> = COPY %vreg689; VReg_128:%vreg687 VReg_64:%vreg689
	Considering merging to VReg_128 with %vreg689 in %vreg687:sub2_sub3
		RHS = %vreg689 [4640r,4672r:0)  0@4640r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4672r:0)[4672r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4672r 2@2016r 3@9712r
		merge %vreg687:1@4672r into %vreg689:0@4640r --> @4640r
		conflict at %vreg689:0@4640r
		taints local %vreg687:0@3552B to 4672r
		pruned %vreg687 at 4640r: %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4672r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4672r 2@2016r 3@9712r
		erased:	4672r	%vreg687:sub2_sub3<def> = COPY %vreg689; VReg_128:%vreg687 VReg_64:%vreg689
		restoring liveness to 2 points: %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		updated: 4640B	%vreg687:sub2_sub3<def> = COPY %vreg676:sub2_sub3; VReg_128:%vreg687 SReg_128:%vreg676
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
4688B	%vreg191<def> = COPY %vreg183; VReg_64:%vreg191 SGPR_64:%vreg183
	Not coalescable.
4704B	%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg802
		RHS = %vreg802 [4704r,4720r:0)  0@4704r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg802:0@4704r into %vreg687:1@4640r --> @4640r
		erased:	4704r	%vreg802<def> = COPY %vreg687; VReg_128:%vreg802,%vreg687
		updated: 4720B	%vreg803<def> = COPY %vreg687:sub0; VReg_32:%vreg803 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
4720B	%vreg803<def> = COPY %vreg687:sub0; VReg_32:%vreg803 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg803 in %vreg687:sub0
		RHS = %vreg803 [4720r,4832r:0)  0@4720r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg803:0@4720r into %vreg687:1@4640r --> @4640r
		erased:	4720r	%vreg803<def> = COPY %vreg687:sub0; VReg_32:%vreg803 VReg_128:%vreg687
		updated: 4832B	%vreg795<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg807, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795,%vreg807 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
4736B	%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg804
		RHS = %vreg804 [4736r,4752r:0)  0@4736r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg804:0@4736r into %vreg687:1@4640r --> @4640r
		erased:	4736r	%vreg804<def> = COPY %vreg687; VReg_128:%vreg804,%vreg687
		updated: 4752B	%vreg805<def> = COPY %vreg687:sub1; VReg_32:%vreg805 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
4752B	%vreg805<def> = COPY %vreg687:sub1; VReg_32:%vreg805 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg805 in %vreg687:sub1
		RHS = %vreg805 [4752r,4848r:0)  0@4752r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg805:0@4752r into %vreg687:1@4640r --> @4640r
		erased:	4752r	%vreg805<def> = COPY %vreg687:sub1; VReg_32:%vreg805 VReg_128:%vreg687
		updated: 4848B	%vreg796<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg809, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg796,%vreg809 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
4768B	%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
	Considering merging to VReg_64 with %vreg191 in %vreg806
		RHS = %vreg191 [4688r,4800r:0)  0@4688r
		LHS = %vreg806 [4768r,4784r:0)  0@4768r
		merge %vreg806:0@4768r into %vreg191:0@4688r --> @4688r
		erased:	4768r	%vreg806<def> = COPY %vreg191; VReg_64:%vreg806,%vreg191
		updated: 4688B	%vreg806<def> = COPY %vreg183; VReg_64:%vreg806 SGPR_64:%vreg183
		updated: 4800B	%vreg808<def> = COPY %vreg806; VReg_64:%vreg808,%vreg806
	Joined. Result = %vreg806 [4688r,4800r:0)  0@4688r
4784B	%vreg807<def> = COPY %vreg806:sub0; VReg_32:%vreg807 VReg_64:%vreg806
	Considering merging to VReg_64 with %vreg807 in %vreg806:sub0
		RHS = %vreg807 [4784r,4832r:0)  0@4784r
		LHS = %vreg806 [4688r,4800r:0)  0@4688r
		merge %vreg807:0@4784r into %vreg806:0@4688r --> @4688r
		erased:	4784r	%vreg807<def> = COPY %vreg806:sub0; VReg_32:%vreg807 VReg_64:%vreg806
		updated: 4832B	%vreg795<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg806:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795 VReg_128:%vreg687 VReg_64:%vreg806
	Joined. Result = %vreg806 [4688r,4832r:0)  0@4688r
4800B	%vreg808<def> = COPY %vreg806; VReg_64:%vreg808,%vreg806
	Considering merging to VReg_64 with %vreg806 in %vreg808
		RHS = %vreg806 [4688r,4832r:0)  0@4688r
		LHS = %vreg808 [4800r,4816r:0)  0@4800r
		merge %vreg808:0@4800r into %vreg806:0@4688r --> @4688r
		erased:	4800r	%vreg808<def> = COPY %vreg806; VReg_64:%vreg808,%vreg806
		updated: 4688B	%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
		updated: 4832B	%vreg795<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg795 VReg_128:%vreg687 VReg_64:%vreg808
	Joined. Result = %vreg808 [4688r,4832r:0)  0@4688r
4816B	%vreg809<def> = COPY %vreg808:sub1; VReg_32:%vreg809 VReg_64:%vreg808
	Considering merging to VReg_64 with %vreg809 in %vreg808:sub1
		RHS = %vreg809 [4816r,4848r:0)  0@4816r
		LHS = %vreg808 [4688r,4832r:0)  0@4688r
		merge %vreg809:0@4816r into %vreg808:0@4688r --> @4688r
		erased:	4816r	%vreg809<def> = COPY %vreg808:sub1; VReg_32:%vreg809 VReg_64:%vreg808
		updated: 4848B	%vreg796<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg796 VReg_128:%vreg687 VReg_64:%vreg808
	Joined. Result = %vreg808 [4688r,4848r:0)  0@4688r
4864B	%vreg797:sub0<def,read-undef> = COPY %vreg795; VReg_64:%vreg797 VReg_32:%vreg795
	Considering merging to VReg_64 with %vreg795 in %vreg797:sub0
		RHS = %vreg795 [4832r,4864r:0)  0@4832r
		LHS = %vreg797 [4864r,4880r:1)[4880r,4896r:0)  0@4880r 1@4864r
		merge %vreg797:1@4864r into %vreg795:0@4832r --> @4832r
		erased:	4864r	%vreg797:sub0<def,read-undef> = COPY %vreg795; VReg_64:%vreg797 VReg_32:%vreg795
		updated: 4832B	%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
	Joined. Result = %vreg797 [4832r,4880r:0)[4880r,4896r:1)  0@4832r 1@4880r
4880B	%vreg797:sub1<def> = COPY %vreg796; VReg_64:%vreg797 VReg_32:%vreg796
	Considering merging to VReg_64 with %vreg796 in %vreg797:sub1
		RHS = %vreg796 [4848r,4880r:0)  0@4848r
		LHS = %vreg797 [4832r,4880r:0)[4880r,4896r:1)  0@4832r 1@4880r
		merge %vreg797:1@4880r into %vreg796:0@4848r --> @4848r
		pruned %vreg797 at 4848r: %vreg797 [4832r,4848r:0)[4880r,4896r:1)  0@4832r 1@4880r
		erased:	4880r	%vreg797:sub1<def> = COPY %vreg796; VReg_64:%vreg797 VReg_32:%vreg796
		restoring liveness to 2 points: %vreg797 [4832r,4848r:0)[4848r,4896r:1)  0@4832r 1@4848r
		updated: 4848B	%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
	Joined. Result = %vreg797 [4832r,4848r:0)[4848r,4896r:1)  0@4832r 1@4848r
4944B	%vreg195:sub0<def,read-undef> = COPY %vreg194; SGPR_64:%vreg195 SReg_32:%vreg194
	Considering merging to SGPR_64 with %vreg194 in %vreg195:sub0
		RHS = %vreg194 [1856r,2096B:0)[3552B,9808B:0)  0@1856r
		LHS = %vreg195 [4944r,4960r:1)[4960r,5200r:0)  0@4960r 1@4944r
		merge %vreg195:1@4944r into %vreg194:0@1856r --> @1856r
		pruned %vreg194 at 4960r: %vreg194 [1856r,2096B:0)  0@1856r
		pruned all of %vreg195 at 4944r: %vreg195 [4960r,5200r:0)  0@4960r 1@4944r
		erased:	4944r	%vreg195:sub0<def,read-undef> = COPY %vreg194; SGPR_64:%vreg195 SReg_32:%vreg194
		restoring liveness to 4 points: %vreg195 [1856r,2096B:0)[4960r,5200r:1)  0@1856r 1@4960r
		updated: 1856B	%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
	Joined. Result = %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
4960B	%vreg195:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg195,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg195
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
		interference at %vreg195:0@1856r
	Interference!
4976B	%vreg197<def> = COPY %vreg195; VReg_64:%vreg197 SGPR_64:%vreg195
	Not coalescable.
4992B	%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg662
		RHS = %vreg662 [4992r,5008r:0)  0@4992r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg662:0@4992r into %vreg562:1@4288r --> @4288r
		erased:	4992r	%vreg662<def> = COPY %vreg562; VReg_128:%vreg662,%vreg562
		updated: 5008B	%vreg663<def> = COPY %vreg562:sub0; VReg_32:%vreg663 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
5008B	%vreg663<def> = COPY %vreg562:sub0; VReg_32:%vreg663 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg663 in %vreg562:sub0
		RHS = %vreg663 [5008r,5120r:0)  0@5008r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg663:0@5008r into %vreg562:1@4288r --> @4288r
		erased:	5008r	%vreg663<def> = COPY %vreg562:sub0; VReg_32:%vreg663 VReg_128:%vreg562
		updated: 5120B	%vreg655<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg667, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655,%vreg667 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
5024B	%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg664
		RHS = %vreg664 [5024r,5040r:0)  0@5024r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg664:0@5024r into %vreg562:1@4288r --> @4288r
		erased:	5024r	%vreg664<def> = COPY %vreg562; VReg_128:%vreg664,%vreg562
		updated: 5040B	%vreg665<def> = COPY %vreg562:sub1; VReg_32:%vreg665 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
5040B	%vreg665<def> = COPY %vreg562:sub1; VReg_32:%vreg665 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg665 in %vreg562:sub1
		RHS = %vreg665 [5040r,5136r:0)  0@5040r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg665:0@5040r into %vreg562:1@4288r --> @4288r
		erased:	5040r	%vreg665<def> = COPY %vreg562:sub1; VReg_32:%vreg665 VReg_128:%vreg562
		updated: 5136B	%vreg656<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg669, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg656,%vreg669 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
5056B	%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
	Considering merging to VReg_64 with %vreg197 in %vreg666
		RHS = %vreg197 [4976r,5088r:0)  0@4976r
		LHS = %vreg666 [5056r,5072r:0)  0@5056r
		merge %vreg666:0@5056r into %vreg197:0@4976r --> @4976r
		erased:	5056r	%vreg666<def> = COPY %vreg197; VReg_64:%vreg666,%vreg197
		updated: 4976B	%vreg666<def> = COPY %vreg195; VReg_64:%vreg666 SGPR_64:%vreg195
		updated: 5088B	%vreg668<def> = COPY %vreg666; VReg_64:%vreg668,%vreg666
	Joined. Result = %vreg666 [4976r,5088r:0)  0@4976r
5072B	%vreg667<def> = COPY %vreg666:sub0; VReg_32:%vreg667 VReg_64:%vreg666
	Considering merging to VReg_64 with %vreg667 in %vreg666:sub0
		RHS = %vreg667 [5072r,5120r:0)  0@5072r
		LHS = %vreg666 [4976r,5088r:0)  0@4976r
		merge %vreg667:0@5072r into %vreg666:0@4976r --> @4976r
		erased:	5072r	%vreg667<def> = COPY %vreg666:sub0; VReg_32:%vreg667 VReg_64:%vreg666
		updated: 5120B	%vreg655<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg666:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655 VReg_128:%vreg562 VReg_64:%vreg666
	Joined. Result = %vreg666 [4976r,5120r:0)  0@4976r
5088B	%vreg668<def> = COPY %vreg666; VReg_64:%vreg668,%vreg666
	Considering merging to VReg_64 with %vreg666 in %vreg668
		RHS = %vreg666 [4976r,5120r:0)  0@4976r
		LHS = %vreg668 [5088r,5104r:0)  0@5088r
		merge %vreg668:0@5088r into %vreg666:0@4976r --> @4976r
		erased:	5088r	%vreg668<def> = COPY %vreg666; VReg_64:%vreg668,%vreg666
		updated: 4976B	%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
		updated: 5120B	%vreg655<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg655 VReg_128:%vreg562 VReg_64:%vreg668
	Joined. Result = %vreg668 [4976r,5120r:0)  0@4976r
5104B	%vreg669<def> = COPY %vreg668:sub1; VReg_32:%vreg669 VReg_64:%vreg668
	Considering merging to VReg_64 with %vreg669 in %vreg668:sub1
		RHS = %vreg669 [5104r,5136r:0)  0@5104r
		LHS = %vreg668 [4976r,5120r:0)  0@4976r
		merge %vreg669:0@5104r into %vreg668:0@4976r --> @4976r
		erased:	5104r	%vreg669<def> = COPY %vreg668:sub1; VReg_32:%vreg669 VReg_64:%vreg668
		updated: 5136B	%vreg656<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg656 VReg_128:%vreg562 VReg_64:%vreg668
	Joined. Result = %vreg668 [4976r,5136r:0)  0@4976r
5152B	%vreg657:sub0<def,read-undef> = COPY %vreg655; VReg_64:%vreg657 VReg_32:%vreg655
	Considering merging to VReg_64 with %vreg655 in %vreg657:sub0
		RHS = %vreg655 [5120r,5152r:0)  0@5120r
		LHS = %vreg657 [5152r,5168r:1)[5168r,5184r:0)  0@5168r 1@5152r
		merge %vreg657:1@5152r into %vreg655:0@5120r --> @5120r
		erased:	5152r	%vreg657:sub0<def,read-undef> = COPY %vreg655; VReg_64:%vreg657 VReg_32:%vreg655
		updated: 5120B	%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
	Joined. Result = %vreg657 [5120r,5168r:0)[5168r,5184r:1)  0@5120r 1@5168r
5168B	%vreg657:sub1<def> = COPY %vreg656; VReg_64:%vreg657 VReg_32:%vreg656
	Considering merging to VReg_64 with %vreg656 in %vreg657:sub1
		RHS = %vreg656 [5136r,5168r:0)  0@5136r
		LHS = %vreg657 [5120r,5168r:0)[5168r,5184r:1)  0@5120r 1@5168r
		merge %vreg657:1@5168r into %vreg656:0@5136r --> @5136r
		pruned %vreg657 at 5136r: %vreg657 [5120r,5136r:0)[5168r,5184r:1)  0@5120r 1@5168r
		erased:	5168r	%vreg657:sub1<def> = COPY %vreg656; VReg_64:%vreg657 VReg_32:%vreg656
		restoring liveness to 2 points: %vreg657 [5120r,5136r:0)[5136r,5184r:1)  0@5120r 1@5136r
		updated: 5136B	%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
	Joined. Result = %vreg657 [5120r,5136r:0)[5136r,5184r:1)  0@5120r 1@5136r
5200B	%vreg199<def> = COPY %vreg195; VReg_64:%vreg199 SGPR_64:%vreg195
	Not coalescable.
5216B	%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg787
		RHS = %vreg787 [5216r,5232r:0)  0@5216r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg787:0@5216r into %vreg687:1@4640r --> @4640r
		erased:	5216r	%vreg787<def> = COPY %vreg687; VReg_128:%vreg787,%vreg687
		updated: 5232B	%vreg788<def> = COPY %vreg687:sub0; VReg_32:%vreg788 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
5232B	%vreg788<def> = COPY %vreg687:sub0; VReg_32:%vreg788 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg788 in %vreg687:sub0
		RHS = %vreg788 [5232r,5344r:0)  0@5232r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg788:0@5232r into %vreg687:1@4640r --> @4640r
		erased:	5232r	%vreg788<def> = COPY %vreg687:sub0; VReg_32:%vreg788 VReg_128:%vreg687
		updated: 5344B	%vreg780<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg792, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780,%vreg792 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
5248B	%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg789
		RHS = %vreg789 [5248r,5264r:0)  0@5248r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg789:0@5248r into %vreg687:1@4640r --> @4640r
		erased:	5248r	%vreg789<def> = COPY %vreg687; VReg_128:%vreg789,%vreg687
		updated: 5264B	%vreg790<def> = COPY %vreg687:sub1; VReg_32:%vreg790 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
5264B	%vreg790<def> = COPY %vreg687:sub1; VReg_32:%vreg790 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg790 in %vreg687:sub1
		RHS = %vreg790 [5264r,5360r:0)  0@5264r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg790:0@5264r into %vreg687:1@4640r --> @4640r
		erased:	5264r	%vreg790<def> = COPY %vreg687:sub1; VReg_32:%vreg790 VReg_128:%vreg687
		updated: 5360B	%vreg781<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg794, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg781,%vreg794 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
5280B	%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
	Considering merging to VReg_64 with %vreg199 in %vreg791
		RHS = %vreg199 [5200r,5312r:0)  0@5200r
		LHS = %vreg791 [5280r,5296r:0)  0@5280r
		merge %vreg791:0@5280r into %vreg199:0@5200r --> @5200r
		erased:	5280r	%vreg791<def> = COPY %vreg199; VReg_64:%vreg791,%vreg199
		updated: 5200B	%vreg791<def> = COPY %vreg195; VReg_64:%vreg791 SGPR_64:%vreg195
		updated: 5312B	%vreg793<def> = COPY %vreg791; VReg_64:%vreg793,%vreg791
	Joined. Result = %vreg791 [5200r,5312r:0)  0@5200r
5296B	%vreg792<def> = COPY %vreg791:sub0; VReg_32:%vreg792 VReg_64:%vreg791
	Considering merging to VReg_64 with %vreg792 in %vreg791:sub0
		RHS = %vreg792 [5296r,5344r:0)  0@5296r
		LHS = %vreg791 [5200r,5312r:0)  0@5200r
		merge %vreg792:0@5296r into %vreg791:0@5200r --> @5200r
		erased:	5296r	%vreg792<def> = COPY %vreg791:sub0; VReg_32:%vreg792 VReg_64:%vreg791
		updated: 5344B	%vreg780<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg791:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780 VReg_128:%vreg687 VReg_64:%vreg791
	Joined. Result = %vreg791 [5200r,5344r:0)  0@5200r
5312B	%vreg793<def> = COPY %vreg791; VReg_64:%vreg793,%vreg791
	Considering merging to VReg_64 with %vreg791 in %vreg793
		RHS = %vreg791 [5200r,5344r:0)  0@5200r
		LHS = %vreg793 [5312r,5328r:0)  0@5312r
		merge %vreg793:0@5312r into %vreg791:0@5200r --> @5200r
		erased:	5312r	%vreg793<def> = COPY %vreg791; VReg_64:%vreg793,%vreg791
		updated: 5200B	%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
		updated: 5344B	%vreg780<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg780 VReg_128:%vreg687 VReg_64:%vreg793
	Joined. Result = %vreg793 [5200r,5344r:0)  0@5200r
5328B	%vreg794<def> = COPY %vreg793:sub1; VReg_32:%vreg794 VReg_64:%vreg793
	Considering merging to VReg_64 with %vreg794 in %vreg793:sub1
		RHS = %vreg794 [5328r,5360r:0)  0@5328r
		LHS = %vreg793 [5200r,5344r:0)  0@5200r
		merge %vreg794:0@5328r into %vreg793:0@5200r --> @5200r
		erased:	5328r	%vreg794<def> = COPY %vreg793:sub1; VReg_32:%vreg794 VReg_64:%vreg793
		updated: 5360B	%vreg781<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg781 VReg_128:%vreg687 VReg_64:%vreg793
	Joined. Result = %vreg793 [5200r,5360r:0)  0@5200r
5376B	%vreg782:sub0<def,read-undef> = COPY %vreg780; VReg_64:%vreg782 VReg_32:%vreg780
	Considering merging to VReg_64 with %vreg780 in %vreg782:sub0
		RHS = %vreg780 [5344r,5376r:0)  0@5344r
		LHS = %vreg782 [5376r,5392r:1)[5392r,5408r:0)  0@5392r 1@5376r
		merge %vreg782:1@5376r into %vreg780:0@5344r --> @5344r
		erased:	5376r	%vreg782:sub0<def,read-undef> = COPY %vreg780; VReg_64:%vreg782 VReg_32:%vreg780
		updated: 5344B	%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
	Joined. Result = %vreg782 [5344r,5392r:0)[5392r,5408r:1)  0@5344r 1@5392r
5392B	%vreg782:sub1<def> = COPY %vreg781; VReg_64:%vreg782 VReg_32:%vreg781
	Considering merging to VReg_64 with %vreg781 in %vreg782:sub1
		RHS = %vreg781 [5360r,5392r:0)  0@5360r
		LHS = %vreg782 [5344r,5392r:0)[5392r,5408r:1)  0@5344r 1@5392r
		merge %vreg782:1@5392r into %vreg781:0@5360r --> @5360r
		pruned %vreg782 at 5360r: %vreg782 [5344r,5360r:0)[5392r,5408r:1)  0@5344r 1@5392r
		erased:	5392r	%vreg782:sub1<def> = COPY %vreg781; VReg_64:%vreg782 VReg_32:%vreg781
		restoring liveness to 2 points: %vreg782 [5344r,5360r:0)[5360r,5408r:1)  0@5344r 1@5360r
		updated: 5360B	%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
	Joined. Result = %vreg782 [5344r,5360r:0)[5360r,5408r:1)  0@5344r 1@5360r
5456B	%vreg203:sub0<def,read-undef> = COPY %vreg202; SGPR_64:%vreg203 SReg_32:%vreg202
	Considering merging to SGPR_64 with %vreg202 in %vreg203:sub0
		RHS = %vreg202 [1872r,2096B:0)[3552B,9808B:0)  0@1872r
		LHS = %vreg203 [5456r,5472r:1)[5472r,5712r:0)  0@5472r 1@5456r
		merge %vreg203:1@5456r into %vreg202:0@1872r --> @1872r
		pruned %vreg202 at 5472r: %vreg202 [1872r,2096B:0)  0@1872r
		pruned all of %vreg203 at 5456r: %vreg203 [5472r,5712r:0)  0@5472r 1@5456r
		erased:	5456r	%vreg203:sub0<def,read-undef> = COPY %vreg202; SGPR_64:%vreg203 SReg_32:%vreg202
		restoring liveness to 4 points: %vreg203 [1872r,2096B:0)[5472r,5712r:1)  0@1872r 1@5472r
		updated: 1872B	%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
	Joined. Result = %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
5472B	%vreg203:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg203,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg203
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
		interference at %vreg203:0@1872r
	Interference!
5488B	%vreg205<def> = COPY %vreg203; VReg_64:%vreg205 SGPR_64:%vreg203
	Not coalescable.
5504B	%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg647
		RHS = %vreg647 [5504r,5520r:0)  0@5504r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg647:0@5504r into %vreg562:1@4288r --> @4288r
		erased:	5504r	%vreg647<def> = COPY %vreg562; VReg_128:%vreg647,%vreg562
		updated: 5520B	%vreg648<def> = COPY %vreg562:sub0; VReg_32:%vreg648 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
5520B	%vreg648<def> = COPY %vreg562:sub0; VReg_32:%vreg648 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg648 in %vreg562:sub0
		RHS = %vreg648 [5520r,5632r:0)  0@5520r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg648:0@5520r into %vreg562:1@4288r --> @4288r
		erased:	5520r	%vreg648<def> = COPY %vreg562:sub0; VReg_32:%vreg648 VReg_128:%vreg562
		updated: 5632B	%vreg640<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg652, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640,%vreg652 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
5536B	%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg649
		RHS = %vreg649 [5536r,5552r:0)  0@5536r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg649:0@5536r into %vreg562:1@4288r --> @4288r
		erased:	5536r	%vreg649<def> = COPY %vreg562; VReg_128:%vreg649,%vreg562
		updated: 5552B	%vreg650<def> = COPY %vreg562:sub1; VReg_32:%vreg650 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
5552B	%vreg650<def> = COPY %vreg562:sub1; VReg_32:%vreg650 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg650 in %vreg562:sub1
		RHS = %vreg650 [5552r,5648r:0)  0@5552r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg650:0@5552r into %vreg562:1@4288r --> @4288r
		erased:	5552r	%vreg650<def> = COPY %vreg562:sub1; VReg_32:%vreg650 VReg_128:%vreg562
		updated: 5648B	%vreg641<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg654, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg641,%vreg654 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
5568B	%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
	Considering merging to VReg_64 with %vreg205 in %vreg651
		RHS = %vreg205 [5488r,5600r:0)  0@5488r
		LHS = %vreg651 [5568r,5584r:0)  0@5568r
		merge %vreg651:0@5568r into %vreg205:0@5488r --> @5488r
		erased:	5568r	%vreg651<def> = COPY %vreg205; VReg_64:%vreg651,%vreg205
		updated: 5488B	%vreg651<def> = COPY %vreg203; VReg_64:%vreg651 SGPR_64:%vreg203
		updated: 5600B	%vreg653<def> = COPY %vreg651; VReg_64:%vreg653,%vreg651
	Joined. Result = %vreg651 [5488r,5600r:0)  0@5488r
5584B	%vreg652<def> = COPY %vreg651:sub0; VReg_32:%vreg652 VReg_64:%vreg651
	Considering merging to VReg_64 with %vreg652 in %vreg651:sub0
		RHS = %vreg652 [5584r,5632r:0)  0@5584r
		LHS = %vreg651 [5488r,5600r:0)  0@5488r
		merge %vreg652:0@5584r into %vreg651:0@5488r --> @5488r
		erased:	5584r	%vreg652<def> = COPY %vreg651:sub0; VReg_32:%vreg652 VReg_64:%vreg651
		updated: 5632B	%vreg640<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg651:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640 VReg_128:%vreg562 VReg_64:%vreg651
	Joined. Result = %vreg651 [5488r,5632r:0)  0@5488r
5600B	%vreg653<def> = COPY %vreg651; VReg_64:%vreg653,%vreg651
	Considering merging to VReg_64 with %vreg651 in %vreg653
		RHS = %vreg651 [5488r,5632r:0)  0@5488r
		LHS = %vreg653 [5600r,5616r:0)  0@5600r
		merge %vreg653:0@5600r into %vreg651:0@5488r --> @5488r
		erased:	5600r	%vreg653<def> = COPY %vreg651; VReg_64:%vreg653,%vreg651
		updated: 5488B	%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
		updated: 5632B	%vreg640<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg640 VReg_128:%vreg562 VReg_64:%vreg653
	Joined. Result = %vreg653 [5488r,5632r:0)  0@5488r
5616B	%vreg654<def> = COPY %vreg653:sub1; VReg_32:%vreg654 VReg_64:%vreg653
	Considering merging to VReg_64 with %vreg654 in %vreg653:sub1
		RHS = %vreg654 [5616r,5648r:0)  0@5616r
		LHS = %vreg653 [5488r,5632r:0)  0@5488r
		merge %vreg654:0@5616r into %vreg653:0@5488r --> @5488r
		erased:	5616r	%vreg654<def> = COPY %vreg653:sub1; VReg_32:%vreg654 VReg_64:%vreg653
		updated: 5648B	%vreg641<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg641 VReg_128:%vreg562 VReg_64:%vreg653
	Joined. Result = %vreg653 [5488r,5648r:0)  0@5488r
5664B	%vreg642:sub0<def,read-undef> = COPY %vreg640; VReg_64:%vreg642 VReg_32:%vreg640
	Considering merging to VReg_64 with %vreg640 in %vreg642:sub0
		RHS = %vreg640 [5632r,5664r:0)  0@5632r
		LHS = %vreg642 [5664r,5680r:1)[5680r,5696r:0)  0@5680r 1@5664r
		merge %vreg642:1@5664r into %vreg640:0@5632r --> @5632r
		erased:	5664r	%vreg642:sub0<def,read-undef> = COPY %vreg640; VReg_64:%vreg642 VReg_32:%vreg640
		updated: 5632B	%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
	Joined. Result = %vreg642 [5632r,5680r:0)[5680r,5696r:1)  0@5632r 1@5680r
5680B	%vreg642:sub1<def> = COPY %vreg641; VReg_64:%vreg642 VReg_32:%vreg641
	Considering merging to VReg_64 with %vreg641 in %vreg642:sub1
		RHS = %vreg641 [5648r,5680r:0)  0@5648r
		LHS = %vreg642 [5632r,5680r:0)[5680r,5696r:1)  0@5632r 1@5680r
		merge %vreg642:1@5680r into %vreg641:0@5648r --> @5648r
		pruned %vreg642 at 5648r: %vreg642 [5632r,5648r:0)[5680r,5696r:1)  0@5632r 1@5680r
		erased:	5680r	%vreg642:sub1<def> = COPY %vreg641; VReg_64:%vreg642 VReg_32:%vreg641
		restoring liveness to 2 points: %vreg642 [5632r,5648r:0)[5648r,5696r:1)  0@5632r 1@5648r
		updated: 5648B	%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
	Joined. Result = %vreg642 [5632r,5648r:0)[5648r,5696r:1)  0@5632r 1@5648r
5712B	%vreg207<def> = COPY %vreg203; VReg_64:%vreg207 SGPR_64:%vreg203
	Not coalescable.
5728B	%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg772
		RHS = %vreg772 [5728r,5744r:0)  0@5728r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg772:0@5728r into %vreg687:1@4640r --> @4640r
		erased:	5728r	%vreg772<def> = COPY %vreg687; VReg_128:%vreg772,%vreg687
		updated: 5744B	%vreg773<def> = COPY %vreg687:sub0; VReg_32:%vreg773 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
5744B	%vreg773<def> = COPY %vreg687:sub0; VReg_32:%vreg773 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg773 in %vreg687:sub0
		RHS = %vreg773 [5744r,5856r:0)  0@5744r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg773:0@5744r into %vreg687:1@4640r --> @4640r
		erased:	5744r	%vreg773<def> = COPY %vreg687:sub0; VReg_32:%vreg773 VReg_128:%vreg687
		updated: 5856B	%vreg765<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg777, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765,%vreg777 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
5760B	%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg774
		RHS = %vreg774 [5760r,5776r:0)  0@5760r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg774:0@5760r into %vreg687:1@4640r --> @4640r
		erased:	5760r	%vreg774<def> = COPY %vreg687; VReg_128:%vreg774,%vreg687
		updated: 5776B	%vreg775<def> = COPY %vreg687:sub1; VReg_32:%vreg775 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
5776B	%vreg775<def> = COPY %vreg687:sub1; VReg_32:%vreg775 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg775 in %vreg687:sub1
		RHS = %vreg775 [5776r,5872r:0)  0@5776r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg775:0@5776r into %vreg687:1@4640r --> @4640r
		erased:	5776r	%vreg775<def> = COPY %vreg687:sub1; VReg_32:%vreg775 VReg_128:%vreg687
		updated: 5872B	%vreg766<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg779, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg766,%vreg779 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
5792B	%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
	Considering merging to VReg_64 with %vreg207 in %vreg776
		RHS = %vreg207 [5712r,5824r:0)  0@5712r
		LHS = %vreg776 [5792r,5808r:0)  0@5792r
		merge %vreg776:0@5792r into %vreg207:0@5712r --> @5712r
		erased:	5792r	%vreg776<def> = COPY %vreg207; VReg_64:%vreg776,%vreg207
		updated: 5712B	%vreg776<def> = COPY %vreg203; VReg_64:%vreg776 SGPR_64:%vreg203
		updated: 5824B	%vreg778<def> = COPY %vreg776; VReg_64:%vreg778,%vreg776
	Joined. Result = %vreg776 [5712r,5824r:0)  0@5712r
5808B	%vreg777<def> = COPY %vreg776:sub0; VReg_32:%vreg777 VReg_64:%vreg776
	Considering merging to VReg_64 with %vreg777 in %vreg776:sub0
		RHS = %vreg777 [5808r,5856r:0)  0@5808r
		LHS = %vreg776 [5712r,5824r:0)  0@5712r
		merge %vreg777:0@5808r into %vreg776:0@5712r --> @5712r
		erased:	5808r	%vreg777<def> = COPY %vreg776:sub0; VReg_32:%vreg777 VReg_64:%vreg776
		updated: 5856B	%vreg765<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg776:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765 VReg_128:%vreg687 VReg_64:%vreg776
	Joined. Result = %vreg776 [5712r,5856r:0)  0@5712r
5824B	%vreg778<def> = COPY %vreg776; VReg_64:%vreg778,%vreg776
	Considering merging to VReg_64 with %vreg776 in %vreg778
		RHS = %vreg776 [5712r,5856r:0)  0@5712r
		LHS = %vreg778 [5824r,5840r:0)  0@5824r
		merge %vreg778:0@5824r into %vreg776:0@5712r --> @5712r
		erased:	5824r	%vreg778<def> = COPY %vreg776; VReg_64:%vreg778,%vreg776
		updated: 5712B	%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
		updated: 5856B	%vreg765<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg765 VReg_128:%vreg687 VReg_64:%vreg778
	Joined. Result = %vreg778 [5712r,5856r:0)  0@5712r
5840B	%vreg779<def> = COPY %vreg778:sub1; VReg_32:%vreg779 VReg_64:%vreg778
	Considering merging to VReg_64 with %vreg779 in %vreg778:sub1
		RHS = %vreg779 [5840r,5872r:0)  0@5840r
		LHS = %vreg778 [5712r,5856r:0)  0@5712r
		merge %vreg779:0@5840r into %vreg778:0@5712r --> @5712r
		erased:	5840r	%vreg779<def> = COPY %vreg778:sub1; VReg_32:%vreg779 VReg_64:%vreg778
		updated: 5872B	%vreg766<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg766 VReg_128:%vreg687 VReg_64:%vreg778
	Joined. Result = %vreg778 [5712r,5872r:0)  0@5712r
5888B	%vreg767:sub0<def,read-undef> = COPY %vreg765; VReg_64:%vreg767 VReg_32:%vreg765
	Considering merging to VReg_64 with %vreg765 in %vreg767:sub0
		RHS = %vreg765 [5856r,5888r:0)  0@5856r
		LHS = %vreg767 [5888r,5904r:1)[5904r,5920r:0)  0@5904r 1@5888r
		merge %vreg767:1@5888r into %vreg765:0@5856r --> @5856r
		erased:	5888r	%vreg767:sub0<def,read-undef> = COPY %vreg765; VReg_64:%vreg767 VReg_32:%vreg765
		updated: 5856B	%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
	Joined. Result = %vreg767 [5856r,5904r:0)[5904r,5920r:1)  0@5856r 1@5904r
5904B	%vreg767:sub1<def> = COPY %vreg766; VReg_64:%vreg767 VReg_32:%vreg766
	Considering merging to VReg_64 with %vreg766 in %vreg767:sub1
		RHS = %vreg766 [5872r,5904r:0)  0@5872r
		LHS = %vreg767 [5856r,5904r:0)[5904r,5920r:1)  0@5856r 1@5904r
		merge %vreg767:1@5904r into %vreg766:0@5872r --> @5872r
		pruned %vreg767 at 5872r: %vreg767 [5856r,5872r:0)[5904r,5920r:1)  0@5856r 1@5904r
		erased:	5904r	%vreg767:sub1<def> = COPY %vreg766; VReg_64:%vreg767 VReg_32:%vreg766
		restoring liveness to 2 points: %vreg767 [5856r,5872r:0)[5872r,5920r:1)  0@5856r 1@5872r
		updated: 5872B	%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
	Joined. Result = %vreg767 [5856r,5872r:0)[5872r,5920r:1)  0@5856r 1@5872r
5968B	%vreg211:sub0<def,read-undef> = COPY %vreg210; SGPR_64:%vreg211 SReg_32:%vreg210
	Considering merging to SGPR_64 with %vreg210 in %vreg211:sub0
		RHS = %vreg210 [1888r,2096B:0)[3552B,9808B:0)  0@1888r
		LHS = %vreg211 [5968r,5984r:1)[5984r,6224r:0)  0@5984r 1@5968r
		merge %vreg211:1@5968r into %vreg210:0@1888r --> @1888r
		pruned %vreg210 at 5984r: %vreg210 [1888r,2096B:0)  0@1888r
		pruned all of %vreg211 at 5968r: %vreg211 [5984r,6224r:0)  0@5984r 1@5968r
		erased:	5968r	%vreg211:sub0<def,read-undef> = COPY %vreg210; SGPR_64:%vreg211 SReg_32:%vreg210
		restoring liveness to 4 points: %vreg211 [1888r,2096B:0)[5984r,6224r:1)  0@1888r 1@5984r
		updated: 1888B	%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
	Joined. Result = %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
5984B	%vreg211:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg211,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg211
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
		interference at %vreg211:0@1888r
	Interference!
6000B	%vreg213<def> = COPY %vreg211; VReg_64:%vreg213 SGPR_64:%vreg211
	Not coalescable.
6016B	%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg632
		RHS = %vreg632 [6016r,6032r:0)  0@6016r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg632:0@6016r into %vreg562:1@4288r --> @4288r
		erased:	6016r	%vreg632<def> = COPY %vreg562; VReg_128:%vreg632,%vreg562
		updated: 6032B	%vreg633<def> = COPY %vreg562:sub0; VReg_32:%vreg633 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
6032B	%vreg633<def> = COPY %vreg562:sub0; VReg_32:%vreg633 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg633 in %vreg562:sub0
		RHS = %vreg633 [6032r,6144r:0)  0@6032r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg633:0@6032r into %vreg562:1@4288r --> @4288r
		erased:	6032r	%vreg633<def> = COPY %vreg562:sub0; VReg_32:%vreg633 VReg_128:%vreg562
		updated: 6144B	%vreg625<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg637, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625,%vreg637 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
6048B	%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg634
		RHS = %vreg634 [6048r,6064r:0)  0@6048r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg634:0@6048r into %vreg562:1@4288r --> @4288r
		erased:	6048r	%vreg634<def> = COPY %vreg562; VReg_128:%vreg634,%vreg562
		updated: 6064B	%vreg635<def> = COPY %vreg562:sub1; VReg_32:%vreg635 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
6064B	%vreg635<def> = COPY %vreg562:sub1; VReg_32:%vreg635 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg635 in %vreg562:sub1
		RHS = %vreg635 [6064r,6160r:0)  0@6064r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg635:0@6064r into %vreg562:1@4288r --> @4288r
		erased:	6064r	%vreg635<def> = COPY %vreg562:sub1; VReg_32:%vreg635 VReg_128:%vreg562
		updated: 6160B	%vreg626<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg639, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg626,%vreg639 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
6080B	%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
	Considering merging to VReg_64 with %vreg213 in %vreg636
		RHS = %vreg213 [6000r,6112r:0)  0@6000r
		LHS = %vreg636 [6080r,6096r:0)  0@6080r
		merge %vreg636:0@6080r into %vreg213:0@6000r --> @6000r
		erased:	6080r	%vreg636<def> = COPY %vreg213; VReg_64:%vreg636,%vreg213
		updated: 6000B	%vreg636<def> = COPY %vreg211; VReg_64:%vreg636 SGPR_64:%vreg211
		updated: 6112B	%vreg638<def> = COPY %vreg636; VReg_64:%vreg638,%vreg636
	Joined. Result = %vreg636 [6000r,6112r:0)  0@6000r
6096B	%vreg637<def> = COPY %vreg636:sub0; VReg_32:%vreg637 VReg_64:%vreg636
	Considering merging to VReg_64 with %vreg637 in %vreg636:sub0
		RHS = %vreg637 [6096r,6144r:0)  0@6096r
		LHS = %vreg636 [6000r,6112r:0)  0@6000r
		merge %vreg637:0@6096r into %vreg636:0@6000r --> @6000r
		erased:	6096r	%vreg637<def> = COPY %vreg636:sub0; VReg_32:%vreg637 VReg_64:%vreg636
		updated: 6144B	%vreg625<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg636:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625 VReg_128:%vreg562 VReg_64:%vreg636
	Joined. Result = %vreg636 [6000r,6144r:0)  0@6000r
6112B	%vreg638<def> = COPY %vreg636; VReg_64:%vreg638,%vreg636
	Considering merging to VReg_64 with %vreg636 in %vreg638
		RHS = %vreg636 [6000r,6144r:0)  0@6000r
		LHS = %vreg638 [6112r,6128r:0)  0@6112r
		merge %vreg638:0@6112r into %vreg636:0@6000r --> @6000r
		erased:	6112r	%vreg638<def> = COPY %vreg636; VReg_64:%vreg638,%vreg636
		updated: 6000B	%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
		updated: 6144B	%vreg625<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg625 VReg_128:%vreg562 VReg_64:%vreg638
	Joined. Result = %vreg638 [6000r,6144r:0)  0@6000r
6128B	%vreg639<def> = COPY %vreg638:sub1; VReg_32:%vreg639 VReg_64:%vreg638
	Considering merging to VReg_64 with %vreg639 in %vreg638:sub1
		RHS = %vreg639 [6128r,6160r:0)  0@6128r
		LHS = %vreg638 [6000r,6144r:0)  0@6000r
		merge %vreg639:0@6128r into %vreg638:0@6000r --> @6000r
		erased:	6128r	%vreg639<def> = COPY %vreg638:sub1; VReg_32:%vreg639 VReg_64:%vreg638
		updated: 6160B	%vreg626<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg626 VReg_128:%vreg562 VReg_64:%vreg638
	Joined. Result = %vreg638 [6000r,6160r:0)  0@6000r
6176B	%vreg627:sub0<def,read-undef> = COPY %vreg625; VReg_64:%vreg627 VReg_32:%vreg625
	Considering merging to VReg_64 with %vreg625 in %vreg627:sub0
		RHS = %vreg625 [6144r,6176r:0)  0@6144r
		LHS = %vreg627 [6176r,6192r:1)[6192r,6208r:0)  0@6192r 1@6176r
		merge %vreg627:1@6176r into %vreg625:0@6144r --> @6144r
		erased:	6176r	%vreg627:sub0<def,read-undef> = COPY %vreg625; VReg_64:%vreg627 VReg_32:%vreg625
		updated: 6144B	%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
	Joined. Result = %vreg627 [6144r,6192r:0)[6192r,6208r:1)  0@6144r 1@6192r
6192B	%vreg627:sub1<def> = COPY %vreg626; VReg_64:%vreg627 VReg_32:%vreg626
	Considering merging to VReg_64 with %vreg626 in %vreg627:sub1
		RHS = %vreg626 [6160r,6192r:0)  0@6160r
		LHS = %vreg627 [6144r,6192r:0)[6192r,6208r:1)  0@6144r 1@6192r
		merge %vreg627:1@6192r into %vreg626:0@6160r --> @6160r
		pruned %vreg627 at 6160r: %vreg627 [6144r,6160r:0)[6192r,6208r:1)  0@6144r 1@6192r
		erased:	6192r	%vreg627:sub1<def> = COPY %vreg626; VReg_64:%vreg627 VReg_32:%vreg626
		restoring liveness to 2 points: %vreg627 [6144r,6160r:0)[6160r,6208r:1)  0@6144r 1@6160r
		updated: 6160B	%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
	Joined. Result = %vreg627 [6144r,6160r:0)[6160r,6208r:1)  0@6144r 1@6160r
6224B	%vreg215<def> = COPY %vreg211; VReg_64:%vreg215 SGPR_64:%vreg211
	Not coalescable.
6240B	%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg757
		RHS = %vreg757 [6240r,6256r:0)  0@6240r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg757:0@6240r into %vreg687:1@4640r --> @4640r
		erased:	6240r	%vreg757<def> = COPY %vreg687; VReg_128:%vreg757,%vreg687
		updated: 6256B	%vreg758<def> = COPY %vreg687:sub0; VReg_32:%vreg758 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
6256B	%vreg758<def> = COPY %vreg687:sub0; VReg_32:%vreg758 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg758 in %vreg687:sub0
		RHS = %vreg758 [6256r,6368r:0)  0@6256r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg758:0@6256r into %vreg687:1@4640r --> @4640r
		erased:	6256r	%vreg758<def> = COPY %vreg687:sub0; VReg_32:%vreg758 VReg_128:%vreg687
		updated: 6368B	%vreg750<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg762, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750,%vreg762 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
6272B	%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg759
		RHS = %vreg759 [6272r,6288r:0)  0@6272r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg759:0@6272r into %vreg687:1@4640r --> @4640r
		erased:	6272r	%vreg759<def> = COPY %vreg687; VReg_128:%vreg759,%vreg687
		updated: 6288B	%vreg760<def> = COPY %vreg687:sub1; VReg_32:%vreg760 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
6288B	%vreg760<def> = COPY %vreg687:sub1; VReg_32:%vreg760 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg760 in %vreg687:sub1
		RHS = %vreg760 [6288r,6384r:0)  0@6288r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg760:0@6288r into %vreg687:1@4640r --> @4640r
		erased:	6288r	%vreg760<def> = COPY %vreg687:sub1; VReg_32:%vreg760 VReg_128:%vreg687
		updated: 6384B	%vreg751<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg764, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg751,%vreg764 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
6304B	%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
	Considering merging to VReg_64 with %vreg215 in %vreg761
		RHS = %vreg215 [6224r,6336r:0)  0@6224r
		LHS = %vreg761 [6304r,6320r:0)  0@6304r
		merge %vreg761:0@6304r into %vreg215:0@6224r --> @6224r
		erased:	6304r	%vreg761<def> = COPY %vreg215; VReg_64:%vreg761,%vreg215
		updated: 6224B	%vreg761<def> = COPY %vreg211; VReg_64:%vreg761 SGPR_64:%vreg211
		updated: 6336B	%vreg763<def> = COPY %vreg761; VReg_64:%vreg763,%vreg761
	Joined. Result = %vreg761 [6224r,6336r:0)  0@6224r
6320B	%vreg762<def> = COPY %vreg761:sub0; VReg_32:%vreg762 VReg_64:%vreg761
	Considering merging to VReg_64 with %vreg762 in %vreg761:sub0
		RHS = %vreg762 [6320r,6368r:0)  0@6320r
		LHS = %vreg761 [6224r,6336r:0)  0@6224r
		merge %vreg762:0@6320r into %vreg761:0@6224r --> @6224r
		erased:	6320r	%vreg762<def> = COPY %vreg761:sub0; VReg_32:%vreg762 VReg_64:%vreg761
		updated: 6368B	%vreg750<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg761:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750 VReg_128:%vreg687 VReg_64:%vreg761
	Joined. Result = %vreg761 [6224r,6368r:0)  0@6224r
6336B	%vreg763<def> = COPY %vreg761; VReg_64:%vreg763,%vreg761
	Considering merging to VReg_64 with %vreg761 in %vreg763
		RHS = %vreg761 [6224r,6368r:0)  0@6224r
		LHS = %vreg763 [6336r,6352r:0)  0@6336r
		merge %vreg763:0@6336r into %vreg761:0@6224r --> @6224r
		erased:	6336r	%vreg763<def> = COPY %vreg761; VReg_64:%vreg763,%vreg761
		updated: 6224B	%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
		updated: 6368B	%vreg750<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg750 VReg_128:%vreg687 VReg_64:%vreg763
	Joined. Result = %vreg763 [6224r,6368r:0)  0@6224r
6352B	%vreg764<def> = COPY %vreg763:sub1; VReg_32:%vreg764 VReg_64:%vreg763
	Considering merging to VReg_64 with %vreg764 in %vreg763:sub1
		RHS = %vreg764 [6352r,6384r:0)  0@6352r
		LHS = %vreg763 [6224r,6368r:0)  0@6224r
		merge %vreg764:0@6352r into %vreg763:0@6224r --> @6224r
		erased:	6352r	%vreg764<def> = COPY %vreg763:sub1; VReg_32:%vreg764 VReg_64:%vreg763
		updated: 6384B	%vreg751<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg751 VReg_128:%vreg687 VReg_64:%vreg763
	Joined. Result = %vreg763 [6224r,6384r:0)  0@6224r
6400B	%vreg752:sub0<def,read-undef> = COPY %vreg750; VReg_64:%vreg752 VReg_32:%vreg750
	Considering merging to VReg_64 with %vreg750 in %vreg752:sub0
		RHS = %vreg750 [6368r,6400r:0)  0@6368r
		LHS = %vreg752 [6400r,6416r:1)[6416r,6432r:0)  0@6416r 1@6400r
		merge %vreg752:1@6400r into %vreg750:0@6368r --> @6368r
		erased:	6400r	%vreg752:sub0<def,read-undef> = COPY %vreg750; VReg_64:%vreg752 VReg_32:%vreg750
		updated: 6368B	%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
	Joined. Result = %vreg752 [6368r,6416r:0)[6416r,6432r:1)  0@6368r 1@6416r
6416B	%vreg752:sub1<def> = COPY %vreg751; VReg_64:%vreg752 VReg_32:%vreg751
	Considering merging to VReg_64 with %vreg751 in %vreg752:sub1
		RHS = %vreg751 [6384r,6416r:0)  0@6384r
		LHS = %vreg752 [6368r,6416r:0)[6416r,6432r:1)  0@6368r 1@6416r
		merge %vreg752:1@6416r into %vreg751:0@6384r --> @6384r
		pruned %vreg752 at 6384r: %vreg752 [6368r,6384r:0)[6416r,6432r:1)  0@6368r 1@6416r
		erased:	6416r	%vreg752:sub1<def> = COPY %vreg751; VReg_64:%vreg752 VReg_32:%vreg751
		restoring liveness to 2 points: %vreg752 [6368r,6384r:0)[6384r,6432r:1)  0@6368r 1@6384r
		updated: 6384B	%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
	Joined. Result = %vreg752 [6368r,6384r:0)[6384r,6432r:1)  0@6368r 1@6384r
6480B	%vreg219:sub0<def,read-undef> = COPY %vreg218; SGPR_64:%vreg219 SReg_32:%vreg218
	Considering merging to SGPR_64 with %vreg218 in %vreg219:sub0
		RHS = %vreg218 [1904r,2096B:0)[3552B,9808B:0)  0@1904r
		LHS = %vreg219 [6480r,6496r:1)[6496r,6736r:0)  0@6496r 1@6480r
		merge %vreg219:1@6480r into %vreg218:0@1904r --> @1904r
		pruned %vreg218 at 6496r: %vreg218 [1904r,2096B:0)  0@1904r
		pruned all of %vreg219 at 6480r: %vreg219 [6496r,6736r:0)  0@6496r 1@6480r
		erased:	6480r	%vreg219:sub0<def,read-undef> = COPY %vreg218; SGPR_64:%vreg219 SReg_32:%vreg218
		restoring liveness to 4 points: %vreg219 [1904r,2096B:0)[6496r,6736r:1)  0@1904r 1@6496r
		updated: 1904B	%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
	Joined. Result = %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
6496B	%vreg219:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg219,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg219
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
		interference at %vreg219:0@1904r
	Interference!
6512B	%vreg221<def> = COPY %vreg219; VReg_64:%vreg221 SGPR_64:%vreg219
	Not coalescable.
6528B	%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg617
		RHS = %vreg617 [6528r,6544r:0)  0@6528r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg617:0@6528r into %vreg562:1@4288r --> @4288r
		erased:	6528r	%vreg617<def> = COPY %vreg562; VReg_128:%vreg617,%vreg562
		updated: 6544B	%vreg618<def> = COPY %vreg562:sub0; VReg_32:%vreg618 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
6544B	%vreg618<def> = COPY %vreg562:sub0; VReg_32:%vreg618 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg618 in %vreg562:sub0
		RHS = %vreg618 [6544r,6656r:0)  0@6544r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg618:0@6544r into %vreg562:1@4288r --> @4288r
		erased:	6544r	%vreg618<def> = COPY %vreg562:sub0; VReg_32:%vreg618 VReg_128:%vreg562
		updated: 6656B	%vreg610<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg622, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610,%vreg622 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
6560B	%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg619
		RHS = %vreg619 [6560r,6576r:0)  0@6560r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg619:0@6560r into %vreg562:1@4288r --> @4288r
		erased:	6560r	%vreg619<def> = COPY %vreg562; VReg_128:%vreg619,%vreg562
		updated: 6576B	%vreg620<def> = COPY %vreg562:sub1; VReg_32:%vreg620 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
6576B	%vreg620<def> = COPY %vreg562:sub1; VReg_32:%vreg620 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg620 in %vreg562:sub1
		RHS = %vreg620 [6576r,6672r:0)  0@6576r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg620:0@6576r into %vreg562:1@4288r --> @4288r
		erased:	6576r	%vreg620<def> = COPY %vreg562:sub1; VReg_32:%vreg620 VReg_128:%vreg562
		updated: 6672B	%vreg611<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg624, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg611,%vreg624 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
6592B	%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
	Considering merging to VReg_64 with %vreg221 in %vreg621
		RHS = %vreg221 [6512r,6624r:0)  0@6512r
		LHS = %vreg621 [6592r,6608r:0)  0@6592r
		merge %vreg621:0@6592r into %vreg221:0@6512r --> @6512r
		erased:	6592r	%vreg621<def> = COPY %vreg221; VReg_64:%vreg621,%vreg221
		updated: 6512B	%vreg621<def> = COPY %vreg219; VReg_64:%vreg621 SGPR_64:%vreg219
		updated: 6624B	%vreg623<def> = COPY %vreg621; VReg_64:%vreg623,%vreg621
	Joined. Result = %vreg621 [6512r,6624r:0)  0@6512r
6608B	%vreg622<def> = COPY %vreg621:sub0; VReg_32:%vreg622 VReg_64:%vreg621
	Considering merging to VReg_64 with %vreg622 in %vreg621:sub0
		RHS = %vreg622 [6608r,6656r:0)  0@6608r
		LHS = %vreg621 [6512r,6624r:0)  0@6512r
		merge %vreg622:0@6608r into %vreg621:0@6512r --> @6512r
		erased:	6608r	%vreg622<def> = COPY %vreg621:sub0; VReg_32:%vreg622 VReg_64:%vreg621
		updated: 6656B	%vreg610<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg621:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610 VReg_128:%vreg562 VReg_64:%vreg621
	Joined. Result = %vreg621 [6512r,6656r:0)  0@6512r
6624B	%vreg623<def> = COPY %vreg621; VReg_64:%vreg623,%vreg621
	Considering merging to VReg_64 with %vreg621 in %vreg623
		RHS = %vreg621 [6512r,6656r:0)  0@6512r
		LHS = %vreg623 [6624r,6640r:0)  0@6624r
		merge %vreg623:0@6624r into %vreg621:0@6512r --> @6512r
		erased:	6624r	%vreg623<def> = COPY %vreg621; VReg_64:%vreg623,%vreg621
		updated: 6512B	%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
		updated: 6656B	%vreg610<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg610 VReg_128:%vreg562 VReg_64:%vreg623
	Joined. Result = %vreg623 [6512r,6656r:0)  0@6512r
6640B	%vreg624<def> = COPY %vreg623:sub1; VReg_32:%vreg624 VReg_64:%vreg623
	Considering merging to VReg_64 with %vreg624 in %vreg623:sub1
		RHS = %vreg624 [6640r,6672r:0)  0@6640r
		LHS = %vreg623 [6512r,6656r:0)  0@6512r
		merge %vreg624:0@6640r into %vreg623:0@6512r --> @6512r
		erased:	6640r	%vreg624<def> = COPY %vreg623:sub1; VReg_32:%vreg624 VReg_64:%vreg623
		updated: 6672B	%vreg611<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg611 VReg_128:%vreg562 VReg_64:%vreg623
	Joined. Result = %vreg623 [6512r,6672r:0)  0@6512r
6688B	%vreg612:sub0<def,read-undef> = COPY %vreg610; VReg_64:%vreg612 VReg_32:%vreg610
	Considering merging to VReg_64 with %vreg610 in %vreg612:sub0
		RHS = %vreg610 [6656r,6688r:0)  0@6656r
		LHS = %vreg612 [6688r,6704r:1)[6704r,6720r:0)  0@6704r 1@6688r
		merge %vreg612:1@6688r into %vreg610:0@6656r --> @6656r
		erased:	6688r	%vreg612:sub0<def,read-undef> = COPY %vreg610; VReg_64:%vreg612 VReg_32:%vreg610
		updated: 6656B	%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
	Joined. Result = %vreg612 [6656r,6704r:0)[6704r,6720r:1)  0@6656r 1@6704r
6704B	%vreg612:sub1<def> = COPY %vreg611; VReg_64:%vreg612 VReg_32:%vreg611
	Considering merging to VReg_64 with %vreg611 in %vreg612:sub1
		RHS = %vreg611 [6672r,6704r:0)  0@6672r
		LHS = %vreg612 [6656r,6704r:0)[6704r,6720r:1)  0@6656r 1@6704r
		merge %vreg612:1@6704r into %vreg611:0@6672r --> @6672r
		pruned %vreg612 at 6672r: %vreg612 [6656r,6672r:0)[6704r,6720r:1)  0@6656r 1@6704r
		erased:	6704r	%vreg612:sub1<def> = COPY %vreg611; VReg_64:%vreg612 VReg_32:%vreg611
		restoring liveness to 2 points: %vreg612 [6656r,6672r:0)[6672r,6720r:1)  0@6656r 1@6672r
		updated: 6672B	%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
	Joined. Result = %vreg612 [6656r,6672r:0)[6672r,6720r:1)  0@6656r 1@6672r
6736B	%vreg223<def> = COPY %vreg219; VReg_64:%vreg223 SGPR_64:%vreg219
	Not coalescable.
6752B	%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg742
		RHS = %vreg742 [6752r,6768r:0)  0@6752r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg742:0@6752r into %vreg687:1@4640r --> @4640r
		erased:	6752r	%vreg742<def> = COPY %vreg687; VReg_128:%vreg742,%vreg687
		updated: 6768B	%vreg743<def> = COPY %vreg687:sub0; VReg_32:%vreg743 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
6768B	%vreg743<def> = COPY %vreg687:sub0; VReg_32:%vreg743 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg743 in %vreg687:sub0
		RHS = %vreg743 [6768r,6880r:0)  0@6768r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg743:0@6768r into %vreg687:1@4640r --> @4640r
		erased:	6768r	%vreg743<def> = COPY %vreg687:sub0; VReg_32:%vreg743 VReg_128:%vreg687
		updated: 6880B	%vreg735<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg747, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735,%vreg747 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
6784B	%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg744
		RHS = %vreg744 [6784r,6800r:0)  0@6784r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg744:0@6784r into %vreg687:1@4640r --> @4640r
		erased:	6784r	%vreg744<def> = COPY %vreg687; VReg_128:%vreg744,%vreg687
		updated: 6800B	%vreg745<def> = COPY %vreg687:sub1; VReg_32:%vreg745 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
6800B	%vreg745<def> = COPY %vreg687:sub1; VReg_32:%vreg745 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg745 in %vreg687:sub1
		RHS = %vreg745 [6800r,6896r:0)  0@6800r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg745:0@6800r into %vreg687:1@4640r --> @4640r
		erased:	6800r	%vreg745<def> = COPY %vreg687:sub1; VReg_32:%vreg745 VReg_128:%vreg687
		updated: 6896B	%vreg736<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg749, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg736,%vreg749 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
6816B	%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
	Considering merging to VReg_64 with %vreg223 in %vreg746
		RHS = %vreg223 [6736r,6848r:0)  0@6736r
		LHS = %vreg746 [6816r,6832r:0)  0@6816r
		merge %vreg746:0@6816r into %vreg223:0@6736r --> @6736r
		erased:	6816r	%vreg746<def> = COPY %vreg223; VReg_64:%vreg746,%vreg223
		updated: 6736B	%vreg746<def> = COPY %vreg219; VReg_64:%vreg746 SGPR_64:%vreg219
		updated: 6848B	%vreg748<def> = COPY %vreg746; VReg_64:%vreg748,%vreg746
	Joined. Result = %vreg746 [6736r,6848r:0)  0@6736r
6832B	%vreg747<def> = COPY %vreg746:sub0; VReg_32:%vreg747 VReg_64:%vreg746
	Considering merging to VReg_64 with %vreg747 in %vreg746:sub0
		RHS = %vreg747 [6832r,6880r:0)  0@6832r
		LHS = %vreg746 [6736r,6848r:0)  0@6736r
		merge %vreg747:0@6832r into %vreg746:0@6736r --> @6736r
		erased:	6832r	%vreg747<def> = COPY %vreg746:sub0; VReg_32:%vreg747 VReg_64:%vreg746
		updated: 6880B	%vreg735<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg746:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735 VReg_128:%vreg687 VReg_64:%vreg746
	Joined. Result = %vreg746 [6736r,6880r:0)  0@6736r
6848B	%vreg748<def> = COPY %vreg746; VReg_64:%vreg748,%vreg746
	Considering merging to VReg_64 with %vreg746 in %vreg748
		RHS = %vreg746 [6736r,6880r:0)  0@6736r
		LHS = %vreg748 [6848r,6864r:0)  0@6848r
		merge %vreg748:0@6848r into %vreg746:0@6736r --> @6736r
		erased:	6848r	%vreg748<def> = COPY %vreg746; VReg_64:%vreg748,%vreg746
		updated: 6736B	%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
		updated: 6880B	%vreg735<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg735 VReg_128:%vreg687 VReg_64:%vreg748
	Joined. Result = %vreg748 [6736r,6880r:0)  0@6736r
6864B	%vreg749<def> = COPY %vreg748:sub1; VReg_32:%vreg749 VReg_64:%vreg748
	Considering merging to VReg_64 with %vreg749 in %vreg748:sub1
		RHS = %vreg749 [6864r,6896r:0)  0@6864r
		LHS = %vreg748 [6736r,6880r:0)  0@6736r
		merge %vreg749:0@6864r into %vreg748:0@6736r --> @6736r
		erased:	6864r	%vreg749<def> = COPY %vreg748:sub1; VReg_32:%vreg749 VReg_64:%vreg748
		updated: 6896B	%vreg736<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg736 VReg_128:%vreg687 VReg_64:%vreg748
	Joined. Result = %vreg748 [6736r,6896r:0)  0@6736r
6912B	%vreg737:sub0<def,read-undef> = COPY %vreg735; VReg_64:%vreg737 VReg_32:%vreg735
	Considering merging to VReg_64 with %vreg735 in %vreg737:sub0
		RHS = %vreg735 [6880r,6912r:0)  0@6880r
		LHS = %vreg737 [6912r,6928r:1)[6928r,6944r:0)  0@6928r 1@6912r
		merge %vreg737:1@6912r into %vreg735:0@6880r --> @6880r
		erased:	6912r	%vreg737:sub0<def,read-undef> = COPY %vreg735; VReg_64:%vreg737 VReg_32:%vreg735
		updated: 6880B	%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
	Joined. Result = %vreg737 [6880r,6928r:0)[6928r,6944r:1)  0@6880r 1@6928r
6928B	%vreg737:sub1<def> = COPY %vreg736; VReg_64:%vreg737 VReg_32:%vreg736
	Considering merging to VReg_64 with %vreg736 in %vreg737:sub1
		RHS = %vreg736 [6896r,6928r:0)  0@6896r
		LHS = %vreg737 [6880r,6928r:0)[6928r,6944r:1)  0@6880r 1@6928r
		merge %vreg737:1@6928r into %vreg736:0@6896r --> @6896r
		pruned %vreg737 at 6896r: %vreg737 [6880r,6896r:0)[6928r,6944r:1)  0@6880r 1@6928r
		erased:	6928r	%vreg737:sub1<def> = COPY %vreg736; VReg_64:%vreg737 VReg_32:%vreg736
		restoring liveness to 2 points: %vreg737 [6880r,6896r:0)[6896r,6944r:1)  0@6880r 1@6896r
		updated: 6896B	%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
	Joined. Result = %vreg737 [6880r,6896r:0)[6896r,6944r:1)  0@6880r 1@6896r
6992B	%vreg227:sub0<def,read-undef> = COPY %vreg226; SGPR_64:%vreg227 SReg_32:%vreg226
	Considering merging to SGPR_64 with %vreg226 in %vreg227:sub0
		RHS = %vreg226 [1920r,2096B:0)[3552B,9808B:0)  0@1920r
		LHS = %vreg227 [6992r,7008r:1)[7008r,7248r:0)  0@7008r 1@6992r
		merge %vreg227:1@6992r into %vreg226:0@1920r --> @1920r
		pruned %vreg226 at 7008r: %vreg226 [1920r,2096B:0)  0@1920r
		pruned all of %vreg227 at 6992r: %vreg227 [7008r,7248r:0)  0@7008r 1@6992r
		erased:	6992r	%vreg227:sub0<def,read-undef> = COPY %vreg226; SGPR_64:%vreg227 SReg_32:%vreg226
		restoring liveness to 4 points: %vreg227 [1920r,2096B:0)[7008r,7248r:1)  0@1920r 1@7008r
		updated: 1920B	%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
	Joined. Result = %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
7008B	%vreg227:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg227,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg227
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
		interference at %vreg227:0@1920r
	Interference!
7024B	%vreg229<def> = COPY %vreg227; VReg_64:%vreg229 SGPR_64:%vreg227
	Not coalescable.
7040B	%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg602
		RHS = %vreg602 [7040r,7056r:0)  0@7040r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg602:0@7040r into %vreg562:1@4288r --> @4288r
		erased:	7040r	%vreg602<def> = COPY %vreg562; VReg_128:%vreg602,%vreg562
		updated: 7056B	%vreg603<def> = COPY %vreg562:sub0; VReg_32:%vreg603 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
7056B	%vreg603<def> = COPY %vreg562:sub0; VReg_32:%vreg603 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg603 in %vreg562:sub0
		RHS = %vreg603 [7056r,7168r:0)  0@7056r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg603:0@7056r into %vreg562:1@4288r --> @4288r
		erased:	7056r	%vreg603<def> = COPY %vreg562:sub0; VReg_32:%vreg603 VReg_128:%vreg562
		updated: 7168B	%vreg595<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg607, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595,%vreg607 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
7072B	%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg604
		RHS = %vreg604 [7072r,7088r:0)  0@7072r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg604:0@7072r into %vreg562:1@4288r --> @4288r
		erased:	7072r	%vreg604<def> = COPY %vreg562; VReg_128:%vreg604,%vreg562
		updated: 7088B	%vreg605<def> = COPY %vreg562:sub1; VReg_32:%vreg605 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
7088B	%vreg605<def> = COPY %vreg562:sub1; VReg_32:%vreg605 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg605 in %vreg562:sub1
		RHS = %vreg605 [7088r,7184r:0)  0@7088r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg605:0@7088r into %vreg562:1@4288r --> @4288r
		erased:	7088r	%vreg605<def> = COPY %vreg562:sub1; VReg_32:%vreg605 VReg_128:%vreg562
		updated: 7184B	%vreg596<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg609, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg596,%vreg609 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
7104B	%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
	Considering merging to VReg_64 with %vreg229 in %vreg606
		RHS = %vreg229 [7024r,7136r:0)  0@7024r
		LHS = %vreg606 [7104r,7120r:0)  0@7104r
		merge %vreg606:0@7104r into %vreg229:0@7024r --> @7024r
		erased:	7104r	%vreg606<def> = COPY %vreg229; VReg_64:%vreg606,%vreg229
		updated: 7024B	%vreg606<def> = COPY %vreg227; VReg_64:%vreg606 SGPR_64:%vreg227
		updated: 7136B	%vreg608<def> = COPY %vreg606; VReg_64:%vreg608,%vreg606
	Joined. Result = %vreg606 [7024r,7136r:0)  0@7024r
7120B	%vreg607<def> = COPY %vreg606:sub0; VReg_32:%vreg607 VReg_64:%vreg606
	Considering merging to VReg_64 with %vreg607 in %vreg606:sub0
		RHS = %vreg607 [7120r,7168r:0)  0@7120r
		LHS = %vreg606 [7024r,7136r:0)  0@7024r
		merge %vreg607:0@7120r into %vreg606:0@7024r --> @7024r
		erased:	7120r	%vreg607<def> = COPY %vreg606:sub0; VReg_32:%vreg607 VReg_64:%vreg606
		updated: 7168B	%vreg595<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg606:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595 VReg_128:%vreg562 VReg_64:%vreg606
	Joined. Result = %vreg606 [7024r,7168r:0)  0@7024r
7136B	%vreg608<def> = COPY %vreg606; VReg_64:%vreg608,%vreg606
	Considering merging to VReg_64 with %vreg606 in %vreg608
		RHS = %vreg606 [7024r,7168r:0)  0@7024r
		LHS = %vreg608 [7136r,7152r:0)  0@7136r
		merge %vreg608:0@7136r into %vreg606:0@7024r --> @7024r
		erased:	7136r	%vreg608<def> = COPY %vreg606; VReg_64:%vreg608,%vreg606
		updated: 7024B	%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
		updated: 7168B	%vreg595<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg595 VReg_128:%vreg562 VReg_64:%vreg608
	Joined. Result = %vreg608 [7024r,7168r:0)  0@7024r
7152B	%vreg609<def> = COPY %vreg608:sub1; VReg_32:%vreg609 VReg_64:%vreg608
	Considering merging to VReg_64 with %vreg609 in %vreg608:sub1
		RHS = %vreg609 [7152r,7184r:0)  0@7152r
		LHS = %vreg608 [7024r,7168r:0)  0@7024r
		merge %vreg609:0@7152r into %vreg608:0@7024r --> @7024r
		erased:	7152r	%vreg609<def> = COPY %vreg608:sub1; VReg_32:%vreg609 VReg_64:%vreg608
		updated: 7184B	%vreg596<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg596 VReg_128:%vreg562 VReg_64:%vreg608
	Joined. Result = %vreg608 [7024r,7184r:0)  0@7024r
7200B	%vreg597:sub0<def,read-undef> = COPY %vreg595; VReg_64:%vreg597 VReg_32:%vreg595
	Considering merging to VReg_64 with %vreg595 in %vreg597:sub0
		RHS = %vreg595 [7168r,7200r:0)  0@7168r
		LHS = %vreg597 [7200r,7216r:1)[7216r,7232r:0)  0@7216r 1@7200r
		merge %vreg597:1@7200r into %vreg595:0@7168r --> @7168r
		erased:	7200r	%vreg597:sub0<def,read-undef> = COPY %vreg595; VReg_64:%vreg597 VReg_32:%vreg595
		updated: 7168B	%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
	Joined. Result = %vreg597 [7168r,7216r:0)[7216r,7232r:1)  0@7168r 1@7216r
7216B	%vreg597:sub1<def> = COPY %vreg596; VReg_64:%vreg597 VReg_32:%vreg596
	Considering merging to VReg_64 with %vreg596 in %vreg597:sub1
		RHS = %vreg596 [7184r,7216r:0)  0@7184r
		LHS = %vreg597 [7168r,7216r:0)[7216r,7232r:1)  0@7168r 1@7216r
		merge %vreg597:1@7216r into %vreg596:0@7184r --> @7184r
		pruned %vreg597 at 7184r: %vreg597 [7168r,7184r:0)[7216r,7232r:1)  0@7168r 1@7216r
		erased:	7216r	%vreg597:sub1<def> = COPY %vreg596; VReg_64:%vreg597 VReg_32:%vreg596
		restoring liveness to 2 points: %vreg597 [7168r,7184r:0)[7184r,7232r:1)  0@7168r 1@7184r
		updated: 7184B	%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
	Joined. Result = %vreg597 [7168r,7184r:0)[7184r,7232r:1)  0@7168r 1@7184r
7248B	%vreg231<def> = COPY %vreg227; VReg_64:%vreg231 SGPR_64:%vreg227
	Not coalescable.
7264B	%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg727
		RHS = %vreg727 [7264r,7280r:0)  0@7264r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg727:0@7264r into %vreg687:1@4640r --> @4640r
		erased:	7264r	%vreg727<def> = COPY %vreg687; VReg_128:%vreg727,%vreg687
		updated: 7280B	%vreg728<def> = COPY %vreg687:sub0; VReg_32:%vreg728 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
7280B	%vreg728<def> = COPY %vreg687:sub0; VReg_32:%vreg728 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg728 in %vreg687:sub0
		RHS = %vreg728 [7280r,7392r:0)  0@7280r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg728:0@7280r into %vreg687:1@4640r --> @4640r
		erased:	7280r	%vreg728<def> = COPY %vreg687:sub0; VReg_32:%vreg728 VReg_128:%vreg687
		updated: 7392B	%vreg720<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg732, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720,%vreg732 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
7296B	%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg729
		RHS = %vreg729 [7296r,7312r:0)  0@7296r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg729:0@7296r into %vreg687:1@4640r --> @4640r
		erased:	7296r	%vreg729<def> = COPY %vreg687; VReg_128:%vreg729,%vreg687
		updated: 7312B	%vreg730<def> = COPY %vreg687:sub1; VReg_32:%vreg730 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
7312B	%vreg730<def> = COPY %vreg687:sub1; VReg_32:%vreg730 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg730 in %vreg687:sub1
		RHS = %vreg730 [7312r,7408r:0)  0@7312r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg730:0@7312r into %vreg687:1@4640r --> @4640r
		erased:	7312r	%vreg730<def> = COPY %vreg687:sub1; VReg_32:%vreg730 VReg_128:%vreg687
		updated: 7408B	%vreg721<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg734, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg721,%vreg734 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
7328B	%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
	Considering merging to VReg_64 with %vreg231 in %vreg731
		RHS = %vreg231 [7248r,7360r:0)  0@7248r
		LHS = %vreg731 [7328r,7344r:0)  0@7328r
		merge %vreg731:0@7328r into %vreg231:0@7248r --> @7248r
		erased:	7328r	%vreg731<def> = COPY %vreg231; VReg_64:%vreg731,%vreg231
		updated: 7248B	%vreg731<def> = COPY %vreg227; VReg_64:%vreg731 SGPR_64:%vreg227
		updated: 7360B	%vreg733<def> = COPY %vreg731; VReg_64:%vreg733,%vreg731
	Joined. Result = %vreg731 [7248r,7360r:0)  0@7248r
7344B	%vreg732<def> = COPY %vreg731:sub0; VReg_32:%vreg732 VReg_64:%vreg731
	Considering merging to VReg_64 with %vreg732 in %vreg731:sub0
		RHS = %vreg732 [7344r,7392r:0)  0@7344r
		LHS = %vreg731 [7248r,7360r:0)  0@7248r
		merge %vreg732:0@7344r into %vreg731:0@7248r --> @7248r
		erased:	7344r	%vreg732<def> = COPY %vreg731:sub0; VReg_32:%vreg732 VReg_64:%vreg731
		updated: 7392B	%vreg720<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg731:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720 VReg_128:%vreg687 VReg_64:%vreg731
	Joined. Result = %vreg731 [7248r,7392r:0)  0@7248r
7360B	%vreg733<def> = COPY %vreg731; VReg_64:%vreg733,%vreg731
	Considering merging to VReg_64 with %vreg731 in %vreg733
		RHS = %vreg731 [7248r,7392r:0)  0@7248r
		LHS = %vreg733 [7360r,7376r:0)  0@7360r
		merge %vreg733:0@7360r into %vreg731:0@7248r --> @7248r
		erased:	7360r	%vreg733<def> = COPY %vreg731; VReg_64:%vreg733,%vreg731
		updated: 7248B	%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
		updated: 7392B	%vreg720<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg720 VReg_128:%vreg687 VReg_64:%vreg733
	Joined. Result = %vreg733 [7248r,7392r:0)  0@7248r
7376B	%vreg734<def> = COPY %vreg733:sub1; VReg_32:%vreg734 VReg_64:%vreg733
	Considering merging to VReg_64 with %vreg734 in %vreg733:sub1
		RHS = %vreg734 [7376r,7408r:0)  0@7376r
		LHS = %vreg733 [7248r,7392r:0)  0@7248r
		merge %vreg734:0@7376r into %vreg733:0@7248r --> @7248r
		erased:	7376r	%vreg734<def> = COPY %vreg733:sub1; VReg_32:%vreg734 VReg_64:%vreg733
		updated: 7408B	%vreg721<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg721 VReg_128:%vreg687 VReg_64:%vreg733
	Joined. Result = %vreg733 [7248r,7408r:0)  0@7248r
7424B	%vreg722:sub0<def,read-undef> = COPY %vreg720; VReg_64:%vreg722 VReg_32:%vreg720
	Considering merging to VReg_64 with %vreg720 in %vreg722:sub0
		RHS = %vreg720 [7392r,7424r:0)  0@7392r
		LHS = %vreg722 [7424r,7440r:1)[7440r,7456r:0)  0@7440r 1@7424r
		merge %vreg722:1@7424r into %vreg720:0@7392r --> @7392r
		erased:	7424r	%vreg722:sub0<def,read-undef> = COPY %vreg720; VReg_64:%vreg722 VReg_32:%vreg720
		updated: 7392B	%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
	Joined. Result = %vreg722 [7392r,7440r:0)[7440r,7456r:1)  0@7392r 1@7440r
7440B	%vreg722:sub1<def> = COPY %vreg721; VReg_64:%vreg722 VReg_32:%vreg721
	Considering merging to VReg_64 with %vreg721 in %vreg722:sub1
		RHS = %vreg721 [7408r,7440r:0)  0@7408r
		LHS = %vreg722 [7392r,7440r:0)[7440r,7456r:1)  0@7392r 1@7440r
		merge %vreg722:1@7440r into %vreg721:0@7408r --> @7408r
		pruned %vreg722 at 7408r: %vreg722 [7392r,7408r:0)[7440r,7456r:1)  0@7392r 1@7440r
		erased:	7440r	%vreg722:sub1<def> = COPY %vreg721; VReg_64:%vreg722 VReg_32:%vreg721
		restoring liveness to 2 points: %vreg722 [7392r,7408r:0)[7408r,7456r:1)  0@7392r 1@7408r
		updated: 7408B	%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
	Joined. Result = %vreg722 [7392r,7408r:0)[7408r,7456r:1)  0@7392r 1@7408r
7504B	%vreg235:sub0<def,read-undef> = COPY %vreg234; SGPR_64:%vreg235 SReg_32:%vreg234
	Considering merging to SGPR_64 with %vreg234 in %vreg235:sub0
		RHS = %vreg234 [1936r,2096B:0)[3552B,9808B:0)  0@1936r
		LHS = %vreg235 [7504r,7520r:1)[7520r,7760r:0)  0@7520r 1@7504r
		merge %vreg235:1@7504r into %vreg234:0@1936r --> @1936r
		pruned %vreg234 at 7520r: %vreg234 [1936r,2096B:0)  0@1936r
		pruned all of %vreg235 at 7504r: %vreg235 [7520r,7760r:0)  0@7520r 1@7504r
		erased:	7504r	%vreg235:sub0<def,read-undef> = COPY %vreg234; SGPR_64:%vreg235 SReg_32:%vreg234
		restoring liveness to 4 points: %vreg235 [1936r,2096B:0)[7520r,7760r:1)  0@1936r 1@7520r
		updated: 1936B	%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
	Joined. Result = %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
7520B	%vreg235:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg235,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg235
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
		interference at %vreg235:0@1936r
	Interference!
7536B	%vreg237<def> = COPY %vreg235; VReg_64:%vreg237 SGPR_64:%vreg235
	Not coalescable.
7552B	%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg587
		RHS = %vreg587 [7552r,7568r:0)  0@7552r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg587:0@7552r into %vreg562:1@4288r --> @4288r
		erased:	7552r	%vreg587<def> = COPY %vreg562; VReg_128:%vreg587,%vreg562
		updated: 7568B	%vreg588<def> = COPY %vreg562:sub0; VReg_32:%vreg588 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
7568B	%vreg588<def> = COPY %vreg562:sub0; VReg_32:%vreg588 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg588 in %vreg562:sub0
		RHS = %vreg588 [7568r,7680r:0)  0@7568r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg588:0@7568r into %vreg562:1@4288r --> @4288r
		erased:	7568r	%vreg588<def> = COPY %vreg562:sub0; VReg_32:%vreg588 VReg_128:%vreg562
		updated: 7680B	%vreg580<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg592, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580,%vreg592 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
7584B	%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg589
		RHS = %vreg589 [7584r,7600r:0)  0@7584r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg589:0@7584r into %vreg562:1@4288r --> @4288r
		erased:	7584r	%vreg589<def> = COPY %vreg562; VReg_128:%vreg589,%vreg562
		updated: 7600B	%vreg590<def> = COPY %vreg562:sub1; VReg_32:%vreg590 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
7600B	%vreg590<def> = COPY %vreg562:sub1; VReg_32:%vreg590 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg590 in %vreg562:sub1
		RHS = %vreg590 [7600r,7696r:0)  0@7600r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg590:0@7600r into %vreg562:1@4288r --> @4288r
		erased:	7600r	%vreg590<def> = COPY %vreg562:sub1; VReg_32:%vreg590 VReg_128:%vreg562
		updated: 7696B	%vreg581<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg594, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg581,%vreg594 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
7616B	%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
	Considering merging to VReg_64 with %vreg237 in %vreg591
		RHS = %vreg237 [7536r,7648r:0)  0@7536r
		LHS = %vreg591 [7616r,7632r:0)  0@7616r
		merge %vreg591:0@7616r into %vreg237:0@7536r --> @7536r
		erased:	7616r	%vreg591<def> = COPY %vreg237; VReg_64:%vreg591,%vreg237
		updated: 7536B	%vreg591<def> = COPY %vreg235; VReg_64:%vreg591 SGPR_64:%vreg235
		updated: 7648B	%vreg593<def> = COPY %vreg591; VReg_64:%vreg593,%vreg591
	Joined. Result = %vreg591 [7536r,7648r:0)  0@7536r
7632B	%vreg592<def> = COPY %vreg591:sub0; VReg_32:%vreg592 VReg_64:%vreg591
	Considering merging to VReg_64 with %vreg592 in %vreg591:sub0
		RHS = %vreg592 [7632r,7680r:0)  0@7632r
		LHS = %vreg591 [7536r,7648r:0)  0@7536r
		merge %vreg592:0@7632r into %vreg591:0@7536r --> @7536r
		erased:	7632r	%vreg592<def> = COPY %vreg591:sub0; VReg_32:%vreg592 VReg_64:%vreg591
		updated: 7680B	%vreg580<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg591:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580 VReg_128:%vreg562 VReg_64:%vreg591
	Joined. Result = %vreg591 [7536r,7680r:0)  0@7536r
7648B	%vreg593<def> = COPY %vreg591; VReg_64:%vreg593,%vreg591
	Considering merging to VReg_64 with %vreg591 in %vreg593
		RHS = %vreg591 [7536r,7680r:0)  0@7536r
		LHS = %vreg593 [7648r,7664r:0)  0@7648r
		merge %vreg593:0@7648r into %vreg591:0@7536r --> @7536r
		erased:	7648r	%vreg593<def> = COPY %vreg591; VReg_64:%vreg593,%vreg591
		updated: 7536B	%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
		updated: 7680B	%vreg580<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg580 VReg_128:%vreg562 VReg_64:%vreg593
	Joined. Result = %vreg593 [7536r,7680r:0)  0@7536r
7664B	%vreg594<def> = COPY %vreg593:sub1; VReg_32:%vreg594 VReg_64:%vreg593
	Considering merging to VReg_64 with %vreg594 in %vreg593:sub1
		RHS = %vreg594 [7664r,7696r:0)  0@7664r
		LHS = %vreg593 [7536r,7680r:0)  0@7536r
		merge %vreg594:0@7664r into %vreg593:0@7536r --> @7536r
		erased:	7664r	%vreg594<def> = COPY %vreg593:sub1; VReg_32:%vreg594 VReg_64:%vreg593
		updated: 7696B	%vreg581<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg581 VReg_128:%vreg562 VReg_64:%vreg593
	Joined. Result = %vreg593 [7536r,7696r:0)  0@7536r
7712B	%vreg582:sub0<def,read-undef> = COPY %vreg580; VReg_64:%vreg582 VReg_32:%vreg580
	Considering merging to VReg_64 with %vreg580 in %vreg582:sub0
		RHS = %vreg580 [7680r,7712r:0)  0@7680r
		LHS = %vreg582 [7712r,7728r:1)[7728r,7744r:0)  0@7728r 1@7712r
		merge %vreg582:1@7712r into %vreg580:0@7680r --> @7680r
		erased:	7712r	%vreg582:sub0<def,read-undef> = COPY %vreg580; VReg_64:%vreg582 VReg_32:%vreg580
		updated: 7680B	%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
	Joined. Result = %vreg582 [7680r,7728r:0)[7728r,7744r:1)  0@7680r 1@7728r
7728B	%vreg582:sub1<def> = COPY %vreg581; VReg_64:%vreg582 VReg_32:%vreg581
	Considering merging to VReg_64 with %vreg581 in %vreg582:sub1
		RHS = %vreg581 [7696r,7728r:0)  0@7696r
		LHS = %vreg582 [7680r,7728r:0)[7728r,7744r:1)  0@7680r 1@7728r
		merge %vreg582:1@7728r into %vreg581:0@7696r --> @7696r
		pruned %vreg582 at 7696r: %vreg582 [7680r,7696r:0)[7728r,7744r:1)  0@7680r 1@7728r
		erased:	7728r	%vreg582:sub1<def> = COPY %vreg581; VReg_64:%vreg582 VReg_32:%vreg581
		restoring liveness to 2 points: %vreg582 [7680r,7696r:0)[7696r,7744r:1)  0@7680r 1@7696r
		updated: 7696B	%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
	Joined. Result = %vreg582 [7680r,7696r:0)[7696r,7744r:1)  0@7680r 1@7696r
7760B	%vreg239<def> = COPY %vreg235; VReg_64:%vreg239 SGPR_64:%vreg235
	Not coalescable.
7776B	%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg712
		RHS = %vreg712 [7776r,7792r:0)  0@7776r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg712:0@7776r into %vreg687:1@4640r --> @4640r
		erased:	7776r	%vreg712<def> = COPY %vreg687; VReg_128:%vreg712,%vreg687
		updated: 7792B	%vreg713<def> = COPY %vreg687:sub0; VReg_32:%vreg713 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
7792B	%vreg713<def> = COPY %vreg687:sub0; VReg_32:%vreg713 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg713 in %vreg687:sub0
		RHS = %vreg713 [7792r,7904r:0)  0@7792r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg713:0@7792r into %vreg687:1@4640r --> @4640r
		erased:	7792r	%vreg713<def> = COPY %vreg687:sub0; VReg_32:%vreg713 VReg_128:%vreg687
		updated: 7904B	%vreg705<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg717, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705,%vreg717 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
7808B	%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg714
		RHS = %vreg714 [7808r,7824r:0)  0@7808r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg714:0@7808r into %vreg687:1@4640r --> @4640r
		erased:	7808r	%vreg714<def> = COPY %vreg687; VReg_128:%vreg714,%vreg687
		updated: 7824B	%vreg715<def> = COPY %vreg687:sub1; VReg_32:%vreg715 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
7824B	%vreg715<def> = COPY %vreg687:sub1; VReg_32:%vreg715 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg715 in %vreg687:sub1
		RHS = %vreg715 [7824r,7920r:0)  0@7824r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg715:0@7824r into %vreg687:1@4640r --> @4640r
		erased:	7824r	%vreg715<def> = COPY %vreg687:sub1; VReg_32:%vreg715 VReg_128:%vreg687
		updated: 7920B	%vreg706<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg719, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg706,%vreg719 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
7840B	%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
	Considering merging to VReg_64 with %vreg239 in %vreg716
		RHS = %vreg239 [7760r,7872r:0)  0@7760r
		LHS = %vreg716 [7840r,7856r:0)  0@7840r
		merge %vreg716:0@7840r into %vreg239:0@7760r --> @7760r
		erased:	7840r	%vreg716<def> = COPY %vreg239; VReg_64:%vreg716,%vreg239
		updated: 7760B	%vreg716<def> = COPY %vreg235; VReg_64:%vreg716 SGPR_64:%vreg235
		updated: 7872B	%vreg718<def> = COPY %vreg716; VReg_64:%vreg718,%vreg716
	Joined. Result = %vreg716 [7760r,7872r:0)  0@7760r
7856B	%vreg717<def> = COPY %vreg716:sub0; VReg_32:%vreg717 VReg_64:%vreg716
	Considering merging to VReg_64 with %vreg717 in %vreg716:sub0
		RHS = %vreg717 [7856r,7904r:0)  0@7856r
		LHS = %vreg716 [7760r,7872r:0)  0@7760r
		merge %vreg717:0@7856r into %vreg716:0@7760r --> @7760r
		erased:	7856r	%vreg717<def> = COPY %vreg716:sub0; VReg_32:%vreg717 VReg_64:%vreg716
		updated: 7904B	%vreg705<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg716:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705 VReg_128:%vreg687 VReg_64:%vreg716
	Joined. Result = %vreg716 [7760r,7904r:0)  0@7760r
7872B	%vreg718<def> = COPY %vreg716; VReg_64:%vreg718,%vreg716
	Considering merging to VReg_64 with %vreg716 in %vreg718
		RHS = %vreg716 [7760r,7904r:0)  0@7760r
		LHS = %vreg718 [7872r,7888r:0)  0@7872r
		merge %vreg718:0@7872r into %vreg716:0@7760r --> @7760r
		erased:	7872r	%vreg718<def> = COPY %vreg716; VReg_64:%vreg718,%vreg716
		updated: 7760B	%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
		updated: 7904B	%vreg705<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg705 VReg_128:%vreg687 VReg_64:%vreg718
	Joined. Result = %vreg718 [7760r,7904r:0)  0@7760r
7888B	%vreg719<def> = COPY %vreg718:sub1; VReg_32:%vreg719 VReg_64:%vreg718
	Considering merging to VReg_64 with %vreg719 in %vreg718:sub1
		RHS = %vreg719 [7888r,7920r:0)  0@7888r
		LHS = %vreg718 [7760r,7904r:0)  0@7760r
		merge %vreg719:0@7888r into %vreg718:0@7760r --> @7760r
		erased:	7888r	%vreg719<def> = COPY %vreg718:sub1; VReg_32:%vreg719 VReg_64:%vreg718
		updated: 7920B	%vreg706<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg706 VReg_128:%vreg687 VReg_64:%vreg718
	Joined. Result = %vreg718 [7760r,7920r:0)  0@7760r
7936B	%vreg707:sub0<def,read-undef> = COPY %vreg705; VReg_64:%vreg707 VReg_32:%vreg705
	Considering merging to VReg_64 with %vreg705 in %vreg707:sub0
		RHS = %vreg705 [7904r,7936r:0)  0@7904r
		LHS = %vreg707 [7936r,7952r:1)[7952r,7968r:0)  0@7952r 1@7936r
		merge %vreg707:1@7936r into %vreg705:0@7904r --> @7904r
		erased:	7936r	%vreg707:sub0<def,read-undef> = COPY %vreg705; VReg_64:%vreg707 VReg_32:%vreg705
		updated: 7904B	%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
	Joined. Result = %vreg707 [7904r,7952r:0)[7952r,7968r:1)  0@7904r 1@7952r
7952B	%vreg707:sub1<def> = COPY %vreg706; VReg_64:%vreg707 VReg_32:%vreg706
	Considering merging to VReg_64 with %vreg706 in %vreg707:sub1
		RHS = %vreg706 [7920r,7952r:0)  0@7920r
		LHS = %vreg707 [7904r,7952r:0)[7952r,7968r:1)  0@7904r 1@7952r
		merge %vreg707:1@7952r into %vreg706:0@7920r --> @7920r
		pruned %vreg707 at 7920r: %vreg707 [7904r,7920r:0)[7952r,7968r:1)  0@7904r 1@7952r
		erased:	7952r	%vreg707:sub1<def> = COPY %vreg706; VReg_64:%vreg707 VReg_32:%vreg706
		restoring liveness to 2 points: %vreg707 [7904r,7920r:0)[7920r,7968r:1)  0@7904r 1@7920r
		updated: 7920B	%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
	Joined. Result = %vreg707 [7904r,7920r:0)[7920r,7968r:1)  0@7904r 1@7920r
8016B	%vreg243:sub0<def,read-undef> = COPY %vreg242; SGPR_64:%vreg243 SReg_32:%vreg242
	Considering merging to SGPR_64 with %vreg242 in %vreg243:sub0
		RHS = %vreg242 [1952r,2096B:0)[3552B,9808B:0)  0@1952r
		LHS = %vreg243 [8016r,8032r:1)[8032r,8272r:0)  0@8032r 1@8016r
		merge %vreg243:1@8016r into %vreg242:0@1952r --> @1952r
		pruned %vreg242 at 8032r: %vreg242 [1952r,2096B:0)  0@1952r
		pruned all of %vreg243 at 8016r: %vreg243 [8032r,8272r:0)  0@8032r 1@8016r
		erased:	8016r	%vreg243:sub0<def,read-undef> = COPY %vreg242; SGPR_64:%vreg243 SReg_32:%vreg242
		restoring liveness to 4 points: %vreg243 [1952r,2096B:0)[8032r,8272r:1)  0@1952r 1@8032r
		updated: 1952B	%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
	Joined. Result = %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
8032B	%vreg243:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg243,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg243
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
		interference at %vreg243:0@1952r
	Interference!
8048B	%vreg245<def> = COPY %vreg243; VReg_64:%vreg245 SGPR_64:%vreg243
	Not coalescable.
8064B	%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg572
		RHS = %vreg572 [8064r,8080r:0)  0@8064r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg572:0@8064r into %vreg562:1@4288r --> @4288r
		erased:	8064r	%vreg572<def> = COPY %vreg562; VReg_128:%vreg572,%vreg562
		updated: 8080B	%vreg573<def> = COPY %vreg562:sub0; VReg_32:%vreg573 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
8080B	%vreg573<def> = COPY %vreg562:sub0; VReg_32:%vreg573 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg573 in %vreg562:sub0
		RHS = %vreg573 [8080r,8192r:0)  0@8080r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg573:0@8080r into %vreg562:1@4288r --> @4288r
		erased:	8080r	%vreg573<def> = COPY %vreg562:sub0; VReg_32:%vreg573 VReg_128:%vreg562
		updated: 8192B	%vreg565<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg577, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565,%vreg577 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
8096B	%vreg574<def> = COPY %vreg562; VReg_128:%vreg574,%vreg562
	Considering merging to VReg_128 with %vreg562 in %vreg574
		RHS = %vreg574 [8096r,8112r:0)  0@8096r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg574:0@8096r into %vreg562:1@4288r --> @4288r
		erased:	8096r	%vreg574<def> = COPY %vreg562; VReg_128:%vreg574,%vreg562
		updated: 8112B	%vreg575<def> = COPY %vreg562:sub1; VReg_32:%vreg575 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
8112B	%vreg575<def> = COPY %vreg562:sub1; VReg_32:%vreg575 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg575 in %vreg562:sub1
		RHS = %vreg575 [8112r,8208r:0)  0@8112r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg575:0@8112r into %vreg562:1@4288r --> @4288r
		erased:	8112r	%vreg575<def> = COPY %vreg562:sub1; VReg_32:%vreg575 VReg_128:%vreg562
		updated: 8208B	%vreg566<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg579, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg566,%vreg579 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
8128B	%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
	Considering merging to VReg_64 with %vreg245 in %vreg576
		RHS = %vreg245 [8048r,8160r:0)  0@8048r
		LHS = %vreg576 [8128r,8144r:0)  0@8128r
		merge %vreg576:0@8128r into %vreg245:0@8048r --> @8048r
		erased:	8128r	%vreg576<def> = COPY %vreg245; VReg_64:%vreg576,%vreg245
		updated: 8048B	%vreg576<def> = COPY %vreg243; VReg_64:%vreg576 SGPR_64:%vreg243
		updated: 8160B	%vreg578<def> = COPY %vreg576; VReg_64:%vreg578,%vreg576
	Joined. Result = %vreg576 [8048r,8160r:0)  0@8048r
8144B	%vreg577<def> = COPY %vreg576:sub0; VReg_32:%vreg577 VReg_64:%vreg576
	Considering merging to VReg_64 with %vreg577 in %vreg576:sub0
		RHS = %vreg577 [8144r,8192r:0)  0@8144r
		LHS = %vreg576 [8048r,8160r:0)  0@8048r
		merge %vreg577:0@8144r into %vreg576:0@8048r --> @8048r
		erased:	8144r	%vreg577<def> = COPY %vreg576:sub0; VReg_32:%vreg577 VReg_64:%vreg576
		updated: 8192B	%vreg565<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg576:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565 VReg_128:%vreg562 VReg_64:%vreg576
	Joined. Result = %vreg576 [8048r,8192r:0)  0@8048r
8160B	%vreg578<def> = COPY %vreg576; VReg_64:%vreg578,%vreg576
	Considering merging to VReg_64 with %vreg576 in %vreg578
		RHS = %vreg576 [8048r,8192r:0)  0@8048r
		LHS = %vreg578 [8160r,8176r:0)  0@8160r
		merge %vreg578:0@8160r into %vreg576:0@8048r --> @8048r
		erased:	8160r	%vreg578<def> = COPY %vreg576; VReg_64:%vreg578,%vreg576
		updated: 8048B	%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
		updated: 8192B	%vreg565<def> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg565 VReg_128:%vreg562 VReg_64:%vreg578
	Joined. Result = %vreg578 [8048r,8192r:0)  0@8048r
8176B	%vreg579<def> = COPY %vreg578:sub1; VReg_32:%vreg579 VReg_64:%vreg578
	Considering merging to VReg_64 with %vreg579 in %vreg578:sub1
		RHS = %vreg579 [8176r,8208r:0)  0@8176r
		LHS = %vreg578 [8048r,8192r:0)  0@8048r
		merge %vreg579:0@8176r into %vreg578:0@8048r --> @8048r
		erased:	8176r	%vreg579<def> = COPY %vreg578:sub1; VReg_32:%vreg579 VReg_64:%vreg578
		updated: 8208B	%vreg566<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg566 VReg_128:%vreg562 VReg_64:%vreg578
	Joined. Result = %vreg578 [8048r,8208r:0)  0@8048r
8224B	%vreg567:sub0<def,read-undef> = COPY %vreg565; VReg_64:%vreg567 VReg_32:%vreg565
	Considering merging to VReg_64 with %vreg565 in %vreg567:sub0
		RHS = %vreg565 [8192r,8224r:0)  0@8192r
		LHS = %vreg567 [8224r,8240r:1)[8240r,8256r:0)  0@8240r 1@8224r
		merge %vreg567:1@8224r into %vreg565:0@8192r --> @8192r
		erased:	8224r	%vreg567:sub0<def,read-undef> = COPY %vreg565; VReg_64:%vreg567 VReg_32:%vreg565
		updated: 8192B	%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
	Joined. Result = %vreg567 [8192r,8240r:0)[8240r,8256r:1)  0@8192r 1@8240r
8240B	%vreg567:sub1<def> = COPY %vreg566; VReg_64:%vreg567 VReg_32:%vreg566
	Considering merging to VReg_64 with %vreg566 in %vreg567:sub1
		RHS = %vreg566 [8208r,8240r:0)  0@8208r
		LHS = %vreg567 [8192r,8240r:0)[8240r,8256r:1)  0@8192r 1@8240r
		merge %vreg567:1@8240r into %vreg566:0@8208r --> @8208r
		pruned %vreg567 at 8208r: %vreg567 [8192r,8208r:0)[8240r,8256r:1)  0@8192r 1@8240r
		erased:	8240r	%vreg567:sub1<def> = COPY %vreg566; VReg_64:%vreg567 VReg_32:%vreg566
		restoring liveness to 2 points: %vreg567 [8192r,8208r:0)[8208r,8256r:1)  0@8192r 1@8208r
		updated: 8208B	%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
	Joined. Result = %vreg567 [8192r,8208r:0)[8208r,8256r:1)  0@8192r 1@8208r
8272B	%vreg247<def> = COPY %vreg243; VReg_64:%vreg247 SGPR_64:%vreg243
	Not coalescable.
8288B	%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg697
		RHS = %vreg697 [8288r,8304r:0)  0@8288r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg697:0@8288r into %vreg687:1@4640r --> @4640r
		erased:	8288r	%vreg697<def> = COPY %vreg687; VReg_128:%vreg697,%vreg687
		updated: 8304B	%vreg698<def> = COPY %vreg687:sub0; VReg_32:%vreg698 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
8304B	%vreg698<def> = COPY %vreg687:sub0; VReg_32:%vreg698 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg698 in %vreg687:sub0
		RHS = %vreg698 [8304r,8416r:0)  0@8304r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg698:0@8304r into %vreg687:1@4640r --> @4640r
		erased:	8304r	%vreg698<def> = COPY %vreg687:sub0; VReg_32:%vreg698 VReg_128:%vreg687
		updated: 8416B	%vreg690<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg702, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690,%vreg702 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
8320B	%vreg699<def> = COPY %vreg687; VReg_128:%vreg699,%vreg687
	Considering merging to VReg_128 with %vreg687 in %vreg699
		RHS = %vreg699 [8320r,8336r:0)  0@8320r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg699:0@8320r into %vreg687:1@4640r --> @4640r
		erased:	8320r	%vreg699<def> = COPY %vreg687; VReg_128:%vreg699,%vreg687
		updated: 8336B	%vreg700<def> = COPY %vreg687:sub1; VReg_32:%vreg700 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
8336B	%vreg700<def> = COPY %vreg687:sub1; VReg_32:%vreg700 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg700 in %vreg687:sub1
		RHS = %vreg700 [8336r,8432r:0)  0@8336r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg700:0@8336r into %vreg687:1@4640r --> @4640r
		erased:	8336r	%vreg700<def> = COPY %vreg687:sub1; VReg_32:%vreg700 VReg_128:%vreg687
		updated: 8432B	%vreg691<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg704, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg691,%vreg704 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
8352B	%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
	Considering merging to VReg_64 with %vreg247 in %vreg701
		RHS = %vreg247 [8272r,8384r:0)  0@8272r
		LHS = %vreg701 [8352r,8368r:0)  0@8352r
		merge %vreg701:0@8352r into %vreg247:0@8272r --> @8272r
		erased:	8352r	%vreg701<def> = COPY %vreg247; VReg_64:%vreg701,%vreg247
		updated: 8272B	%vreg701<def> = COPY %vreg243; VReg_64:%vreg701 SGPR_64:%vreg243
		updated: 8384B	%vreg703<def> = COPY %vreg701; VReg_64:%vreg703,%vreg701
	Joined. Result = %vreg701 [8272r,8384r:0)  0@8272r
8368B	%vreg702<def> = COPY %vreg701:sub0; VReg_32:%vreg702 VReg_64:%vreg701
	Considering merging to VReg_64 with %vreg702 in %vreg701:sub0
		RHS = %vreg702 [8368r,8416r:0)  0@8368r
		LHS = %vreg701 [8272r,8384r:0)  0@8272r
		merge %vreg702:0@8368r into %vreg701:0@8272r --> @8272r
		erased:	8368r	%vreg702<def> = COPY %vreg701:sub0; VReg_32:%vreg702 VReg_64:%vreg701
		updated: 8416B	%vreg690<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg701:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690 VReg_128:%vreg687 VReg_64:%vreg701
	Joined. Result = %vreg701 [8272r,8416r:0)  0@8272r
8384B	%vreg703<def> = COPY %vreg701; VReg_64:%vreg703,%vreg701
	Considering merging to VReg_64 with %vreg701 in %vreg703
		RHS = %vreg701 [8272r,8416r:0)  0@8272r
		LHS = %vreg703 [8384r,8400r:0)  0@8384r
		merge %vreg703:0@8384r into %vreg701:0@8272r --> @8272r
		erased:	8384r	%vreg703<def> = COPY %vreg701; VReg_64:%vreg703,%vreg701
		updated: 8272B	%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
		updated: 8416B	%vreg690<def> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg690 VReg_128:%vreg687 VReg_64:%vreg703
	Joined. Result = %vreg703 [8272r,8416r:0)  0@8272r
8400B	%vreg704<def> = COPY %vreg703:sub1; VReg_32:%vreg704 VReg_64:%vreg703
	Considering merging to VReg_64 with %vreg704 in %vreg703:sub1
		RHS = %vreg704 [8400r,8432r:0)  0@8400r
		LHS = %vreg703 [8272r,8416r:0)  0@8272r
		merge %vreg704:0@8400r into %vreg703:0@8272r --> @8272r
		erased:	8400r	%vreg704<def> = COPY %vreg703:sub1; VReg_32:%vreg704 VReg_64:%vreg703
		updated: 8432B	%vreg691<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_32:%vreg691 VReg_128:%vreg687 VReg_64:%vreg703
	Joined. Result = %vreg703 [8272r,8432r:0)  0@8272r
8448B	%vreg692:sub0<def,read-undef> = COPY %vreg690; VReg_64:%vreg692 VReg_32:%vreg690
	Considering merging to VReg_64 with %vreg690 in %vreg692:sub0
		RHS = %vreg690 [8416r,8448r:0)  0@8416r
		LHS = %vreg692 [8448r,8464r:1)[8464r,8480r:0)  0@8464r 1@8448r
		merge %vreg692:1@8448r into %vreg690:0@8416r --> @8416r
		erased:	8448r	%vreg692:sub0<def,read-undef> = COPY %vreg690; VReg_64:%vreg692 VReg_32:%vreg690
		updated: 8416B	%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
	Joined. Result = %vreg692 [8416r,8464r:0)[8464r,8480r:1)  0@8416r 1@8464r
8464B	%vreg692:sub1<def> = COPY %vreg691; VReg_64:%vreg692 VReg_32:%vreg691
	Considering merging to VReg_64 with %vreg691 in %vreg692:sub1
		RHS = %vreg691 [8432r,8464r:0)  0@8432r
		LHS = %vreg692 [8416r,8464r:0)[8464r,8480r:1)  0@8416r 1@8464r
		merge %vreg692:1@8464r into %vreg691:0@8432r --> @8432r
		pruned %vreg692 at 8432r: %vreg692 [8416r,8432r:0)[8464r,8480r:1)  0@8416r 1@8464r
		erased:	8464r	%vreg692:sub1<def> = COPY %vreg691; VReg_64:%vreg692 VReg_32:%vreg691
		restoring liveness to 2 points: %vreg692 [8416r,8432r:0)[8432r,8480r:1)  0@8416r 1@8432r
		updated: 8432B	%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
	Joined. Result = %vreg692 [8416r,8432r:0)[8432r,8480r:1)  0@8416r 1@8432r
8528B	%vreg250:sub0<def,read-undef> = COPY %vreg249; VReg_512:%vreg250 VGPR_32:%vreg249
	Considering merging to VReg_512 with %vreg249 in %vreg250:sub0
		RHS = %vreg249 [8512r,8528r:0)  0@8512r
		LHS = %vreg250 [8528r,8544r:15)[8544r,8560r:14)[8560r,8576r:13)[8576r,8592r:12)[8592r,8608r:11)[8608r,8624r:10)[8624r,8640r:9)[8640r,8656r:8)[8656r,8672r:7)[8672r,8688r:6)[8688r,8704r:5)[8704r,8720r:4)[8720r,8736r:3)[8736r,8752r:2)[8752r,8768r:1)[8768r,9248r:0)  0@8768r 1@8752r 2@8736r 3@8720r 4@8704r 5@8688r 6@8672r 7@8656r 8@8640r 9@8624r 10@8608r 11@8592r 12@8576r 13@8560r 14@8544r 15@8528r
		merge %vreg250:15@8528r into %vreg249:0@8512r --> @8512r
		erased:	8528r	%vreg250:sub0<def,read-undef> = COPY %vreg249; VReg_512:%vreg250 VGPR_32:%vreg249
AllocationOrder(VReg_512) = [ %VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15 %VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16 %VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18 %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19 %VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20 %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21 %VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22 %VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23 %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24 %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25 %VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26 %VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27 %VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28 %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29 %VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30 %VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31 %VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32 %VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33 %VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34 %VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35 %VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36 %VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37 %VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38 %VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39 %VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40 %VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41 %VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42 %VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43 %VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44 %VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45 %VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46 %VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47 %VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48 %VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49 %VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50 %VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51 %VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52 %VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53 %VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54 %VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55 %VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56 %VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57 %VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58 %VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59 %VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60 %VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61 %VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62 %VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63 %VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64 %VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65 %VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66 %VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67 %VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68 %VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69 %VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70 %VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71 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%VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182 %VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183 %VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184 %VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185 %VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186 %VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187 %VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188 %VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189 %VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190 %VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191 %VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192 %VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193 %VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194 %VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195 %VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196 %VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197 %VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198 %VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199 %VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200 %VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201 %VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202 %VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203 %VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204 %VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205 %VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206 %VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207 %VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208 %VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209 %VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210 %VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211 %VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212 %VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213 %VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214 %VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215 %VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216 %VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217 %VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218 %VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219 %VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220 %VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221 %VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222 %VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223 %VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224 %VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225 %VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226 %VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227 %VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228 %VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229 %VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230 %VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231 %VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232 %VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233 %VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234 %VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235 %VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236 %VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237 %VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238 %VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239 %VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240 %VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241 %VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242 %VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243 %VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244 %VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245 %VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246 %VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247 %VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248 %VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249 %VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250 %VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251 %VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252 %VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253 %VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254 %VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255 ]
		updated: 8512B	%vreg250:sub0<def,read-undef> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
	Joined. Result = %vreg250 [8512r,8544r:0)[8544r,8560r:1)[8560r,8576r:2)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@8512r 1@8544r 2@8560r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8544B	%vreg250:sub1<def> = COPY %vreg241; VReg_512:%vreg250 VGPR_32:%vreg241
	Considering merging to VReg_512 with %vreg241 in %vreg250:sub1
		RHS = %vreg241 [8000r,8544r:0)  0@8000r
		LHS = %vreg250 [8512r,8544r:0)[8544r,8560r:1)[8560r,8576r:2)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@8512r 1@8544r 2@8560r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:1@8544r into %vreg241:0@8000r --> @8000r
		pruned %vreg241 at 8512r: %vreg241 [8000r,8512r:0)  0@8000r
		pruned all of %vreg250 at 8544r: %vreg250 [8512r,8544r:0)[8560r,8576r:2)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@8512r 1@8544r 2@8560r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8544r	%vreg250:sub1<def> = COPY %vreg241; VReg_512:%vreg250 VGPR_32:%vreg241
		restoring liveness to 3 points: %vreg250 [8000r,8512r:0)[8512r,8544r:1)[8560r,8576r:2)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@8000r 1@8512r 2@8560r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 8000B	%vreg250:sub1<def,read-undef> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
	Joined. Result = %vreg250 [8000r,8512r:0)[8512r,8560r:1)[8560r,8576r:2)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@8000r 1@8512r 2@8560r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8560B	%vreg250:sub2<def> = COPY %vreg233; VReg_512:%vreg250 VGPR_32:%vreg233
	Considering merging to VReg_512 with %vreg233 in %vreg250:sub2
		RHS = %vreg233 [7488r,8560r:0)  0@7488r
		LHS = %vreg250 [8000r,8512r:0)[8512r,8560r:1)[8560r,8576r:2)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@8000r 1@8512r 2@8560r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:2@8560r into %vreg233:0@7488r --> @7488r
		pruned %vreg233 at 8000r: %vreg233 [7488r,8000r:0)  0@7488r
		pruned %vreg233 at 8512r: %vreg233 [7488r,8000r:0)  0@7488r
		pruned all of %vreg250 at 8560r: %vreg250 [8000r,8512r:0)[8512r,8560r:1)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@8000r 1@8512r 2@8560r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8560r	%vreg250:sub2<def> = COPY %vreg233; VReg_512:%vreg250 VGPR_32:%vreg233
		restoring liveness to 4 points: %vreg250 [7488r,8000r:0)[8000r,8512r:1)[8512r,8560r:2)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@7488r 1@8000r 2@8512r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 7488B	%vreg250:sub2<def,read-undef> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
	Joined. Result = %vreg250 [7488r,8000r:0)[8000r,8512r:1)[8512r,8576r:2)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@7488r 1@8000r 2@8512r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8576B	%vreg250:sub3<def> = COPY %vreg225; VReg_512:%vreg250 VGPR_32:%vreg225
	Considering merging to VReg_512 with %vreg225 in %vreg250:sub3
		RHS = %vreg225 [6976r,8576r:0)  0@6976r
		LHS = %vreg250 [7488r,8000r:0)[8000r,8512r:1)[8512r,8576r:2)[8576r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@7488r 1@8000r 2@8512r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:3@8576r into %vreg225:0@6976r --> @6976r
		pruned %vreg225 at 7488r: %vreg225 [6976r,7488r:0)  0@6976r
		pruned %vreg225 at 8000r: %vreg225 [6976r,7488r:0)  0@6976r
		pruned %vreg225 at 8512r: %vreg225 [6976r,7488r:0)  0@6976r
		pruned all of %vreg250 at 8576r: %vreg250 [7488r,8000r:0)[8000r,8512r:1)[8512r,8576r:2)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@7488r 1@8000r 2@8512r 3@8576r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8576r	%vreg250:sub3<def> = COPY %vreg225; VReg_512:%vreg250 VGPR_32:%vreg225
		restoring liveness to 5 points: %vreg250 [6976r,7488r:0)[7488r,8000r:1)[8000r,8512r:2)[8512r,8576r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@6976r 1@7488r 2@8000r 3@8512r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 6976B	%vreg250:sub3<def,read-undef> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
	Joined. Result = %vreg250 [6976r,7488r:0)[7488r,8000r:1)[8000r,8512r:2)[8512r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@6976r 1@7488r 2@8000r 3@8512r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8592B	%vreg250:sub4<def> = COPY %vreg217; VReg_512:%vreg250 VGPR_32:%vreg217
	Considering merging to VReg_512 with %vreg217 in %vreg250:sub4
		RHS = %vreg217 [6464r,8592r:0)  0@6464r
		LHS = %vreg250 [6976r,7488r:0)[7488r,8000r:1)[8000r,8512r:2)[8512r,8592r:3)[8592r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@6976r 1@7488r 2@8000r 3@8512r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:4@8592r into %vreg217:0@6464r --> @6464r
		pruned %vreg217 at 6976r: %vreg217 [6464r,6976r:0)  0@6464r
		pruned %vreg217 at 7488r: %vreg217 [6464r,6976r:0)  0@6464r
		pruned %vreg217 at 8000r: %vreg217 [6464r,6976r:0)  0@6464r
		pruned %vreg217 at 8512r: %vreg217 [6464r,6976r:0)  0@6464r
		pruned all of %vreg250 at 8592r: %vreg250 [6976r,7488r:0)[7488r,8000r:1)[8000r,8512r:2)[8512r,8592r:3)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@6976r 1@7488r 2@8000r 3@8512r 4@8592r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8592r	%vreg250:sub4<def> = COPY %vreg217; VReg_512:%vreg250 VGPR_32:%vreg217
		restoring liveness to 6 points: %vreg250 [6464r,6976r:0)[6976r,7488r:1)[7488r,8000r:2)[8000r,8512r:3)[8512r,8592r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@6464r 1@6976r 2@7488r 3@8000r 4@8512r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 6464B	%vreg250:sub4<def,read-undef> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
	Joined. Result = %vreg250 [6464r,6976r:0)[6976r,7488r:1)[7488r,8000r:2)[8000r,8512r:3)[8512r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@6464r 1@6976r 2@7488r 3@8000r 4@8512r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8608B	%vreg250:sub5<def> = COPY %vreg209; VReg_512:%vreg250 VGPR_32:%vreg209
	Considering merging to VReg_512 with %vreg209 in %vreg250:sub5
		RHS = %vreg209 [5952r,8608r:0)  0@5952r
		LHS = %vreg250 [6464r,6976r:0)[6976r,7488r:1)[7488r,8000r:2)[8000r,8512r:3)[8512r,8608r:4)[8608r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@6464r 1@6976r 2@7488r 3@8000r 4@8512r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:5@8608r into %vreg209:0@5952r --> @5952r
		pruned %vreg209 at 6464r: %vreg209 [5952r,6464r:0)  0@5952r
		pruned %vreg209 at 6976r: %vreg209 [5952r,6464r:0)  0@5952r
		pruned %vreg209 at 7488r: %vreg209 [5952r,6464r:0)  0@5952r
		pruned %vreg209 at 8000r: %vreg209 [5952r,6464r:0)  0@5952r
		pruned %vreg209 at 8512r: %vreg209 [5952r,6464r:0)  0@5952r
		pruned all of %vreg250 at 8608r: %vreg250 [6464r,6976r:0)[6976r,7488r:1)[7488r,8000r:2)[8000r,8512r:3)[8512r,8608r:4)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@6464r 1@6976r 2@7488r 3@8000r 4@8512r 5@8608r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8608r	%vreg250:sub5<def> = COPY %vreg209; VReg_512:%vreg250 VGPR_32:%vreg209
		restoring liveness to 7 points: %vreg250 [5952r,6464r:0)[6464r,6976r:1)[6976r,7488r:2)[7488r,8000r:3)[8000r,8512r:4)[8512r,8608r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@5952r 1@6464r 2@6976r 3@7488r 4@8000r 5@8512r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 5952B	%vreg250:sub5<def,read-undef> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
	Joined. Result = %vreg250 [5952r,6464r:0)[6464r,6976r:1)[6976r,7488r:2)[7488r,8000r:3)[8000r,8512r:4)[8512r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@5952r 1@6464r 2@6976r 3@7488r 4@8000r 5@8512r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8624B	%vreg250:sub6<def> = COPY %vreg201; VReg_512:%vreg250 VGPR_32:%vreg201
	Considering merging to VReg_512 with %vreg201 in %vreg250:sub6
		RHS = %vreg201 [5440r,8624r:0)  0@5440r
		LHS = %vreg250 [5952r,6464r:0)[6464r,6976r:1)[6976r,7488r:2)[7488r,8000r:3)[8000r,8512r:4)[8512r,8624r:5)[8624r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@5952r 1@6464r 2@6976r 3@7488r 4@8000r 5@8512r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:6@8624r into %vreg201:0@5440r --> @5440r
		pruned %vreg201 at 5952r: %vreg201 [5440r,5952r:0)  0@5440r
		pruned %vreg201 at 6464r: %vreg201 [5440r,5952r:0)  0@5440r
		pruned %vreg201 at 6976r: %vreg201 [5440r,5952r:0)  0@5440r
		pruned %vreg201 at 7488r: %vreg201 [5440r,5952r:0)  0@5440r
		pruned %vreg201 at 8000r: %vreg201 [5440r,5952r:0)  0@5440r
		pruned %vreg201 at 8512r: %vreg201 [5440r,5952r:0)  0@5440r
		pruned all of %vreg250 at 8624r: %vreg250 [5952r,6464r:0)[6464r,6976r:1)[6976r,7488r:2)[7488r,8000r:3)[8000r,8512r:4)[8512r,8624r:5)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@5952r 1@6464r 2@6976r 3@7488r 4@8000r 5@8512r 6@8624r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8624r	%vreg250:sub6<def> = COPY %vreg201; VReg_512:%vreg250 VGPR_32:%vreg201
		restoring liveness to 8 points: %vreg250 [5440r,5952r:0)[5952r,6464r:1)[6464r,6976r:2)[6976r,7488r:3)[7488r,8000r:4)[8000r,8512r:5)[8512r,8624r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@5440r 1@5952r 2@6464r 3@6976r 4@7488r 5@8000r 6@8512r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 5440B	%vreg250:sub6<def,read-undef> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
	Joined. Result = %vreg250 [5440r,5952r:0)[5952r,6464r:1)[6464r,6976r:2)[6976r,7488r:3)[7488r,8000r:4)[8000r,8512r:5)[8512r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@5440r 1@5952r 2@6464r 3@6976r 4@7488r 5@8000r 6@8512r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8640B	%vreg250:sub7<def> = COPY %vreg193; VReg_512:%vreg250 VGPR_32:%vreg193
	Considering merging to VReg_512 with %vreg193 in %vreg250:sub7
		RHS = %vreg193 [4928r,8640r:0)  0@4928r
		LHS = %vreg250 [5440r,5952r:0)[5952r,6464r:1)[6464r,6976r:2)[6976r,7488r:3)[7488r,8000r:4)[8000r,8512r:5)[8512r,8640r:6)[8640r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@5440r 1@5952r 2@6464r 3@6976r 4@7488r 5@8000r 6@8512r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:7@8640r into %vreg193:0@4928r --> @4928r
		pruned %vreg193 at 5440r: %vreg193 [4928r,5440r:0)  0@4928r
		pruned %vreg193 at 5952r: %vreg193 [4928r,5440r:0)  0@4928r
		pruned %vreg193 at 6464r: %vreg193 [4928r,5440r:0)  0@4928r
		pruned %vreg193 at 6976r: %vreg193 [4928r,5440r:0)  0@4928r
		pruned %vreg193 at 7488r: %vreg193 [4928r,5440r:0)  0@4928r
		pruned %vreg193 at 8000r: %vreg193 [4928r,5440r:0)  0@4928r
		pruned %vreg193 at 8512r: %vreg193 [4928r,5440r:0)  0@4928r
		pruned all of %vreg250 at 8640r: %vreg250 [5440r,5952r:0)[5952r,6464r:1)[6464r,6976r:2)[6976r,7488r:3)[7488r,8000r:4)[8000r,8512r:5)[8512r,8640r:6)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@5440r 1@5952r 2@6464r 3@6976r 4@7488r 5@8000r 6@8512r 7@8640r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8640r	%vreg250:sub7<def> = COPY %vreg193; VReg_512:%vreg250 VGPR_32:%vreg193
		restoring liveness to 9 points: %vreg250 [4928r,5440r:0)[5440r,5952r:1)[5952r,6464r:2)[6464r,6976r:3)[6976r,7488r:4)[7488r,8000r:5)[8000r,8512r:6)[8512r,8640r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4928r 1@5440r 2@5952r 3@6464r 4@6976r 5@7488r 6@8000r 7@8512r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 4928B	%vreg250:sub7<def,read-undef> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
	Joined. Result = %vreg250 [4928r,5440r:0)[5440r,5952r:1)[5952r,6464r:2)[6464r,6976r:3)[6976r,7488r:4)[7488r,8000r:5)[8000r,8512r:6)[8512r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4928r 1@5440r 2@5952r 3@6464r 4@6976r 5@7488r 6@8000r 7@8512r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8656B	%vreg250:sub8<def> = COPY %vreg180; VReg_512:%vreg250 VGPR_32:%vreg180
	Considering merging to VReg_512 with %vreg180 in %vreg250:sub8
		RHS = %vreg180 [4208r,8656r:0)  0@4208r
		LHS = %vreg250 [4928r,5440r:0)[5440r,5952r:1)[5952r,6464r:2)[6464r,6976r:3)[6976r,7488r:4)[7488r,8000r:5)[8000r,8512r:6)[8512r,8656r:7)[8656r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4928r 1@5440r 2@5952r 3@6464r 4@6976r 5@7488r 6@8000r 7@8512r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:8@8656r into %vreg180:0@4208r --> @4208r
		pruned %vreg180 at 4928r: %vreg180 [4208r,4928r:0)  0@4208r
		pruned %vreg180 at 5440r: %vreg180 [4208r,4928r:0)  0@4208r
		pruned %vreg180 at 5952r: %vreg180 [4208r,4928r:0)  0@4208r
		pruned %vreg180 at 6464r: %vreg180 [4208r,4928r:0)  0@4208r
		pruned %vreg180 at 6976r: %vreg180 [4208r,4928r:0)  0@4208r
		pruned %vreg180 at 7488r: %vreg180 [4208r,4928r:0)  0@4208r
		pruned %vreg180 at 8000r: %vreg180 [4208r,4928r:0)  0@4208r
		pruned %vreg180 at 8512r: %vreg180 [4208r,4928r:0)  0@4208r
		pruned all of %vreg250 at 8656r: %vreg250 [4928r,5440r:0)[5440r,5952r:1)[5952r,6464r:2)[6464r,6976r:3)[6976r,7488r:4)[7488r,8000r:5)[8000r,8512r:6)[8512r,8656r:7)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4928r 1@5440r 2@5952r 3@6464r 4@6976r 5@7488r 6@8000r 7@8512r 8@8656r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8656r	%vreg250:sub8<def> = COPY %vreg180; VReg_512:%vreg250 VGPR_32:%vreg180
		restoring liveness to 10 points: %vreg250 [4208r,4928r:0)[4928r,5440r:1)[5440r,5952r:2)[5952r,6464r:3)[6464r,6976r:4)[6976r,7488r:5)[7488r,8000r:6)[8000r,8512r:7)[8512r,8656r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4208r 1@4928r 2@5440r 3@5952r 4@6464r 5@6976r 6@7488r 7@8000r 8@8512r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 4208B	%vreg250:sub8<def,read-undef> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
	Joined. Result = %vreg250 [4208r,4928r:0)[4928r,5440r:1)[5440r,5952r:2)[5952r,6464r:3)[6464r,6976r:4)[6976r,7488r:5)[7488r,8000r:6)[8000r,8512r:7)[8512r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4208r 1@4928r 2@5440r 3@5952r 4@6464r 5@6976r 6@7488r 7@8000r 8@8512r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8672B	%vreg250:sub9<def> = COPY %vreg176; VReg_512:%vreg250 VGPR_32:%vreg176
	Considering merging to VReg_512 with %vreg176 in %vreg250:sub9
		RHS = %vreg176 [4144r,8672r:0)  0@4144r
		LHS = %vreg250 [4208r,4928r:0)[4928r,5440r:1)[5440r,5952r:2)[5952r,6464r:3)[6464r,6976r:4)[6976r,7488r:5)[7488r,8000r:6)[8000r,8512r:7)[8512r,8672r:8)[8672r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4208r 1@4928r 2@5440r 3@5952r 4@6464r 5@6976r 6@7488r 7@8000r 8@8512r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:9@8672r into %vreg176:0@4144r --> @4144r
		pruned %vreg176 at 4208r: %vreg176 [4144r,4208r:0)  0@4144r
		pruned %vreg176 at 4928r: %vreg176 [4144r,4208r:0)  0@4144r
		pruned %vreg176 at 5440r: %vreg176 [4144r,4208r:0)  0@4144r
		pruned %vreg176 at 5952r: %vreg176 [4144r,4208r:0)  0@4144r
		pruned %vreg176 at 6464r: %vreg176 [4144r,4208r:0)  0@4144r
		pruned %vreg176 at 6976r: %vreg176 [4144r,4208r:0)  0@4144r
		pruned %vreg176 at 7488r: %vreg176 [4144r,4208r:0)  0@4144r
		pruned %vreg176 at 8000r: %vreg176 [4144r,4208r:0)  0@4144r
		pruned %vreg176 at 8512r: %vreg176 [4144r,4208r:0)  0@4144r
		pruned all of %vreg250 at 8672r: %vreg250 [4208r,4928r:0)[4928r,5440r:1)[5440r,5952r:2)[5952r,6464r:3)[6464r,6976r:4)[6976r,7488r:5)[7488r,8000r:6)[8000r,8512r:7)[8512r,8672r:8)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4208r 1@4928r 2@5440r 3@5952r 4@6464r 5@6976r 6@7488r 7@8000r 8@8512r 9@8672r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8672r	%vreg250:sub9<def> = COPY %vreg176; VReg_512:%vreg250 VGPR_32:%vreg176
		restoring liveness to 11 points: %vreg250 [4144r,4208r:0)[4208r,4928r:1)[4928r,5440r:2)[5440r,5952r:3)[5952r,6464r:4)[6464r,6976r:5)[6976r,7488r:6)[7488r,8000r:7)[8000r,8512r:8)[8512r,8672r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4144r 1@4208r 2@4928r 3@5440r 4@5952r 5@6464r 6@6976r 7@7488r 8@8000r 9@8512r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 4144B	%vreg250:sub9<def,read-undef> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
	Joined. Result = %vreg250 [4144r,4208r:0)[4208r,4928r:1)[4928r,5440r:2)[5440r,5952r:3)[5952r,6464r:4)[6464r,6976r:5)[6976r,7488r:6)[7488r,8000r:7)[8000r,8512r:8)[8512r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4144r 1@4208r 2@4928r 3@5440r 4@5952r 5@6464r 6@6976r 7@7488r 8@8000r 9@8512r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8688B	%vreg250:sub10<def> = COPY %vreg172; VReg_512:%vreg250 VGPR_32:%vreg172
	Considering merging to VReg_512 with %vreg172 in %vreg250:sub10
		RHS = %vreg172 [4080r,8688r:0)  0@4080r
		LHS = %vreg250 [4144r,4208r:0)[4208r,4928r:1)[4928r,5440r:2)[5440r,5952r:3)[5952r,6464r:4)[6464r,6976r:5)[6976r,7488r:6)[7488r,8000r:7)[8000r,8512r:8)[8512r,8688r:9)[8688r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4144r 1@4208r 2@4928r 3@5440r 4@5952r 5@6464r 6@6976r 7@7488r 8@8000r 9@8512r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:10@8688r into %vreg172:0@4080r --> @4080r
		pruned %vreg172 at 4144r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned %vreg172 at 4208r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned %vreg172 at 4928r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned %vreg172 at 5440r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned %vreg172 at 5952r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned %vreg172 at 6464r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned %vreg172 at 6976r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned %vreg172 at 7488r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned %vreg172 at 8000r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned %vreg172 at 8512r: %vreg172 [4080r,4144r:0)  0@4080r
		pruned all of %vreg250 at 8688r: %vreg250 [4144r,4208r:0)[4208r,4928r:1)[4928r,5440r:2)[5440r,5952r:3)[5952r,6464r:4)[6464r,6976r:5)[6976r,7488r:6)[7488r,8000r:7)[8000r,8512r:8)[8512r,8688r:9)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4144r 1@4208r 2@4928r 3@5440r 4@5952r 5@6464r 6@6976r 7@7488r 8@8000r 9@8512r 10@8688r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8688r	%vreg250:sub10<def> = COPY %vreg172; VReg_512:%vreg250 VGPR_32:%vreg172
		restoring liveness to 12 points: %vreg250 [4080r,4144r:0)[4144r,4208r:1)[4208r,4928r:2)[4928r,5440r:3)[5440r,5952r:4)[5952r,6464r:5)[6464r,6976r:6)[6976r,7488r:7)[7488r,8000r:8)[8000r,8512r:9)[8512r,8688r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4080r 1@4144r 2@4208r 3@4928r 4@5440r 5@5952r 6@6464r 7@6976r 8@7488r 9@8000r 10@8512r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 4080B	%vreg250:sub10<def,read-undef> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
	Joined. Result = %vreg250 [4080r,4144r:0)[4144r,4208r:1)[4208r,4928r:2)[4928r,5440r:3)[5440r,5952r:4)[5952r,6464r:5)[6464r,6976r:6)[6976r,7488r:7)[7488r,8000r:8)[8000r,8512r:9)[8512r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4080r 1@4144r 2@4208r 3@4928r 4@5440r 5@5952r 6@6464r 7@6976r 8@7488r 9@8000r 10@8512r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
8704B	%vreg250:sub11<def> = COPY %vreg168; VReg_512:%vreg250 VGPR_32:%vreg168
	Considering merging to VReg_512 with %vreg168 in %vreg250:sub11
		RHS = %vreg168 [4016r,8704r:0)  0@4016r
		LHS = %vreg250 [4080r,4144r:0)[4144r,4208r:1)[4208r,4928r:2)[4928r,5440r:3)[5440r,5952r:4)[5952r,6464r:5)[6464r,6976r:6)[6976r,7488r:7)[7488r,8000r:8)[8000r,8512r:9)[8512r,8704r:10)[8704r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4080r 1@4144r 2@4208r 3@4928r 4@5440r 5@5952r 6@6464r 7@6976r 8@7488r 9@8000r 10@8512r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:11@8704r into %vreg168:0@4016r --> @4016r
		pruned %vreg168 at 4080r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 4144r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 4208r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 4928r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 5440r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 5952r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 6464r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 6976r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 7488r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 8000r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned %vreg168 at 8512r: %vreg168 [4016r,4080r:0)  0@4016r
		pruned all of %vreg250 at 8704r: %vreg250 [4080r,4144r:0)[4144r,4208r:1)[4208r,4928r:2)[4928r,5440r:3)[5440r,5952r:4)[5952r,6464r:5)[6464r,6976r:6)[6976r,7488r:7)[7488r,8000r:8)[8000r,8512r:9)[8512r,8704r:10)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4080r 1@4144r 2@4208r 3@4928r 4@5440r 5@5952r 6@6464r 7@6976r 8@7488r 9@8000r 10@8512r 11@8704r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8704r	%vreg250:sub11<def> = COPY %vreg168; VReg_512:%vreg250 VGPR_32:%vreg168
		restoring liveness to 13 points: %vreg250 [4016r,4080r:0)[4080r,4144r:1)[4144r,4208r:2)[4208r,4928r:3)[4928r,5440r:4)[5440r,5952r:5)[5952r,6464r:6)[6464r,6976r:7)[6976r,7488r:8)[7488r,8000r:9)[8000r,8512r:10)[8512r,8704r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4016r 1@4080r 2@4144r 3@4208r 4@4928r 5@5440r 6@5952r 7@6464r 8@6976r 9@7488r 10@8000r 11@8512r 12@8720r 13@8736r 14@8752r 15@8768r
		updated: 4016B	%vreg250:sub11<def,read-undef> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
	Joined. Result = %vreg250 [4016r,4080r:0)[4080r,4144r:1)[4144r,4208r:2)[4208r,4928r:3)[4928r,5440r:4)[5440r,5952r:5)[5952r,6464r:6)[6464r,6976r:7)[6976r,7488r:8)[7488r,8000r:9)[8000r,8512r:10)[8512r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4016r 1@4080r 2@4144r 3@4208r 4@4928r 5@5440r 6@5952r 7@6464r 8@6976r 9@7488r 10@8000r 11@8512r 12@8720r 13@8736r 14@8752r 15@8768r
8720B	%vreg250:sub12<def> = COPY %vreg164; VReg_512:%vreg250 VGPR_32:%vreg164
	Considering merging to VReg_512 with %vreg164 in %vreg250:sub12
		RHS = %vreg164 [3952r,8720r:0)  0@3952r
		LHS = %vreg250 [4016r,4080r:0)[4080r,4144r:1)[4144r,4208r:2)[4208r,4928r:3)[4928r,5440r:4)[5440r,5952r:5)[5952r,6464r:6)[6464r,6976r:7)[6976r,7488r:8)[7488r,8000r:9)[8000r,8512r:10)[8512r,8720r:11)[8720r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4016r 1@4080r 2@4144r 3@4208r 4@4928r 5@5440r 6@5952r 7@6464r 8@6976r 9@7488r 10@8000r 11@8512r 12@8720r 13@8736r 14@8752r 15@8768r
		merge %vreg250:12@8720r into %vreg164:0@3952r --> @3952r
		pruned %vreg164 at 4016r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 4080r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 4144r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 4208r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 4928r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 5440r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 5952r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 6464r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 6976r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 7488r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 8000r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned %vreg164 at 8512r: %vreg164 [3952r,4016r:0)  0@3952r
		pruned all of %vreg250 at 8720r: %vreg250 [4016r,4080r:0)[4080r,4144r:1)[4144r,4208r:2)[4208r,4928r:3)[4928r,5440r:4)[5440r,5952r:5)[5952r,6464r:6)[6464r,6976r:7)[6976r,7488r:8)[7488r,8000r:9)[8000r,8512r:10)[8512r,8720r:11)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@4016r 1@4080r 2@4144r 3@4208r 4@4928r 5@5440r 6@5952r 7@6464r 8@6976r 9@7488r 10@8000r 11@8512r 12@8720r 13@8736r 14@8752r 15@8768r
		erased:	8720r	%vreg250:sub12<def> = COPY %vreg164; VReg_512:%vreg250 VGPR_32:%vreg164
		restoring liveness to 14 points: %vreg250 [3952r,4016r:0)[4016r,4080r:1)[4080r,4144r:2)[4144r,4208r:3)[4208r,4928r:4)[4928r,5440r:5)[5440r,5952r:6)[5952r,6464r:7)[6464r,6976r:8)[6976r,7488r:9)[7488r,8000r:10)[8000r,8512r:11)[8512r,8720r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@3952r 1@4016r 2@4080r 3@4144r 4@4208r 5@4928r 6@5440r 7@5952r 8@6464r 9@6976r 10@7488r 11@8000r 12@8512r 13@8736r 14@8752r 15@8768r
		updated: 3952B	%vreg250:sub12<def,read-undef> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
	Joined. Result = %vreg250 [3952r,4016r:0)[4016r,4080r:1)[4080r,4144r:2)[4144r,4208r:3)[4208r,4928r:4)[4928r,5440r:5)[5440r,5952r:6)[5952r,6464r:7)[6464r,6976r:8)[6976r,7488r:9)[7488r,8000r:10)[8000r,8512r:11)[8512r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@3952r 1@4016r 2@4080r 3@4144r 4@4208r 5@4928r 6@5440r 7@5952r 8@6464r 9@6976r 10@7488r 11@8000r 12@8512r 13@8736r 14@8752r 15@8768r
8736B	%vreg250:sub13<def> = COPY %vreg160; VReg_512:%vreg250 VGPR_32:%vreg160
	Considering merging to VReg_512 with %vreg160 in %vreg250:sub13
		RHS = %vreg160 [3888r,8736r:0)  0@3888r
		LHS = %vreg250 [3952r,4016r:0)[4016r,4080r:1)[4080r,4144r:2)[4144r,4208r:3)[4208r,4928r:4)[4928r,5440r:5)[5440r,5952r:6)[5952r,6464r:7)[6464r,6976r:8)[6976r,7488r:9)[7488r,8000r:10)[8000r,8512r:11)[8512r,8736r:12)[8736r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@3952r 1@4016r 2@4080r 3@4144r 4@4208r 5@4928r 6@5440r 7@5952r 8@6464r 9@6976r 10@7488r 11@8000r 12@8512r 13@8736r 14@8752r 15@8768r
		merge %vreg250:13@8736r into %vreg160:0@3888r --> @3888r
		pruned %vreg160 at 3952r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 4016r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 4080r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 4144r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 4208r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 4928r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 5440r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 5952r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 6464r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 6976r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 7488r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 8000r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned %vreg160 at 8512r: %vreg160 [3888r,3952r:0)  0@3888r
		pruned all of %vreg250 at 8736r: %vreg250 [3952r,4016r:0)[4016r,4080r:1)[4080r,4144r:2)[4144r,4208r:3)[4208r,4928r:4)[4928r,5440r:5)[5440r,5952r:6)[5952r,6464r:7)[6464r,6976r:8)[6976r,7488r:9)[7488r,8000r:10)[8000r,8512r:11)[8512r,8736r:12)[8752r,8768r:14)[8768r,9248r:15)  0@3952r 1@4016r 2@4080r 3@4144r 4@4208r 5@4928r 6@5440r 7@5952r 8@6464r 9@6976r 10@7488r 11@8000r 12@8512r 13@8736r 14@8752r 15@8768r
		erased:	8736r	%vreg250:sub13<def> = COPY %vreg160; VReg_512:%vreg250 VGPR_32:%vreg160
		restoring liveness to 15 points: %vreg250 [3888r,3952r:0)[3952r,4016r:1)[4016r,4080r:2)[4080r,4144r:3)[4144r,4208r:4)[4208r,4928r:5)[4928r,5440r:6)[5440r,5952r:7)[5952r,6464r:8)[6464r,6976r:9)[6976r,7488r:10)[7488r,8000r:11)[8000r,8512r:12)[8512r,8736r:13)[8752r,8768r:14)[8768r,9248r:15)  0@3888r 1@3952r 2@4016r 3@4080r 4@4144r 5@4208r 6@4928r 7@5440r 8@5952r 9@6464r 10@6976r 11@7488r 12@8000r 13@8512r 14@8752r 15@8768r
		updated: 3888B	%vreg250:sub13<def,read-undef> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
	Joined. Result = %vreg250 [3888r,3952r:0)[3952r,4016r:1)[4016r,4080r:2)[4080r,4144r:3)[4144r,4208r:4)[4208r,4928r:5)[4928r,5440r:6)[5440r,5952r:7)[5952r,6464r:8)[6464r,6976r:9)[6976r,7488r:10)[7488r,8000r:11)[8000r,8512r:12)[8512r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@3888r 1@3952r 2@4016r 3@4080r 4@4144r 5@4208r 6@4928r 7@5440r 8@5952r 9@6464r 10@6976r 11@7488r 12@8000r 13@8512r 14@8752r 15@8768r
8752B	%vreg250:sub14<def> = COPY %vreg156; VReg_512:%vreg250 VGPR_32:%vreg156
	Considering merging to VReg_512 with %vreg156 in %vreg250:sub14
		RHS = %vreg156 [3824r,8752r:0)  0@3824r
		LHS = %vreg250 [3888r,3952r:0)[3952r,4016r:1)[4016r,4080r:2)[4080r,4144r:3)[4144r,4208r:4)[4208r,4928r:5)[4928r,5440r:6)[5440r,5952r:7)[5952r,6464r:8)[6464r,6976r:9)[6976r,7488r:10)[7488r,8000r:11)[8000r,8512r:12)[8512r,8752r:13)[8752r,8768r:14)[8768r,9248r:15)  0@3888r 1@3952r 2@4016r 3@4080r 4@4144r 5@4208r 6@4928r 7@5440r 8@5952r 9@6464r 10@6976r 11@7488r 12@8000r 13@8512r 14@8752r 15@8768r
		merge %vreg250:14@8752r into %vreg156:0@3824r --> @3824r
		pruned %vreg156 at 3888r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 3952r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 4016r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 4080r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 4144r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 4208r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 4928r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 5440r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 5952r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 6464r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 6976r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 7488r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 8000r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned %vreg156 at 8512r: %vreg156 [3824r,3888r:0)  0@3824r
		pruned all of %vreg250 at 8752r: %vreg250 [3888r,3952r:0)[3952r,4016r:1)[4016r,4080r:2)[4080r,4144r:3)[4144r,4208r:4)[4208r,4928r:5)[4928r,5440r:6)[5440r,5952r:7)[5952r,6464r:8)[6464r,6976r:9)[6976r,7488r:10)[7488r,8000r:11)[8000r,8512r:12)[8512r,8752r:13)[8768r,9248r:15)  0@3888r 1@3952r 2@4016r 3@4080r 4@4144r 5@4208r 6@4928r 7@5440r 8@5952r 9@6464r 10@6976r 11@7488r 12@8000r 13@8512r 14@8752r 15@8768r
		erased:	8752r	%vreg250:sub14<def> = COPY %vreg156; VReg_512:%vreg250 VGPR_32:%vreg156
		restoring liveness to 16 points: %vreg250 [3824r,3888r:0)[3888r,3952r:1)[3952r,4016r:2)[4016r,4080r:3)[4080r,4144r:4)[4144r,4208r:5)[4208r,4928r:6)[4928r,5440r:7)[5440r,5952r:8)[5952r,6464r:9)[6464r,6976r:10)[6976r,7488r:11)[7488r,8000r:12)[8000r,8512r:13)[8512r,8752r:14)[8768r,9248r:15)  0@3824r 1@3888r 2@3952r 3@4016r 4@4080r 5@4144r 6@4208r 7@4928r 8@5440r 9@5952r 10@6464r 11@6976r 12@7488r 13@8000r 14@8512r 15@8768r
		updated: 3824B	%vreg250:sub14<def,read-undef> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
	Joined. Result = %vreg250 [3824r,3888r:0)[3888r,3952r:1)[3952r,4016r:2)[4016r,4080r:3)[4080r,4144r:4)[4144r,4208r:5)[4208r,4928r:6)[4928r,5440r:7)[5440r,5952r:8)[5952r,6464r:9)[6464r,6976r:10)[6976r,7488r:11)[7488r,8000r:12)[8000r,8512r:13)[8512r,8768r:14)[8768r,9248r:15)  0@3824r 1@3888r 2@3952r 3@4016r 4@4080r 5@4144r 6@4208r 7@4928r 8@5440r 9@5952r 10@6464r 11@6976r 12@7488r 13@8000r 14@8512r 15@8768r
8768B	%vreg250:sub15<def> = COPY %vreg152; VReg_512:%vreg250 VGPR_32:%vreg152
	Considering merging to VReg_512 with %vreg152 in %vreg250:sub15
		RHS = %vreg152 [3760r,8768r:0)  0@3760r
		LHS = %vreg250 [3824r,3888r:0)[3888r,3952r:1)[3952r,4016r:2)[4016r,4080r:3)[4080r,4144r:4)[4144r,4208r:5)[4208r,4928r:6)[4928r,5440r:7)[5440r,5952r:8)[5952r,6464r:9)[6464r,6976r:10)[6976r,7488r:11)[7488r,8000r:12)[8000r,8512r:13)[8512r,8768r:14)[8768r,9248r:15)  0@3824r 1@3888r 2@3952r 3@4016r 4@4080r 5@4144r 6@4208r 7@4928r 8@5440r 9@5952r 10@6464r 11@6976r 12@7488r 13@8000r 14@8512r 15@8768r
		merge %vreg250:15@8768r into %vreg152:0@3760r --> @3760r
		pruned %vreg152 at 3824r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 3888r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 3952r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 4016r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 4080r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 4144r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 4208r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 4928r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 5440r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 5952r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 6464r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 6976r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 7488r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 8000r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned %vreg152 at 8512r: %vreg152 [3760r,3824r:0)  0@3760r
		pruned all of %vreg250 at 8768r: %vreg250 [3824r,3888r:0)[3888r,3952r:1)[3952r,4016r:2)[4016r,4080r:3)[4080r,4144r:4)[4144r,4208r:5)[4208r,4928r:6)[4928r,5440r:7)[5440r,5952r:8)[5952r,6464r:9)[6464r,6976r:10)[6976r,7488r:11)[7488r,8000r:12)[8000r,8512r:13)[8512r,8768r:14)  0@3824r 1@3888r 2@3952r 3@4016r 4@4080r 5@4144r 6@4208r 7@4928r 8@5440r 9@5952r 10@6464r 11@6976r 12@7488r 13@8000r 14@8512r 15@8768r
		erased:	8768r	%vreg250:sub15<def> = COPY %vreg152; VReg_512:%vreg250 VGPR_32:%vreg152
		restoring liveness to 17 points: %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,8768r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		updated: 3760B	%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
8784B	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg251 in %vreg250:sub1
		RHS = %vreg251 [8784r,8816r:0)  0@8784r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg251:0@8784r into %vreg250:15@8512r --> @8512r
		erased:	8784r	%vreg251<def> = COPY %vreg250:sub1; VGPR_32:%vreg251 VReg_512:%vreg250
		updated: 8816B	%vreg253<def> = V_ADD_F32_e32 %vreg252, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VSrc_32:%vreg252 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
8800B	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg252 in %vreg250:sub0
		RHS = %vreg252 [8800r,8816r:0)  0@8800r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg252:0@8800r into %vreg250:15@8512r --> @8512r
		erased:	8800r	%vreg252<def> = COPY %vreg250:sub0; VSrc_32:%vreg252 VReg_512:%vreg250
		updated: 8816B	%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
8832B	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg254 in %vreg250:sub2
		RHS = %vreg254 [8832r,8848r:0)  0@8832r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg254:0@8832r into %vreg250:15@8512r --> @8512r
		erased:	8832r	%vreg254<def> = COPY %vreg250:sub2; VSrc_32:%vreg254 VReg_512:%vreg250
		updated: 8848B	%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
8864B	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg256 in %vreg250:sub3
		RHS = %vreg256 [8864r,8880r:0)  0@8864r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg256:0@8864r into %vreg250:15@8512r --> @8512r
		erased:	8864r	%vreg256<def> = COPY %vreg250:sub3; VSrc_32:%vreg256 VReg_512:%vreg250
		updated: 8880B	%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
8896B	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg258 in %vreg250:sub4
		RHS = %vreg258 [8896r,8912r:0)  0@8896r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg258:0@8896r into %vreg250:15@8512r --> @8512r
		erased:	8896r	%vreg258<def> = COPY %vreg250:sub4; VSrc_32:%vreg258 VReg_512:%vreg250
		updated: 8912B	%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
8928B	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg260 in %vreg250:sub5
		RHS = %vreg260 [8928r,8944r:0)  0@8928r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg260:0@8928r into %vreg250:15@8512r --> @8512r
		erased:	8928r	%vreg260<def> = COPY %vreg250:sub5; VSrc_32:%vreg260 VReg_512:%vreg250
		updated: 8944B	%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
8960B	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg262 in %vreg250:sub6
		RHS = %vreg262 [8960r,8976r:0)  0@8960r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg262:0@8960r into %vreg250:15@8512r --> @8512r
		erased:	8960r	%vreg262<def> = COPY %vreg250:sub6; VSrc_32:%vreg262 VReg_512:%vreg250
		updated: 8976B	%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
8992B	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg264 in %vreg250:sub7
		RHS = %vreg264 [8992r,9008r:0)  0@8992r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg264:0@8992r into %vreg250:15@8512r --> @8512r
		erased:	8992r	%vreg264<def> = COPY %vreg250:sub7; VSrc_32:%vreg264 VReg_512:%vreg250
		updated: 9008B	%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
9024B	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg266 in %vreg250:sub8
		RHS = %vreg266 [9024r,9040r:0)  0@9024r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg266:0@9024r into %vreg250:15@8512r --> @8512r
		erased:	9024r	%vreg266<def> = COPY %vreg250:sub8; VSrc_32:%vreg266 VReg_512:%vreg250
		updated: 9040B	%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
9056B	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg268 in %vreg250:sub9
		RHS = %vreg268 [9056r,9072r:0)  0@9056r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg268:0@9056r into %vreg250:15@8512r --> @8512r
		erased:	9056r	%vreg268<def> = COPY %vreg250:sub9; VSrc_32:%vreg268 VReg_512:%vreg250
		updated: 9072B	%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
9088B	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg270 in %vreg250:sub10
		RHS = %vreg270 [9088r,9104r:0)  0@9088r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg270:0@9088r into %vreg250:15@8512r --> @8512r
		erased:	9088r	%vreg270<def> = COPY %vreg250:sub10; VSrc_32:%vreg270 VReg_512:%vreg250
		updated: 9104B	%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
9120B	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg272 in %vreg250:sub11
		RHS = %vreg272 [9120r,9136r:0)  0@9120r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg272:0@9120r into %vreg250:15@8512r --> @8512r
		erased:	9120r	%vreg272<def> = COPY %vreg250:sub11; VSrc_32:%vreg272 VReg_512:%vreg250
		updated: 9136B	%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
9152B	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg274 in %vreg250:sub12
		RHS = %vreg274 [9152r,9168r:0)  0@9152r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg274:0@9152r into %vreg250:15@8512r --> @8512r
		erased:	9152r	%vreg274<def> = COPY %vreg250:sub12; VSrc_32:%vreg274 VReg_512:%vreg250
		updated: 9168B	%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
9184B	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg276 in %vreg250:sub13
		RHS = %vreg276 [9184r,9200r:0)  0@9184r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg276:0@9184r into %vreg250:15@8512r --> @8512r
		erased:	9184r	%vreg276<def> = COPY %vreg250:sub13; VSrc_32:%vreg276 VReg_512:%vreg250
		updated: 9200B	%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
9216B	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg278 in %vreg250:sub14
		RHS = %vreg278 [9216r,9232r:0)  0@9216r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg278:0@9216r into %vreg250:15@8512r --> @8512r
		erased:	9216r	%vreg278<def> = COPY %vreg250:sub14; VSrc_32:%vreg278 VReg_512:%vreg250
		updated: 9232B	%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
9248B	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
	Considering merging to VReg_512 with %vreg280 in %vreg250:sub15
		RHS = %vreg280 [9248r,9264r:0)  0@9248r
		LHS = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9248r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
		merge %vreg280:0@9248r into %vreg250:15@8512r --> @8512r
		erased:	9248r	%vreg280<def> = COPY %vreg250:sub15; VSrc_32:%vreg280 VReg_512:%vreg250
		updated: 9264B	%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
	Joined. Result = %vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9264r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
9296B	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
	Considering merging to SReg_64_with_sub0 with %vreg284 in %vreg283:sub0
		RHS = %vreg284 [9296r,9472r:0)  0@9296r
		LHS = %vreg283 [1968r,2096B:0)[3552B,9808B:0)  0@1968r
		merge %vreg284:0@9296r into %vreg283:0@1968r --> @1968r
		erased:	9296r	%vreg284<def> = COPY %vreg283:sub0; SReg_32:%vreg284 SReg_64_with_sub0:%vreg283
AllocationOrder(SReg_64_with_sub0) = [ %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR10_SGPR11 %SGPR12_SGPR13 %SGPR14_SGPR15 %SGPR16_SGPR17 %SGPR18_SGPR19 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %SGPR42_SGPR43 %SGPR44_SGPR45 %SGPR46_SGPR47 %SGPR48_SGPR49 %SGPR50_SGPR51 %SGPR52_SGPR53 %SGPR54_SGPR55 %SGPR56_SGPR57 %SGPR58_SGPR59 %SGPR60_SGPR61 %SGPR62_SGPR63 %SGPR64_SGPR65 %SGPR66_SGPR67 %SGPR68_SGPR69 %SGPR70_SGPR71 %SGPR72_SGPR73 %SGPR74_SGPR75 %SGPR76_SGPR77 %SGPR78_SGPR79 %SGPR80_SGPR81 %SGPR82_SGPR83 %SGPR84_SGPR85 %SGPR86_SGPR87 %SGPR88_SGPR89 %SGPR90_SGPR91 %SGPR92_SGPR93 %SGPR94_SGPR95 %SGPR96_SGPR97 %SGPR98_SGPR99 %SGPR100_SGPR101 %VCC ]
		updated: 9360B	%vreg811<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg810, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811,%vreg810 SReg_64_with_sub0:%vreg283
		updated: 9472B	%vreg820<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg819, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820,%vreg819 SReg_64_with_sub0:%vreg283
	Joined. Result = %vreg283 [1968r,2096B:0)[3552B,9808B:0)  0@1968r
9312B	%vreg810<def> = COPY %vreg687:sub0; VReg_32:%vreg810 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg810 in %vreg687:sub0
		RHS = %vreg810 [9312r,9360r:0)  0@9312r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9344r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg810:0@9312r into %vreg687:1@4640r --> @4640r
		erased:	9312r	%vreg810<def> = COPY %vreg687:sub0; VReg_32:%vreg810 VReg_128:%vreg687
		updated: 9360B	%vreg811<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg811 SReg_64_with_sub0:%vreg283 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9360r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
9328B	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
	Considering merging to SGPR_64 with %vreg286 in %vreg283:sub1
		RHS = %vreg286 [9328r,9488r:0)  0@9328r
		LHS = %vreg283 [1968r,2096B:0)[3552B,9808B:0)  0@1968r
		merge %vreg286:0@9328r into %vreg283:0@1968r --> @1968r
		erased:	9328r	%vreg286<def> = COPY %vreg283:sub1; SReg_32:%vreg286 SReg_64_with_sub0:%vreg283
		updated: 9376B	%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
		updated: 9488B	%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
	Joined. Result = %vreg283 [1968r,2096B:0)[3552B,9808B:0)  0@1968r
9344B	%vreg816<def> = COPY %vreg687:sub1; VReg_32:%vreg816 VReg_128:%vreg687
	Considering merging to VReg_128 with %vreg816 in %vreg687:sub1
		RHS = %vreg816 [9344r,9392r:0)  0@9344r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9360r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg816:0@9344r into %vreg687:1@4640r --> @4640r
		erased:	9344r	%vreg816<def> = COPY %vreg687:sub1; VReg_32:%vreg816 VReg_128:%vreg687
		updated: 9392B	%vreg817<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg817,%vreg818 VReg_128:%vreg687
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9392r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
9376B	%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
	Not coalescable.
9408B	%vreg812:sub0<def,read-undef> = COPY %vreg811; VReg_64:%vreg812 VReg_32:%vreg811
	Considering merging to VReg_64 with %vreg811 in %vreg812:sub0
		RHS = %vreg811 [9360r,9408r:0)  0@9360r
		LHS = %vreg812 [9408r,9424r:1)[9424r,9632r:0)  0@9424r 1@9408r
		merge %vreg812:1@9408r into %vreg811:0@9360r --> @9360r
		erased:	9408r	%vreg812:sub0<def,read-undef> = COPY %vreg811; VReg_64:%vreg812 VReg_32:%vreg811
		updated: 9360B	%vreg812:sub0<def,read-undef> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg812 SGPR_64:%vreg283 VReg_128:%vreg687
	Joined. Result = %vreg812 [9360r,9424r:0)[9424r,9632r:1)  0@9360r 1@9424r
9424B	%vreg812:sub1<def> = COPY %vreg817; VReg_64:%vreg812 VReg_32:%vreg817
	Considering merging to VReg_64 with %vreg817 in %vreg812:sub1
		RHS = %vreg817 [9392r,9424r:0)  0@9392r
		LHS = %vreg812 [9360r,9424r:0)[9424r,9632r:1)  0@9360r 1@9424r
		merge %vreg812:1@9424r into %vreg817:0@9392r --> @9392r
		pruned %vreg812 at 9392r: %vreg812 [9360r,9392r:0)[9424r,9632r:1)  0@9360r 1@9424r
		erased:	9424r	%vreg812:sub1<def> = COPY %vreg817; VReg_64:%vreg812 VReg_32:%vreg817
		restoring liveness to 2 points: %vreg812 [9360r,9392r:0)[9392r,9632r:1)  0@9360r 1@9392r
		updated: 9392B	%vreg812:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg812 VReg_128:%vreg687 VReg_32:%vreg818
	Joined. Result = %vreg812 [9360r,9392r:0)[9392r,9632r:1)  0@9360r 1@9392r
9440B	%vreg819<def> = COPY %vreg562:sub0; VReg_32:%vreg819 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg819 in %vreg562:sub0
		RHS = %vreg819 [9440r,9472r:0)  0@9440r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9456r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg819:0@9440r into %vreg562:1@4288r --> @4288r
		erased:	9440r	%vreg819<def> = COPY %vreg562:sub0; VReg_32:%vreg819 VReg_128:%vreg562
		updated: 9472B	%vreg820<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg820 SGPR_64:%vreg283 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9472r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
9456B	%vreg825<def> = COPY %vreg562:sub1; VReg_32:%vreg825 VReg_128:%vreg562
	Considering merging to VReg_128 with %vreg825 in %vreg562:sub1
		RHS = %vreg825 [9456r,9504r:0)  0@9456r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9472r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg825:0@9456r into %vreg562:1@4288r --> @4288r
		erased:	9456r	%vreg825<def> = COPY %vreg562:sub1; VReg_32:%vreg825 VReg_128:%vreg562
		updated: 9504B	%vreg826<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg826,%vreg827 VReg_128:%vreg562
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9504r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
9488B	%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
	Not coalescable.
9520B	%vreg821:sub0<def,read-undef> = COPY %vreg820; VReg_64:%vreg821 VReg_32:%vreg820
	Considering merging to VReg_64 with %vreg820 in %vreg821:sub0
		RHS = %vreg820 [9472r,9520r:0)  0@9472r
		LHS = %vreg821 [9520r,9536r:1)[9536r,9648r:0)  0@9536r 1@9520r
		merge %vreg821:1@9520r into %vreg820:0@9472r --> @9472r
		erased:	9520r	%vreg821:sub0<def,read-undef> = COPY %vreg820; VReg_64:%vreg821 VReg_32:%vreg820
		updated: 9472B	%vreg821:sub0<def,read-undef> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg821 SGPR_64:%vreg283 VReg_128:%vreg562
	Joined. Result = %vreg821 [9472r,9536r:0)[9536r,9648r:1)  0@9472r 1@9536r
9536B	%vreg821:sub1<def> = COPY %vreg826; VReg_64:%vreg821 VReg_32:%vreg826
	Considering merging to VReg_64 with %vreg826 in %vreg821:sub1
		RHS = %vreg826 [9504r,9536r:0)  0@9504r
		LHS = %vreg821 [9472r,9536r:0)[9536r,9648r:1)  0@9472r 1@9536r
		merge %vreg821:1@9536r into %vreg826:0@9504r --> @9504r
		pruned %vreg821 at 9504r: %vreg821 [9472r,9504r:0)[9536r,9648r:1)  0@9472r 1@9536r
		erased:	9536r	%vreg821:sub1<def> = COPY %vreg826; VReg_64:%vreg821 VReg_32:%vreg826
		restoring liveness to 2 points: %vreg821 [9472r,9504r:0)[9504r,9648r:1)  0@9472r 1@9504r
		updated: 9504B	%vreg821:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg821 VReg_128:%vreg562 VReg_32:%vreg827
	Joined. Result = %vreg821 [9472r,9504r:0)[9504r,9648r:1)  0@9472r 1@9504r
9552B	%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
	Not coalescable.
9616B	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
	Considering merging to SReg_64 with %vreg298 in %vreg31
		RHS = %vreg298 [9600r,9776r:0)  0@9600r
		LHS = %vreg31 [2096B,2112r:0)[9616r,9808B:0)  0@9616r
		merge %vreg31:0@9616r into %vreg298:0@9600r --> @9600r
		erased:	9616r	%vreg31<def> = COPY %vreg298; SReg_64:%vreg31,%vreg298
		updated: 9600B	%vreg31<def> = SI_IF_BREAK %vreg297, %vreg851, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg31,%vreg297,%vreg851
		updated: 9776B	SI_LOOP %vreg31, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg31
	Joined. Result = %vreg31 [2096B,2112r:0)[9600r,9808B:0)  0@9600r
9632B	%vreg815<def> = COPY %vreg812; VReg_64:%vreg815,%vreg812
	Considering merging to VReg_64 with %vreg812 in %vreg815
		RHS = %vreg815 [9632r,9712r:0)  0@9632r
		LHS = %vreg812 [9360r,9392r:0)[9392r,9632r:1)  0@9360r 1@9392r
		merge %vreg815:0@9632r into %vreg812:1@9392r --> @9392r
		erased:	9632r	%vreg815<def> = COPY %vreg812; VReg_64:%vreg815,%vreg812
		updated: 9712B	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg812; VReg_128:%vreg687 VReg_64:%vreg812
	Joined. Result = %vreg812 [9360r,9392r:0)[9392r,9712r:1)  0@9360r 1@9392r
9648B	%vreg824<def> = COPY %vreg821; VReg_64:%vreg824,%vreg821
	Considering merging to VReg_64 with %vreg821 in %vreg824
		RHS = %vreg824 [9648r,9728r:0)  0@9648r
		LHS = %vreg821 [9472r,9504r:0)[9504r,9648r:1)  0@9472r 1@9504r
		merge %vreg824:0@9648r into %vreg821:1@9504r --> @9504r
		erased:	9648r	%vreg824<def> = COPY %vreg821; VReg_64:%vreg824,%vreg821
		updated: 9728B	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg821; VReg_128:%vreg562 VReg_64:%vreg821
	Joined. Result = %vreg821 [9472r,9504r:0)[9504r,9728r:1)  0@9472r 1@9504r
9664B	%vreg27<def> = COPY %vreg282; VGPR_32:%vreg27,%vreg282
	Considering merging to VGPR_32 with %vreg282 in %vreg27
		RHS = %vreg282 [9280r,9664r:0)  0@9280r
		LHS = %vreg27 [2096B,2176r:0)[9664r,9808B:0)  0@9664r
		merge %vreg27:0@9664r into %vreg282:0@9280r --> @9280r
		erased:	9664r	%vreg27<def> = COPY %vreg282; VGPR_32:%vreg27,%vreg282
		updated: 9280B	%vreg27<def> = V_ADD_F32_e32 %vreg855, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg27,%vreg855,%vreg281
	Joined. Result = %vreg27 [2096B,2176r:0)[9280r,9808B:0)  0@9280r
9680B	%vreg544<def> = COPY %vreg545; VReg_32:%vreg544,%vreg545
	Considering merging to VReg_32 with %vreg545 in %vreg544
		RHS = %vreg545 [9568r,9680r:0)  0@9568r
		LHS = %vreg544 [9680r,9744r:0)  0@9680r
		merge %vreg544:0@9680r into %vreg545:0@9568r --> @9568r
		erased:	9680r	%vreg544<def> = COPY %vreg545; VReg_32:%vreg544,%vreg545
		updated: 9568B	%vreg544<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg544,%vreg854
		updated: 9584B	%vreg297<def> = V_CMP_GE_I32_e64 %vreg544, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg544 VGPR_32:%vreg296
	Joined. Result = %vreg544 [9568r,9744r:0)  0@9568r
9696B	%vreg851<def> = COPY %vreg31; SReg_64:%vreg851,%vreg31
	Considering merging to SReg_64 with %vreg31 in %vreg851
		RHS = %vreg31 [2096B,2112r:0)[9600r,9808B:0)  0@9600r
		LHS = %vreg851 [2000r,2096B:0)[3552B,9600r:2)[9696r,9808B:1)  0@2000r 1@9696r 2@3552B-phi
		merge %vreg851:1@9696r into %vreg31:0@9600r --> @9600r
		erased:	9696r	%vreg851<def> = COPY %vreg31; SReg_64:%vreg851,%vreg31
		updated: 9600B	%vreg851<def> = SI_IF_BREAK %vreg297, %vreg851, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg851,%vreg297
		updated: 2112B	SI_END_CF %vreg851, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg851
		updated: 9776B	SI_LOOP %vreg851, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg851
	Joined. Result = %vreg851 [2000r,2096B:0)[2096B,2112r:2)[3552B,9600r:1)[9600r,9808B:2)  0@2000r 1@3552B-phi 2@9600r
9712B	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg812; VReg_128:%vreg687 VReg_64:%vreg812
	Considering merging to VReg_128 with %vreg812 in %vreg687:sub0_sub1
		RHS = %vreg812 [9360r,9392r:0)[9392r,9712r:1)  0@9360r 1@9392r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9392r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		merge %vreg687:3@9712r into %vreg812:1@9392r --> @9392r
		conflict at %vreg812:0@9360r
		taints local %vreg687:1@4640r to 9392r
		pruned %vreg687 at 9360r: %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9360r:1)[9712r,9808B:3)  0@3552B-phi 1@4640r 2@2016r 3@9712r
		erased:	9712r	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg812; VReg_128:%vreg687 VReg_64:%vreg812
		restoring liveness to 2 points: %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9360r:1)[9360r,9392r:3)[9392r,9808B:4)  0@3552B-phi 1@4640r 2@2016r 3@9360r 4@9392r
		updated: 9392B	%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
		updated: 9360B	%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
	Joined. Result = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9360r:1)[9360r,9392r:3)[9392r,9808B:4)  0@3552B-phi 1@4640r 2@2016r 3@9360r 4@9392r
9728B	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg821; VReg_128:%vreg562 VReg_64:%vreg821
	Considering merging to VReg_128 with %vreg821 in %vreg562:sub0_sub1
		RHS = %vreg821 [9472r,9504r:0)[9504r,9728r:1)  0@9472r 1@9504r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9504r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		merge %vreg562:3@9728r into %vreg821:1@9504r --> @9504r
		conflict at %vreg821:0@9472r
		taints local %vreg562:1@4288r to 9504r
		pruned %vreg562 at 9472r: %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9472r:1)[9728r,9808B:3)  0@3552B-phi 1@4288r 2@2032r 3@9728r
		erased:	9728r	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg821; VReg_128:%vreg562 VReg_64:%vreg821
		restoring liveness to 2 points: %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9472r:1)[9472r,9504r:3)[9504r,9808B:4)  0@3552B-phi 1@4288r 2@2032r 3@9472r 4@9504r
		updated: 9504B	%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
		updated: 9472B	%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
	Joined. Result = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9472r:1)[9472r,9504r:3)[9504r,9808B:4)  0@3552B-phi 1@4288r 2@2032r 3@9472r 4@9504r
9744B	%vreg854<def> = COPY %vreg544; VReg_32:%vreg854,%vreg544
	Considering merging to VReg_32 with %vreg544 in %vreg854
		RHS = %vreg544 [9568r,9744r:0)  0@9568r
		LHS = %vreg854 [2048r,2096B:0)[3552B,9568r:2)[9744r,9808B:1)  0@2048r 1@9744r 2@3552B-phi
		merge %vreg854:1@9744r into %vreg544:0@9568r --> @9568r
		erased:	9744r	%vreg854<def> = COPY %vreg544; VReg_32:%vreg854,%vreg544
		updated: 9568B	%vreg854<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
		updated: 9584B	%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
	Joined. Result = %vreg854 [2048r,2096B:0)[3552B,9568r:1)[9568r,9808B:2)  0@2048r 1@3552B-phi 2@9568r
9760B	%vreg855<def> = COPY %vreg27; VGPR_32:%vreg855,%vreg27
	Considering merging to VGPR_32 with %vreg27 in %vreg855
		RHS = %vreg27 [2096B,2176r:0)[9280r,9808B:0)  0@9280r
		LHS = %vreg855 [2064r,2096B:0)[3552B,9280r:2)[9760r,9808B:1)  0@2064r 1@9760r 2@3552B-phi
		merge %vreg855:1@9760r into %vreg27:0@9280r --> @9280r
		erased:	9760r	%vreg855<def> = COPY %vreg27; VGPR_32:%vreg855,%vreg27
		updated: 9280B	%vreg855<def> = V_ADD_F32_e32 %vreg855, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg855,%vreg281
		updated: 2176B	%vreg849<def> = COPY %vreg855; VGPR_32:%vreg849,%vreg855
	Joined. Result = %vreg855 [2064r,2096B:0)[2096B,2176r:2)[3552B,9280r:1)[9280r,9808B:2)  0@2064r 1@3552B-phi 2@9280r
for.body31:
9888B	%vreg37<def> = COPY %vreg861; VGPR_32:%vreg37,%vreg861
	Considering merging to VGPR_32 with %vreg861 in %vreg37
		RHS = %vreg37 [9888r,10336r:0)  0@9888r
		LHS = %vreg861 [3376r,3408B:0)[9872B,9888r:2)[10544r,10592B:1)  0@3376r 1@10544r 2@9872B-phi
		merge %vreg37:0@9888r into %vreg861:2@9872B --> @9872B
		erased:	9888r	%vreg37<def> = COPY %vreg861; VGPR_32:%vreg37,%vreg861
		updated: 10336B	%vreg370<def> = V_MAD_F32 %vreg369, %vreg369, %vreg861, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg370,%vreg369,%vreg369,%vreg861
	Joined. Result = %vreg861 [3376r,3408B:0)[9872B,10336r:2)[10544r,10592B:1)  0@3376r 1@10544r 2@9872B-phi
9904B	%vreg455<def> = COPY %vreg860; VReg_32:%vreg455,%vreg860
	Considering merging to VReg_32 with %vreg860 in %vreg455
		RHS = %vreg455 [9904r,10352r:0)  0@9904r
		LHS = %vreg860 [3360r,3408B:0)[9872B,9904r:2)[10528r,10592B:1)  0@3360r 1@10528r 2@9872B-phi
		merge %vreg455:0@9904r into %vreg860:2@9872B --> @9872B
		erased:	9904r	%vreg455<def> = COPY %vreg860; VReg_32:%vreg455,%vreg860
		updated: 10352B	%vreg458<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg458,%vreg860
	Joined. Result = %vreg860 [3360r,3408B:0)[9872B,10352r:2)[10528r,10592B:1)  0@3360r 1@10528r 2@9872B-phi
9920B	%vreg35<def> = COPY %vreg859; VReg_64:%vreg35,%vreg859
	Considering merging to VReg_64 with %vreg859 in %vreg35
		RHS = %vreg35 [9920r,10288r:0)  0@9920r
		LHS = %vreg859 [3344r,3408B:0)[9872B,9920r:2)[10512r,10592B:1)  0@3344r 1@10512r 2@9872B-phi
		merge %vreg35:0@9920r into %vreg859:2@9872B --> @9872B
		erased:	9920r	%vreg35<def> = COPY %vreg859; VReg_64:%vreg35,%vreg859
		updated: 10112B	%vreg837<def> = COPY %vreg859:sub0; VReg_32:%vreg837 VReg_64:%vreg859
		updated: 10128B	%vreg843<def> = COPY %vreg859:sub1; VReg_32:%vreg843 VReg_64:%vreg859
		updated: 10288B	%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
	Joined. Result = %vreg859 [3344r,3408B:0)[9872B,10288r:2)[10512r,10592B:1)  0@3344r 1@10512r 2@9872B-phi
9936B	%vreg34<def> = COPY %vreg858; VReg_64:%vreg34,%vreg858
	Considering merging to VReg_64 with %vreg858 in %vreg34
		RHS = %vreg34 [9936r,10304r:0)  0@9936r
		LHS = %vreg858 [3328r,3408B:0)[9872B,9936r:2)[10496r,10592B:1)  0@3328r 1@10496r 2@9872B-phi
		merge %vreg34:0@9936r into %vreg858:2@9872B --> @9872B
		erased:	9936r	%vreg34<def> = COPY %vreg858; VReg_64:%vreg34,%vreg858
		updated: 9984B	%vreg828<def> = COPY %vreg858:sub0; VReg_32:%vreg828 VReg_64:%vreg858
		updated: 10016B	%vreg834<def> = COPY %vreg858:sub1; VReg_32:%vreg834 VReg_64:%vreg858
		updated: 10304B	%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
	Joined. Result = %vreg858 [3328r,3408B:0)[9872B,10304r:2)[10496r,10592B:1)  0@3328r 1@10496r 2@9872B-phi
9952B	%vreg33<def> = COPY %vreg857; SReg_64:%vreg33,%vreg857
	Considering merging to SReg_64 with %vreg857 in %vreg33
		RHS = %vreg33 [9952r,10384r:0)  0@9952r
		LHS = %vreg857 [3312r,3408B:0)[9872B,9952r:2)[10480r,10592B:1)  0@3312r 1@10480r 2@9872B-phi
		merge %vreg33:0@9952r into %vreg857:2@9872B --> @9872B
		erased:	9952r	%vreg33<def> = COPY %vreg857; SReg_64:%vreg33,%vreg857
		updated: 10384B	%vreg372<def> = SI_IF_BREAK %vreg371, %vreg857, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg372,%vreg371,%vreg857
	Joined. Result = %vreg857 [3312r,3408B:0)[9872B,10384r:2)[10480r,10592B:1)  0@3312r 1@10480r 2@9872B-phi
9968B	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
	Considering merging to SReg_64_with_sub0 with %vreg354 in %vreg353:sub0
		RHS = %vreg354 [9968r,10144r:0)  0@9968r
		LHS = %vreg353 [3248r,3408B:0)[9872B,10592B:0)  0@3248r
		merge %vreg354:0@9968r into %vreg353:0@3248r --> @3248r
		erased:	9968r	%vreg354<def> = COPY %vreg353:sub0; SReg_32:%vreg354 SReg_64_with_sub0:%vreg353
		updated: 10032B	%vreg829<def> = V_ADD_I32_e32 %vreg353:sub0, %vreg828, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829,%vreg828 SReg_64_with_sub0:%vreg353
		updated: 10144B	%vreg838<def> = V_ADD_I32_e32 %vreg353:sub0, %vreg837, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838,%vreg837 SReg_64_with_sub0:%vreg353
	Joined. Result = %vreg353 [3248r,3408B:0)[9872B,10592B:0)  0@3248r
9984B	%vreg828<def> = COPY %vreg858:sub0; VReg_32:%vreg828 VReg_64:%vreg858
	Considering merging to VReg_64 with %vreg828 in %vreg858:sub0
		RHS = %vreg828 [9984r,10032r:0)  0@9984r
		LHS = %vreg858 [3328r,3408B:0)[9872B,10304r:2)[10496r,10592B:1)  0@3328r 1@10496r 2@9872B-phi
		merge %vreg828:0@9984r into %vreg858:2@9872B --> @9872B
		erased:	9984r	%vreg828<def> = COPY %vreg858:sub0; VReg_32:%vreg828 VReg_64:%vreg858
		updated: 10032B	%vreg829<def> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg829 SReg_64_with_sub0:%vreg353 VReg_64:%vreg858
	Joined. Result = %vreg858 [3328r,3408B:0)[9872B,10304r:2)[10496r,10592B:1)  0@3328r 1@10496r 2@9872B-phi
10000B	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
	Considering merging to SGPR_64 with %vreg356 in %vreg353:sub1
		RHS = %vreg356 [10000r,10160r:0)  0@10000r
		LHS = %vreg353 [3248r,3408B:0)[9872B,10592B:0)  0@3248r
		merge %vreg356:0@10000r into %vreg353:0@3248r --> @3248r
		erased:	10000r	%vreg356<def> = COPY %vreg353:sub1; SReg_32:%vreg356 SReg_64_with_sub0:%vreg353
		updated: 10048B	%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
		updated: 10160B	%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
	Joined. Result = %vreg353 [3248r,3408B:0)[9872B,10592B:0)  0@3248r
10016B	%vreg834<def> = COPY %vreg858:sub1; VReg_32:%vreg834 VReg_64:%vreg858
	Considering merging to VReg_64 with %vreg834 in %vreg858:sub1
		RHS = %vreg834 [10016r,10064r:0)  0@10016r
		LHS = %vreg858 [3328r,3408B:0)[9872B,10304r:2)[10496r,10592B:1)  0@3328r 1@10496r 2@9872B-phi
		merge %vreg834:0@10016r into %vreg858:2@9872B --> @9872B
		erased:	10016r	%vreg834<def> = COPY %vreg858:sub1; VReg_32:%vreg834 VReg_64:%vreg858
		updated: 10064B	%vreg835<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg835,%vreg836 VReg_64:%vreg858
	Joined. Result = %vreg858 [3328r,3408B:0)[9872B,10304r:2)[10496r,10592B:1)  0@3328r 1@10496r 2@9872B-phi
10048B	%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
	Not coalescable.
10080B	%vreg830:sub0<def,read-undef> = COPY %vreg829; VReg_64:%vreg830 VReg_32:%vreg829
	Considering merging to VReg_64 with %vreg829 in %vreg830:sub0
		RHS = %vreg829 [10032r,10080r:0)  0@10032r
		LHS = %vreg830 [10080r,10096r:1)[10096r,10416r:0)  0@10096r 1@10080r
		merge %vreg830:1@10080r into %vreg829:0@10032r --> @10032r
		erased:	10080r	%vreg830:sub0<def,read-undef> = COPY %vreg829; VReg_64:%vreg830 VReg_32:%vreg829
		updated: 10032B	%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
	Joined. Result = %vreg830 [10032r,10096r:0)[10096r,10416r:1)  0@10032r 1@10096r
10096B	%vreg830:sub1<def> = COPY %vreg835; VReg_64:%vreg830 VReg_32:%vreg835
	Considering merging to VReg_64 with %vreg835 in %vreg830:sub1
		RHS = %vreg835 [10064r,10096r:0)  0@10064r
		LHS = %vreg830 [10032r,10096r:0)[10096r,10416r:1)  0@10032r 1@10096r
		merge %vreg830:1@10096r into %vreg835:0@10064r --> @10064r
		pruned %vreg830 at 10064r: %vreg830 [10032r,10064r:0)[10096r,10416r:1)  0@10032r 1@10096r
		erased:	10096r	%vreg830:sub1<def> = COPY %vreg835; VReg_64:%vreg830 VReg_32:%vreg835
		restoring liveness to 2 points: %vreg830 [10032r,10064r:0)[10064r,10416r:1)  0@10032r 1@10064r
		updated: 10064B	%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
	Joined. Result = %vreg830 [10032r,10064r:0)[10064r,10416r:1)  0@10032r 1@10064r
10112B	%vreg837<def> = COPY %vreg859:sub0; VReg_32:%vreg837 VReg_64:%vreg859
	Considering merging to VReg_64 with %vreg837 in %vreg859:sub0
		RHS = %vreg837 [10112r,10144r:0)  0@10112r
		LHS = %vreg859 [3344r,3408B:0)[9872B,10288r:2)[10512r,10592B:1)  0@3344r 1@10512r 2@9872B-phi
		merge %vreg837:0@10112r into %vreg859:2@9872B --> @9872B
		erased:	10112r	%vreg837<def> = COPY %vreg859:sub0; VReg_32:%vreg837 VReg_64:%vreg859
		updated: 10144B	%vreg838<def> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg838 SGPR_64:%vreg353 VReg_64:%vreg859
	Joined. Result = %vreg859 [3344r,3408B:0)[9872B,10288r:2)[10512r,10592B:1)  0@3344r 1@10512r 2@9872B-phi
10128B	%vreg843<def> = COPY %vreg859:sub1; VReg_32:%vreg843 VReg_64:%vreg859
	Considering merging to VReg_64 with %vreg843 in %vreg859:sub1
		RHS = %vreg843 [10128r,10176r:0)  0@10128r
		LHS = %vreg859 [3344r,3408B:0)[9872B,10288r:2)[10512r,10592B:1)  0@3344r 1@10512r 2@9872B-phi
		merge %vreg843:0@10128r into %vreg859:2@9872B --> @9872B
		erased:	10128r	%vreg843<def> = COPY %vreg859:sub1; VReg_32:%vreg843 VReg_64:%vreg859
		updated: 10176B	%vreg844<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg844,%vreg845 VReg_64:%vreg859
	Joined. Result = %vreg859 [3344r,3408B:0)[9872B,10288r:2)[10512r,10592B:1)  0@3344r 1@10512r 2@9872B-phi
10160B	%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
	Not coalescable.
10192B	%vreg839:sub0<def,read-undef> = COPY %vreg838; VReg_64:%vreg839 VReg_32:%vreg838
	Considering merging to VReg_64 with %vreg838 in %vreg839:sub0
		RHS = %vreg838 [10144r,10192r:0)  0@10144r
		LHS = %vreg839 [10192r,10208r:1)[10208r,10432r:0)  0@10208r 1@10192r
		merge %vreg839:1@10192r into %vreg838:0@10144r --> @10144r
		erased:	10192r	%vreg839:sub0<def,read-undef> = COPY %vreg838; VReg_64:%vreg839 VReg_32:%vreg838
		updated: 10144B	%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
	Joined. Result = %vreg839 [10144r,10208r:0)[10208r,10432r:1)  0@10144r 1@10208r
10208B	%vreg839:sub1<def> = COPY %vreg844; VReg_64:%vreg839 VReg_32:%vreg844
	Considering merging to VReg_64 with %vreg844 in %vreg839:sub1
		RHS = %vreg844 [10176r,10208r:0)  0@10176r
		LHS = %vreg839 [10144r,10208r:0)[10208r,10432r:1)  0@10144r 1@10208r
		merge %vreg839:1@10208r into %vreg844:0@10176r --> @10176r
		pruned %vreg839 at 10176r: %vreg839 [10144r,10176r:0)[10208r,10432r:1)  0@10144r 1@10208r
		erased:	10208r	%vreg839:sub1<def> = COPY %vreg844; VReg_64:%vreg839 VReg_32:%vreg844
		restoring liveness to 2 points: %vreg839 [10144r,10176r:0)[10176r,10432r:1)  0@10144r 1@10176r
		updated: 10176B	%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
	Joined. Result = %vreg839 [10144r,10176r:0)[10176r,10432r:1)  0@10144r 1@10176r
10224B	%vreg411:sub0<def,read-undef> = COPY %vreg413; SGPR_64:%vreg411 SGPR_32:%vreg413
	Considering merging to SGPR_64 with %vreg413 in %vreg411:sub0
		RHS = %vreg413 [3264r,3408B:0)[9872B,10592B:0)  0@3264r
		LHS = %vreg411 [10224r,10240r:1)[10240r,10272r:0)  0@10240r 1@10224r
		merge %vreg411:1@10224r into %vreg413:0@3264r --> @3264r
		pruned %vreg413 at 10240r: %vreg413 [3264r,3408B:0)  0@3264r
		pruned all of %vreg411 at 10224r: %vreg411 [10240r,10272r:0)  0@10240r 1@10224r
		erased:	10224r	%vreg411:sub0<def,read-undef> = COPY %vreg413; SGPR_64:%vreg411 SGPR_32:%vreg413
		restoring liveness to 4 points: %vreg411 [3264r,3408B:0)[10240r,10272r:1)  0@3264r 1@10240r
		updated: 3264B	%vreg411:sub0<def,read-undef> = S_MOV_B32 0; SGPR_64:%vreg411
	Joined. Result = %vreg411 [3264r,3408B:0)[9872B,10240r:2)[10240r,10592B:1)  0@3264r 1@10240r 2@9872B-phi
10240B	%vreg411:sub1<def> = COPY %vreg412; SGPR_64:%vreg411 SGPR_32:%vreg412
	Considering merging to SGPR_64 with %vreg412 in %vreg411:sub1
		RHS = %vreg412 [3280r,3408B:0)[9872B,10592B:0)  0@3280r
		LHS = %vreg411 [3264r,3408B:0)[9872B,10240r:2)[10240r,10592B:1)  0@3264r 1@10240r 2@9872B-phi
		merge %vreg411:1@10240r into %vreg412:0@3280r --> @3280r
		pruned all of %vreg411 at 10240r: %vreg411 [3264r,3408B:0)[9872B,10240r:2)  0@3264r 1@10240r 2@9872B-phi
		pruned %vreg412 at 9872B: %vreg412 [3280r,3408B:0)  0@3280r
		pruned %vreg411 at 3280r: %vreg411 [3264r,3280r:0)[9872B,10240r:2)  0@3264r 1@10240r 2@9872B-phi
		erased:	10240r	%vreg411:sub1<def> = COPY %vreg412; SGPR_64:%vreg411 SGPR_32:%vreg412
		restoring liveness to 4 points: %vreg411 [3264r,3280r:0)[3280r,3408B:1)[9872B,10240r:2)  0@3264r 1@3280r 2@9872B-phi
		updated: 3280B	%vreg411:sub1<def> = S_MOV_B32 61440; SGPR_64:%vreg411
	Joined. Result = %vreg411 [3264r,3280r:0)[3280r,3408B:1)[9872B,10592B:2)  0@3264r 1@3280r 2@9872B-phi
10256B	%vreg366:sub0_sub1<def,read-undef> = COPY %vreg352; SReg_128:%vreg366 SGPR_64:%vreg352
	Considering merging to SReg_128 with %vreg352 in %vreg366:sub0_sub1
		RHS = %vreg352 [3184r,3408B:0)[9872B,10592B:0)  0@3184r
		LHS = %vreg366 [10256r,10272r:1)[10272r,10304r:0)  0@10272r 1@10256r
		merge %vreg366:1@10256r into %vreg352:0@3184r --> @3184r
		pruned %vreg352 at 10272r: %vreg352 [3184r,3408B:0)  0@3184r
		pruned all of %vreg366 at 10256r: %vreg366 [10272r,10304r:0)  0@10272r 1@10256r
		erased:	10256r	%vreg366:sub0_sub1<def,read-undef> = COPY %vreg352; SReg_128:%vreg366 SGPR_64:%vreg352
		restoring liveness to 4 points: %vreg366 [3184r,3408B:0)[10272r,10304r:1)  0@3184r 1@10272r
		updated: 3184B	%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
		updated: 3200B	%vreg303<def> = COPY %vreg366:sub0_sub1; SGPR_64:%vreg303 SReg_128:%vreg366
	Joined. Result = %vreg366 [3184r,3408B:0)[9872B,10272r:2)[10272r,10592B:1)  0@3184r 1@10272r 2@9872B-phi
10272B	%vreg366:sub2_sub3<def> = COPY %vreg411; SReg_128:%vreg366 SGPR_64:%vreg411
	Considering merging to SReg_128 with %vreg411 in %vreg366:sub2_sub3
		RHS = %vreg411 [3264r,3280r:0)[3280r,3408B:1)[9872B,10592B:2)  0@3264r 1@3280r 2@9872B-phi
		LHS = %vreg366 [3184r,3408B:0)[9872B,10272r:2)[10272r,10592B:1)  0@3184r 1@10272r 2@9872B-phi
		merge %vreg411:2@9872B into %vreg366:2@9872B --> @9872B
		merge %vreg366:1@10272r into %vreg411:2@9872B --> @9872B
		pruned %vreg366 at 3264r: %vreg366 [3184r,3264r:0)[9872B,10272r:2)[10272r,10592B:1)  0@3184r 1@10272r 2@9872B-phi
		pruned %vreg366 at 3280r: %vreg366 [3184r,3264r:0)[9872B,10272r:2)[10272r,10592B:1)  0@3184r 1@10272r 2@9872B-phi
		erased:	10272r	%vreg366:sub2_sub3<def> = COPY %vreg411; SReg_128:%vreg366 SGPR_64:%vreg411
		restoring liveness to 3 points: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
		updated: 3280B	%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
		updated: 3264B	%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
	Joined. Result = %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
10400B	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
	Considering merging to SReg_64 with %vreg372 in %vreg42
		RHS = %vreg372 [10384r,10560r:0)  0@10384r
		LHS = %vreg42 [10400r,10608r:0)  0@10400r
		merge %vreg42:0@10400r into %vreg372:0@10384r --> @10384r
		erased:	10400r	%vreg42<def> = COPY %vreg372; SReg_64:%vreg42,%vreg372
		updated: 10384B	%vreg42<def> = SI_IF_BREAK %vreg371, %vreg857, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg42,%vreg371,%vreg857
		updated: 10560B	SI_LOOP %vreg42, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg42
	Joined. Result = %vreg42 [10384r,10608r:0)  0@10384r
10416B	%vreg833<def> = COPY %vreg830; VReg_64:%vreg833,%vreg830
	Considering merging to VReg_64 with %vreg830 in %vreg833
		RHS = %vreg833 [10416r,10496r:0)  0@10416r
		LHS = %vreg830 [10032r,10064r:0)[10064r,10416r:1)  0@10032r 1@10064r
		merge %vreg833:0@10416r into %vreg830:1@10064r --> @10064r
		erased:	10416r	%vreg833<def> = COPY %vreg830; VReg_64:%vreg833,%vreg830
		updated: 10496B	%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
	Joined. Result = %vreg830 [10032r,10064r:0)[10064r,10496r:1)  0@10032r 1@10064r
10432B	%vreg842<def> = COPY %vreg839; VReg_64:%vreg842,%vreg839
	Considering merging to VReg_64 with %vreg839 in %vreg842
		RHS = %vreg842 [10432r,10512r:0)  0@10432r
		LHS = %vreg839 [10144r,10176r:0)[10176r,10432r:1)  0@10144r 1@10176r
		merge %vreg842:0@10432r into %vreg839:1@10176r --> @10176r
		erased:	10432r	%vreg842<def> = COPY %vreg839; VReg_64:%vreg842,%vreg839
		updated: 10512B	%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
	Joined. Result = %vreg839 [10144r,10176r:0)[10176r,10512r:1)  0@10144r 1@10176r
10448B	%vreg38<def> = COPY %vreg370; VGPR_32:%vreg38,%vreg370
	Considering merging to VGPR_32 with %vreg370 in %vreg38
		RHS = %vreg370 [10336r,10448r:0)  0@10336r
		LHS = %vreg38 [10448r,10624r:0)  0@10448r
		merge %vreg38:0@10448r into %vreg370:0@10336r --> @10336r
		erased:	10448r	%vreg38<def> = COPY %vreg370; VGPR_32:%vreg38,%vreg370
		updated: 10336B	%vreg38<def> = V_MAD_F32 %vreg369, %vreg369, %vreg861, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg38,%vreg369,%vreg369,%vreg861
	Joined. Result = %vreg38 [10336r,10624r:0)  0@10336r
10464B	%vreg457<def> = COPY %vreg458; VReg_32:%vreg457,%vreg458
	Considering merging to VReg_32 with %vreg458 in %vreg457
		RHS = %vreg458 [10352r,10464r:0)  0@10352r
		LHS = %vreg457 [10464r,10528r:0)  0@10464r
		merge %vreg457:0@10464r into %vreg458:0@10352r --> @10352r
		erased:	10464r	%vreg457<def> = COPY %vreg458; VReg_32:%vreg457,%vreg458
		updated: 10352B	%vreg457<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg457,%vreg860
		updated: 10368B	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg457, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg457
	Joined. Result = %vreg457 [10352r,10528r:0)  0@10352r
10480B	%vreg857<def> = COPY %vreg42; SReg_64:%vreg857,%vreg42
	Considering merging to SReg_64 with %vreg42 in %vreg857
		RHS = %vreg42 [10384r,10608r:0)  0@10384r
		LHS = %vreg857 [3312r,3408B:0)[9872B,10384r:2)[10480r,10592B:1)  0@3312r 1@10480r 2@9872B-phi
		merge %vreg857:1@10480r into %vreg42:0@10384r --> @10384r
		erased:	10480r	%vreg857<def> = COPY %vreg42; SReg_64:%vreg857,%vreg42
		updated: 10384B	%vreg857<def> = SI_IF_BREAK %vreg371, %vreg857, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg857,%vreg371
		updated: 10608B	SI_END_CF %vreg857, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg857
		updated: 10560B	SI_LOOP %vreg857, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg857
	Joined. Result = %vreg857 [3312r,3408B:0)[9872B,10384r:1)[10384r,10608r:2)  0@3312r 1@9872B-phi 2@10384r
10496B	%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
	Considering merging to VReg_64 with %vreg830 in %vreg858
		RHS = %vreg830 [10032r,10064r:0)[10064r,10496r:1)  0@10032r 1@10064r
		LHS = %vreg858 [3328r,3408B:0)[9872B,10304r:2)[10496r,10592B:1)  0@3328r 1@10496r 2@9872B-phi
		merge %vreg858:1@10496r into %vreg830:1@10064r --> @10064r
		conflict at %vreg830:0@10032r
		taints local %vreg858:2@9872B to 10304r
		tainted lanes used by: %vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
  %vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
Checking if cheap as move
	Interference!
10512B	%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
	Considering merging to VReg_64 with %vreg839 in %vreg859
		RHS = %vreg839 [10144r,10176r:0)[10176r,10512r:1)  0@10144r 1@10176r
		LHS = %vreg859 [3344r,3408B:0)[9872B,10288r:2)[10512r,10592B:1)  0@3344r 1@10512r 2@9872B-phi
		merge %vreg859:1@10512r into %vreg839:1@10176r --> @10176r
		conflict at %vreg839:0@10144r
		taints local %vreg859:2@9872B to 10288r
		tainted lanes used by: %vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
  %vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
Checking if cheap as move
	Interference!
10528B	%vreg860<def> = COPY %vreg457; VReg_32:%vreg860,%vreg457
	Considering merging to VReg_32 with %vreg457 in %vreg860
		RHS = %vreg457 [10352r,10528r:0)  0@10352r
		LHS = %vreg860 [3360r,3408B:0)[9872B,10352r:2)[10528r,10592B:1)  0@3360r 1@10528r 2@9872B-phi
		merge %vreg860:1@10528r into %vreg457:0@10352r --> @10352r
		erased:	10528r	%vreg860<def> = COPY %vreg457; VReg_32:%vreg860,%vreg457
		updated: 10352B	%vreg860<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
		updated: 10368B	%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
	Joined. Result = %vreg860 [3360r,3408B:0)[9872B,10352r:1)[10352r,10592B:2)  0@3360r 1@9872B-phi 2@10352r
10544B	%vreg861<def> = COPY %vreg38; VGPR_32:%vreg861,%vreg38
	Considering merging to VGPR_32 with %vreg38 in %vreg861
		RHS = %vreg38 [10336r,10624r:0)  0@10336r
		LHS = %vreg861 [3376r,3408B:0)[9872B,10336r:2)[10544r,10592B:1)  0@3376r 1@10544r 2@9872B-phi
		merge %vreg861:1@10544r into %vreg38:0@10336r --> @10336r
		erased:	10544r	%vreg861<def> = COPY %vreg38; VGPR_32:%vreg861,%vreg38
		updated: 10336B	%vreg861<def> = V_MAD_F32 %vreg369, %vreg369, %vreg861, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg861,%vreg369,%vreg369
		updated: 10624B	%vreg856<def> = COPY %vreg861; VGPR_32:%vreg856,%vreg861
	Joined. Result = %vreg861 [3376r,3408B:0)[9872B,10336r:1)[10336r,10624r:2)  0@3376r 1@9872B-phi 2@10336r
Flow:
11056B	%vreg395<def> = COPY %vreg393; SReg_64:%vreg395,%vreg393
	Considering merging to SReg_64 with %vreg393 in %vreg395
		RHS = %vreg393 [11008r,11056r:0)[11280B,11456B:0)  0@11008r
		LHS = %vreg395 [11056r,11072r:0)[11072r,11280B:1)[11456B,11472r:1)  0@11056r 1@11072r
		merge %vreg395:0@11056r into %vreg393:0@11008r --> @11008r
		erased:	11056r	%vreg395<def> = COPY %vreg393; SReg_64:%vreg395,%vreg393
		updated: 11008B	%vreg395<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
	Joined. Result = %vreg395 [11008r,11072r:0)[11072r,11280B:1)[11280B,11456B:0)[11456B,11472r:1)  0@11008r 1@11072r
for.cond.preheader:
512B	%vreg442<def> = COPY %vreg57; VReg_32:%vreg442,%vreg57
	Considering merging to VReg_32 with %vreg57 in %vreg442
		RHS = %vreg57 [64r,512r:0)  0@64r
		LHS = %vreg442 [512r,2224B:0)[2272B,2416r:0)[3408B,9808B:0)  0@512r
		merge %vreg442:0@512r into %vreg57:0@64r --> @64r
		erased:	512r	%vreg442<def> = COPY %vreg57; VReg_32:%vreg442,%vreg57
		updated: 64B	%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
		updated: 256B	%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
	Joined. Result = %vreg442 [64r,2224B:0)[2272B,2416r:0)[3408B,9808B:0)  0@64r
528B	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
	Considering merging to SReg_32 with %vreg58 in %vreg4
		RHS = %vreg58 [48r,528r:0)  0@48r
		LHS = %vreg4 [528r,2224B:0)[2272B,2384r:0)[3408B,9808B:0)  0@528r
		merge %vreg4:0@528r into %vreg58:0@48r --> @48r
		erased:	528r	%vreg4<def> = COPY %vreg58; SReg_32:%vreg4,%vreg58
AllocationOrder(SReg_32) = [ %SGPR0 %SGPR1 %SGPR2 %SGPR3 %SGPR4 %SGPR5 %SGPR6 %SGPR7 %SGPR8 %SGPR9 %SGPR10 %SGPR11 %SGPR12 %SGPR13 %SGPR14 %SGPR15 %SGPR16 %SGPR17 %SGPR18 %SGPR19 %SGPR20 %SGPR21 %SGPR22 %SGPR23 %SGPR24 %SGPR25 %SGPR26 %SGPR27 %SGPR28 %SGPR29 %SGPR30 %SGPR31 %SGPR32 %SGPR33 %SGPR34 %SGPR35 %SGPR36 %SGPR37 %SGPR38 %SGPR39 %SGPR40 %SGPR41 %SGPR42 %SGPR43 %SGPR44 %SGPR45 %SGPR46 %SGPR47 %SGPR48 %SGPR49 %SGPR50 %SGPR51 %SGPR52 %SGPR53 %SGPR54 %SGPR55 %SGPR56 %SGPR57 %SGPR58 %SGPR59 %SGPR60 %SGPR61 %SGPR62 %SGPR63 %SGPR64 %SGPR65 %SGPR66 %SGPR67 %SGPR68 %SGPR69 %SGPR70 %SGPR71 %SGPR72 %SGPR73 %SGPR74 %SGPR75 %SGPR76 %SGPR77 %SGPR78 %SGPR79 %SGPR80 %SGPR81 %SGPR82 %SGPR83 %SGPR84 %SGPR85 %SGPR86 %SGPR87 %SGPR88 %SGPR89 %SGPR90 %SGPR91 %SGPR92 %SGPR93 %SGPR94 %SGPR95 %SGPR96 %SGPR97 %SGPR98 %SGPR99 %SGPR100 %SGPR101 %M0 %VCC_LO ]
		updated: 48B	%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
		updated: 208B	%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
	Joined. Result = %vreg4 [48r,2224B:0)[2272B,2384r:0)[3408B,9808B:0)  0@48r
544B	%vreg445<def> = COPY %vreg59; VReg_32:%vreg445,%vreg59
	Considering merging to VReg_32 with %vreg59 in %vreg445
		RHS = %vreg59 [32r,544r:0)  0@32r
		LHS = %vreg445 [544r,2224B:0)[2272B,2848r:0)[3408B,9808B:0)  0@544r
		merge %vreg445:0@544r into %vreg59:0@32r --> @32r
		erased:	544r	%vreg445<def> = COPY %vreg59; VReg_32:%vreg445,%vreg59
		updated: 32B	%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
		updated: 144B	%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
	Joined. Result = %vreg445 [32r,2224B:0)[2272B,2848r:0)[3408B,9808B:0)  0@32r
560B	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
	Considering merging to SReg_32 with %vreg60 in %vreg0
		RHS = %vreg60 [16r,560r:0)  0@16r
		LHS = %vreg0 [560r,2224B:0)[2272B,2816r:0)[3408B,9808B:0)  0@560r
		merge %vreg0:0@560r into %vreg60:0@16r --> @16r
		erased:	560r	%vreg0<def> = COPY %vreg60; SReg_32:%vreg0,%vreg60
		updated: 16B	%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
		updated: 96B	%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
	Joined. Result = %vreg0 [16r,2224B:0)[2272B,2816r:0)[3408B,9808B:0)  0@16r
576B	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
	Considering merging to SGPR_32 with %vreg70 in %vreg5
		RHS = %vreg70 [224r,576r:0)  0@224r
		LHS = %vreg5 [576r,2224B:0)[2272B,2400r:0)[3408B,9808B:0)  0@576r
		merge %vreg5:0@576r into %vreg70:0@224r --> @224r
		erased:	576r	%vreg5<def> = COPY %vreg70; SReg_32:%vreg5 SGPR_32:%vreg70
AllocationOrder(SGPR_32) = [ %SGPR0 %SGPR1 %SGPR2 %SGPR3 %SGPR4 %SGPR5 %SGPR6 %SGPR7 %SGPR8 %SGPR9 %SGPR10 %SGPR11 %SGPR12 %SGPR13 %SGPR14 %SGPR15 %SGPR16 %SGPR17 %SGPR18 %SGPR19 %SGPR20 %SGPR21 %SGPR22 %SGPR23 %SGPR24 %SGPR25 %SGPR26 %SGPR27 %SGPR28 %SGPR29 %SGPR30 %SGPR31 %SGPR32 %SGPR33 %SGPR34 %SGPR35 %SGPR36 %SGPR37 %SGPR38 %SGPR39 %SGPR40 %SGPR41 %SGPR42 %SGPR43 %SGPR44 %SGPR45 %SGPR46 %SGPR47 %SGPR48 %SGPR49 %SGPR50 %SGPR51 %SGPR52 %SGPR53 %SGPR54 %SGPR55 %SGPR56 %SGPR57 %SGPR58 %SGPR59 %SGPR60 %SGPR61 %SGPR62 %SGPR63 %SGPR64 %SGPR65 %SGPR66 %SGPR67 %SGPR68 %SGPR69 %SGPR70 %SGPR71 %SGPR72 %SGPR73 %SGPR74 %SGPR75 %SGPR76 %SGPR77 %SGPR78 %SGPR79 %SGPR80 %SGPR81 %SGPR82 %SGPR83 %SGPR84 %SGPR85 %SGPR86 %SGPR87 %SGPR88 %SGPR89 %SGPR90 %SGPR91 %SGPR92 %SGPR93 %SGPR94 %SGPR95 %SGPR96 %SGPR97 %SGPR98 %SGPR99 %SGPR100 %SGPR101 ]
		updated: 224B	%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
		updated: 240B	%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
	Joined. Result = %vreg5 [224r,2224B:0)[2272B,2400r:0)[3408B,9808B:0)  0@224r
592B	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
	Considering merging to SGPR_32 with %vreg62 in %vreg1
		RHS = %vreg62 [112r,592r:0)  0@112r
		LHS = %vreg1 [592r,2224B:0)[2272B,2832r:0)[3408B,9808B:0)  0@592r
		merge %vreg1:0@592r into %vreg62:0@112r --> @112r
		erased:	592r	%vreg1<def> = COPY %vreg62; SReg_32:%vreg1 SGPR_32:%vreg62
		updated: 112B	%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
		updated: 128B	%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
	Joined. Result = %vreg1 [112r,2224B:0)[2272B,2832r:0)[3408B,9808B:0)  0@112r
608B	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
	Considering merging to SGPR_32 with %vreg79 in %vreg55
		RHS = %vreg79 [352r,608r:0)  0@352r
		LHS = %vreg55 [608r,2224B:0)[2272B,3168r:0)[3408B,9808B:0)  0@608r
		merge %vreg55:0@608r into %vreg79:0@352r --> @352r
		erased:	608r	%vreg55<def> = COPY %vreg79; SReg_32:%vreg55 SGPR_32:%vreg79
		updated: 352B	%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
	Joined. Result = %vreg55 [352r,2224B:0)[2272B,3168r:0)[3408B,9808B:0)  0@352r
624B	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
	Considering merging to SGPR_32 with %vreg82 in %vreg52
		RHS = %vreg82 [400r,624r:0)  0@400r
		LHS = %vreg52 [624r,2224B:0)[2272B,2864r:0)[3408B,9808B:0)  0@624r
		merge %vreg52:0@624r into %vreg82:0@400r --> @400r
		erased:	624r	%vreg52<def> = COPY %vreg82; SReg_32:%vreg52 SGPR_32:%vreg82
		updated: 400B	%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
	Joined. Result = %vreg52 [400r,2224B:0)[2272B,2864r:0)[3408B,9808B:0)  0@400r
640B	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
	Considering merging to SReg_64_with_sub0 with %vreg83 in %vreg51
		RHS = %vreg83 [416r,640r:0)  0@416r
		LHS = %vreg51 [640r,2224B:0)[2272B,3088r:0)[3408B,9808B:0)  0@640r
		merge %vreg51:0@640r into %vreg83:0@416r --> @416r
		erased:	640r	%vreg51<def> = COPY %vreg83; VSrc_64_with_sub0:%vreg51 SReg_64:%vreg83
		updated: 416B	%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
	Joined. Result = %vreg51 [416r,2224B:0)[2272B,3088r:0)[3408B,9808B:0)  0@416r
656B	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
	Considering merging to SGPR_32 with %vreg84 in %vreg50
		RHS = %vreg84 [432r,656r:0)  0@432r
		LHS = %vreg50 [656r,2224B:0)[2272B,2432r:0)[3408B,9808B:0)  0@656r
		merge %vreg50:0@656r into %vreg84:0@432r --> @432r
		erased:	656r	%vreg50<def> = COPY %vreg84; SReg_32:%vreg50 SGPR_32:%vreg84
		updated: 432B	%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
	Joined. Result = %vreg50 [432r,2224B:0)[2272B,2432r:0)[3408B,9808B:0)  0@432r
672B	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
	Considering merging to SReg_64_with_sub0 with %vreg85 in %vreg49
		RHS = %vreg85 [448r,672r:0)  0@448r
		LHS = %vreg49 [672r,2224B:0)[2272B,2736r:0)[3408B,9808B:0)  0@672r
		merge %vreg49:0@672r into %vreg85:0@448r --> @448r
		erased:	672r	%vreg49<def> = COPY %vreg85; VSrc_64_with_sub0:%vreg49 SReg_64:%vreg85
		updated: 448B	%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
	Joined. Result = %vreg49 [448r,2224B:0)[2272B,2736r:0)[3408B,9808B:0)  0@448r
736B	%vreg448<def> = COPY %vreg90; VReg_32:%vreg448,%vreg90
	Considering merging to VReg_32 with %vreg90 in %vreg448
		RHS = %vreg90 [720r,736r:0)  0@720r
		LHS = %vreg448 [736r,784r:0)  0@736r
		merge %vreg448:0@736r into %vreg90:0@720r --> @720r
		erased:	736r	%vreg448<def> = COPY %vreg90; VReg_32:%vreg448,%vreg90
		updated: 720B	%vreg448<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg448
	Joined. Result = %vreg448 [720r,784r:0)  0@720r
768B	%vreg87<def> = COPY %vreg91; VGPR_32:%vreg87,%vreg91
	Considering merging to VGPR_32 with %vreg91 in %vreg87
		RHS = %vreg91 [752r,768r:0)  0@752r
		LHS = %vreg87 [768r,800r:0)  0@768r
		merge %vreg87:0@768r into %vreg91:0@752r --> @752r
		erased:	768r	%vreg87<def> = COPY %vreg91; VGPR_32:%vreg87,%vreg91
		updated: 752B	%vreg87<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg87
	Joined. Result = %vreg87 [752r,800r:0)  0@752r
784B	%vreg450<def> = COPY %vreg448; VReg_32:%vreg450,%vreg448
	Considering merging to VReg_32 with %vreg448 in %vreg450
		RHS = %vreg448 [720r,784r:0)  0@720r
		LHS = %vreg450 [784r,816r:0)  0@784r
		merge %vreg450:0@784r into %vreg448:0@720r --> @720r
		erased:	784r	%vreg450<def> = COPY %vreg448; VReg_32:%vreg450,%vreg448
		updated: 720B	%vreg450<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg450
	Joined. Result = %vreg450 [720r,816r:0)  0@720r
800B	%vreg849<def> = COPY %vreg87; VGPR_32:%vreg849,%vreg87
	Considering merging to VGPR_32 with %vreg87 in %vreg849
		RHS = %vreg87 [752r,800r:0)  0@752r
		LHS = %vreg849 [800r,864B:0)[2176r,2224B:1)[3408B,3440r:2)  0@800r 1@2176r 2@3408B-phi
		merge %vreg849:0@800r into %vreg87:0@752r --> @752r
		erased:	800r	%vreg849<def> = COPY %vreg87; VGPR_32:%vreg849,%vreg87
		updated: 752B	%vreg849<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg849
	Joined. Result = %vreg849 [752r,864B:0)[2176r,2224B:1)[3408B,3440r:2)  0@752r 1@2176r 2@3408B-phi
816B	%vreg850<def> = COPY %vreg450; VReg_32:%vreg850,%vreg450
	Considering merging to VReg_32 with %vreg450 in %vreg850
		RHS = %vreg450 [720r,816r:0)  0@720r
		LHS = %vreg850 [816r,864B:0)[2192r,2224B:1)[3408B,3424r:2)  0@816r 1@2192r 2@3408B-phi
		merge %vreg850:0@816r into %vreg450:0@720r --> @720r
		erased:	816r	%vreg850<def> = COPY %vreg450; VReg_32:%vreg850,%vreg450
		updated: 720B	%vreg850<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg850
	Joined. Result = %vreg850 [720r,864B:0)[2192r,2224B:1)[3408B,3424r:2)  0@720r 1@2192r 2@3408B-phi
Flow48:
for.cond29.preheader:
2288B	%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
	Not coalescable.
2320B	%vreg856<def> = COPY %vreg20; VGPR_32:%vreg856,%vreg20
	Considering merging to VGPR_32 with %vreg20 in %vreg856
		RHS = %vreg20 [2272B,3376r:0)[3440r,3552B:0)  0@3440r
		LHS = %vreg856 [2320r,2368B:0)[9808B,9824r:2)[10624r,10656B:1)  0@2320r 1@10624r 2@9808B-phi
		merge %vreg856:0@2320r into %vreg20:0@3440r --> @3440r
		erased:	2320r	%vreg856<def> = COPY %vreg20; VGPR_32:%vreg856,%vreg20
		updated: 3440B	%vreg856<def> = COPY %vreg849; VGPR_32:%vreg856,%vreg849
		updated: 3376B	%vreg861<def> = COPY %vreg856; VGPR_32:%vreg861,%vreg856
	Joined. Result = %vreg856 [2272B,3376r:0)[3440r,3552B:0)[9808B,9824r:2)[10624r,10656B:1)  0@3440r 1@10624r 2@9808B-phi
Flow47:
3424B	%vreg449<def> = COPY %vreg850; VReg_32:%vreg449,%vreg850
	Considering merging to VReg_32 with %vreg850 in %vreg449
		RHS = %vreg449 [3424r,3520r:0)  0@3424r
		LHS = %vreg850 [720r,864B:0)[2192r,2224B:1)[3408B,3424r:2)  0@720r 1@2192r 2@3408B-phi
		merge %vreg449:0@3424r into %vreg850:2@3408B --> @3408B
		erased:	3424r	%vreg449<def> = COPY %vreg850; VReg_32:%vreg449,%vreg850
		updated: 3520B	%vreg453<def> = COPY %vreg850; VReg_32:%vreg453,%vreg850
	Joined. Result = %vreg850 [720r,864B:0)[2192r,2224B:1)[3408B,3520r:2)  0@720r 1@2192r 2@3408B-phi
3440B	%vreg856<def> = COPY %vreg849; VGPR_32:%vreg856,%vreg849
	Considering merging to VGPR_32 with %vreg849 in %vreg856
		RHS = %vreg849 [752r,864B:0)[2176r,2224B:1)[3408B,3440r:2)  0@752r 1@2176r 2@3408B-phi
		LHS = %vreg856 [2272B,3376r:0)[3440r,3552B:0)[9808B,9824r:2)[10624r,10656B:1)  0@3440r 1@10624r 2@9808B-phi
		merge %vreg856:0@3440r into %vreg849:2@3408B --> @3408B
		erased:	3440r	%vreg856<def> = COPY %vreg849; VGPR_32:%vreg856,%vreg849
		updated: 752B	%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
		updated: 2176B	%vreg856<def> = COPY %vreg855; VGPR_32:%vreg856,%vreg855
	Joined. Result = %vreg856 [752r,864B:3)[2176r,2224B:4)[2272B,3376r:0)[3408B,3552B:0)[9808B,9824r:2)[10624r,10656B:1)  0@3408B-phi 1@10624r 2@9808B-phi 3@752r 4@2176r
3456B	%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
	Not coalescable.
3472B	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
	Considering merging to SGPR_32 with %vreg80 in %vreg54
		RHS = %vreg80 [368r,2224B:0)[3408B,3472r:0)[3552B,9808B:0)  0@368r
		LHS = %vreg54 [2272B,3408B:0)[3472r,3552B:0)[9808B,10672r:0)  0@3472r
		merge %vreg54:0@3472r into %vreg80:0@368r --> @368r
		erased:	3472r	%vreg54<def> = COPY %vreg80; SReg_32:%vreg54 SGPR_32:%vreg80
		updated: 368B	%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
	Joined. Result = %vreg54 [368r,2224B:0)[2272B,10672r:0)  0@368r
3488B	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
	Considering merging to SReg_64_with_sub0 with %vreg81 in %vreg53
		RHS = %vreg81 [384r,2224B:0)[3408B,3488r:0)[3552B,9808B:0)  0@384r
		LHS = %vreg53 [2272B,3408B:0)[3488r,3552B:0)[9808B,10832r:0)  0@3488r
		merge %vreg53:0@3488r into %vreg81:0@384r --> @384r
		erased:	3488r	%vreg53<def> = COPY %vreg81; VSrc_64_with_sub0:%vreg53 SReg_64:%vreg81
		updated: 384B	%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
	Joined. Result = %vreg53 [384r,2224B:0)[2272B,10832r:0)  0@384r
3520B	%vreg453<def> = COPY %vreg850; VReg_32:%vreg453,%vreg850
	Considering merging to VReg_32 with %vreg850 in %vreg453
		RHS = %vreg453 [2272B,3168r:0)[3520r,3552B:0)  0@3520r
		LHS = %vreg850 [720r,864B:0)[2192r,2224B:1)[3408B,3520r:2)  0@720r 1@2192r 2@3408B-phi
		merge %vreg453:0@3520r into %vreg850:2@3408B --> @3408B
		erased:	3520r	%vreg453<def> = COPY %vreg850; VReg_32:%vreg453,%vreg850
		updated: 2304B	%vreg301<def> = V_CMP_LT_I32_e64 %vreg850, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_32:%vreg850 VGPR_32:%vreg300
		updated: 3168B	%vreg454<def> = V_SUB_I32_e32 %vreg55, %vreg850, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg454,%vreg850 SGPR_32:%vreg55
		updated: 2528B	%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg850, %EXEC<imp-use>; VReg_32:%vreg494,%vreg850
		updated: 2544B	%vreg459:sub0<def,read-undef> = COPY %vreg850; VReg_64:%vreg459 VReg_32:%vreg850
	Joined. Result = %vreg850 [720r,864B:0)[2192r,2224B:1)[2272B,3168r:2)[3408B,3552B:2)  0@720r 1@2192r 2@3408B-phi
Flow46:
9824B	%vreg32<def> = COPY %vreg856; VGPR_32:%vreg32,%vreg856
	Considering merging to VGPR_32 with %vreg856 in %vreg32
		RHS = %vreg32 [9824r,9872B:0)[10656B,10912r:0)  0@9824r
		LHS = %vreg856 [752r,864B:3)[2176r,2224B:4)[2272B,3376r:0)[3408B,3552B:0)[9808B,9824r:2)[10624r,10656B:1)  0@3408B-phi 1@10624r 2@9808B-phi 3@752r 4@2176r
		merge %vreg32:0@9824r into %vreg856:2@9808B --> @9808B
		erased:	9824r	%vreg32<def> = COPY %vreg856; VGPR_32:%vreg32,%vreg856
		updated: 10912B	%vreg388<def> = V_MUL_F32_e64 %vreg856, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
	Joined. Result = %vreg856 [752r,864B:3)[2176r,2224B:4)[2272B,3376r:0)[3408B,3552B:0)[9808B,9872B:2)[10624r,10656B:1)[10656B,10912r:2)  0@3408B-phi 1@10624r 2@9808B-phi 3@752r 4@2176r
for.end48:
10672B	%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SGPR_32:%vreg54
	Not coalescable.
10736B	%vreg425:sub0<def,read-undef> = COPY %vreg424; VReg_64:%vreg425 VReg_32:%vreg424
	Considering merging to VReg_64 with %vreg424 in %vreg425:sub0
		RHS = %vreg424 [10704r,10736r:0)  0@10704r
		LHS = %vreg425 [10736r,10752r:1)[10752r,10768r:0)  0@10752r 1@10736r
		merge %vreg425:1@10736r into %vreg424:0@10704r --> @10704r
		erased:	10736r	%vreg425:sub0<def,read-undef> = COPY %vreg424; VReg_64:%vreg425 VReg_32:%vreg424
		updated: 10704B	%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
		updated: 10720B	%vreg437<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_32:%vreg437 VReg_64:%vreg425
	Joined. Result = %vreg425 [10704r,10752r:0)[10752r,10768r:1)  0@10704r 1@10752r
10752B	%vreg425:sub1<def> = COPY %vreg437; VReg_64:%vreg425 VReg_32:%vreg437
	Considering merging to VReg_64 with %vreg437 in %vreg425:sub1
		RHS = %vreg437 [10720r,10752r:0)  0@10720r
		LHS = %vreg425 [10704r,10752r:0)[10752r,10768r:1)  0@10704r 1@10752r
		merge %vreg425:1@10752r into %vreg437:0@10720r --> @10720r
		pruned %vreg425 at 10720r: %vreg425 [10704r,10720r:0)[10752r,10768r:1)  0@10704r 1@10752r
		erased:	10752r	%vreg425:sub1<def> = COPY %vreg437; VReg_64:%vreg425 VReg_32:%vreg437
		restoring liveness to 2 points: %vreg425 [10704r,10720r:0)[10720r,10768r:1)  0@10704r 1@10720r
		updated: 10720B	%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_64:%vreg425
	Joined. Result = %vreg425 [10704r,10720r:0)[10720r,10768r:1)  0@10704r 1@10720r
10784B	%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
	Considering merging to VReg_64 with %vreg435 in %vreg428:sub0
		RHS = %vreg435 [10784r,10848r:0)  0@10784r
		LHS = %vreg428 [10768r,10800r:0)  0@10768r
		merge %vreg435:0@10784r into %vreg428:0@10768r --> @10768r
		erased:	10784r	%vreg435<def> = COPY %vreg428:sub0; VReg_32:%vreg435 VReg_64:%vreg428
		updated: 10848B	%vreg436<def> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg436,%vreg847 VReg_64:%vreg428
	Joined. Result = %vreg428 [10768r,10848r:0)  0@10768r
10800B	%vreg429<def> = COPY %vreg428:sub1; VReg_32:%vreg429 VReg_64:%vreg428
	Considering merging to VReg_64 with %vreg429 in %vreg428:sub1
		RHS = %vreg429 [10800r,10864r:0)  0@10800r
		LHS = %vreg428 [10768r,10848r:0)  0@10768r
		merge %vreg429:0@10800r into %vreg428:0@10768r --> @10768r
		erased:	10800r	%vreg429<def> = COPY %vreg428:sub1; VReg_32:%vreg429 VReg_64:%vreg428
		updated: 10864B	%vreg430<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg430,%vreg848 VReg_64:%vreg428
	Joined. Result = %vreg428 [10768r,10864r:0)  0@10768r
10816B	%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
	Not coalescable.
10832B	%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
	Not coalescable.
10880B	%vreg432:sub0<def,read-undef> = COPY %vreg436; VReg_64:%vreg432 VReg_32:%vreg436
	Considering merging to VReg_64 with %vreg436 in %vreg432:sub0
		RHS = %vreg436 [10848r,10880r:0)  0@10848r
		LHS = %vreg432 [10880r,10896r:1)[10896r,10992r:0)  0@10896r 1@10880r
		merge %vreg432:1@10880r into %vreg436:0@10848r --> @10848r
		erased:	10880r	%vreg432:sub0<def,read-undef> = COPY %vreg436; VReg_64:%vreg432 VReg_32:%vreg436
		updated: 10848B	%vreg432:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg432,%vreg428 VReg_32:%vreg847
	Joined. Result = %vreg432 [10848r,10896r:0)[10896r,10992r:1)  0@10848r 1@10896r
10896B	%vreg432:sub1<def> = COPY %vreg430; VReg_64:%vreg432 VReg_32:%vreg430
	Considering merging to VReg_64 with %vreg430 in %vreg432:sub1
		RHS = %vreg430 [10864r,10896r:0)  0@10864r
		LHS = %vreg432 [10848r,10896r:0)[10896r,10992r:1)  0@10848r 1@10896r
		merge %vreg432:1@10896r into %vreg430:0@10864r --> @10864r
		pruned %vreg432 at 10864r: %vreg432 [10848r,10864r:0)[10896r,10992r:1)  0@10848r 1@10896r
		erased:	10896r	%vreg432:sub1<def> = COPY %vreg430; VReg_64:%vreg432 VReg_32:%vreg430
		restoring liveness to 2 points: %vreg432 [10848r,10864r:0)[10864r,10992r:1)  0@10848r 1@10864r
		updated: 10864B	%vreg432:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg432,%vreg428 VReg_32:%vreg848
	Joined. Result = %vreg432 [10848r,10864r:0)[10864r,10992r:1)  0@10848r 1@10864r
10992B	%vreg45<def> = COPY %vreg432; VReg_64:%vreg45,%vreg432
	Considering merging to VReg_64 with %vreg432 in %vreg45
		RHS = %vreg432 [10848r,10864r:0)[10864r,10992r:1)  0@10848r 1@10864r
		LHS = %vreg45 [10992r,11248r:0)[11280B,11456B:0)  0@10992r
		merge %vreg45:0@10992r into %vreg432:1@10864r --> @10864r
		erased:	10992r	%vreg45<def> = COPY %vreg432; VReg_64:%vreg45,%vreg432
		updated: 10864B	%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
		updated: 10848B	%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
	Joined. Result = %vreg45 [10848r,10864r:0)[10864r,11248r:1)[11280B,11456B:1)  0@10848r 1@10864r
Flow44:
entry:
16B	%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
	Considering merging %vreg0 with %SGPR2
	Can only merge into reserved registers.
32B	%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
	Considering merging %vreg445 with %VGPR0
	Can only merge into reserved registers.
48B	%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
	Considering merging %vreg4 with %SGPR3
	Can only merge into reserved registers.
64B	%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
	Considering merging %vreg442 with %VGPR1
	Can only merge into reserved registers.
80B	%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
	Considering merging %vreg48 with %SGPR0_SGPR1
	Can only merge into reserved registers.
96B	%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
	Not coalescable.
176B	%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
	Not coalescable.
208B	%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
	Not coalescable.
288B	%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
	Not coalescable.
for.body.lr.ph:
880B	%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
	Not coalescable.
960B	%vreg104:sub0<def,read-undef> = COPY %vreg101; VReg_64:%vreg104 VReg_32:%vreg101
	Considering merging to VReg_64 with %vreg101 in %vreg104:sub0
		RHS = %vreg101 [928r,960r:0)  0@928r
		LHS = %vreg104 [960r,976r:1)[976r,992r:0)  0@976r 1@960r
		merge %vreg104:1@960r into %vreg101:0@928r --> @928r
		erased:	960r	%vreg104:sub0<def,read-undef> = COPY %vreg101; VReg_64:%vreg104 VReg_32:%vreg101
		updated: 928B	%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
		updated: 944B	%vreg497<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_32:%vreg497 VReg_64:%vreg104
	Joined. Result = %vreg104 [928r,976r:0)[976r,992r:1)  0@928r 1@976r
976B	%vreg104:sub1<def> = COPY %vreg497; VReg_64:%vreg104 VReg_32:%vreg497
	Considering merging to VReg_64 with %vreg497 in %vreg104:sub1
		RHS = %vreg497 [944r,976r:0)  0@944r
		LHS = %vreg104 [928r,976r:0)[976r,992r:1)  0@928r 1@976r
		merge %vreg104:1@976r into %vreg497:0@944r --> @944r
		pruned %vreg104 at 944r: %vreg104 [928r,944r:0)[976r,992r:1)  0@928r 1@976r
		erased:	976r	%vreg104:sub1<def> = COPY %vreg497; VReg_64:%vreg104 VReg_32:%vreg497
		restoring liveness to 2 points: %vreg104 [928r,944r:0)[944r,992r:1)  0@928r 1@944r
		updated: 944B	%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_64:%vreg104
	Joined. Result = %vreg104 [928r,944r:0)[944r,992r:1)  0@928r 1@944r
1008B	%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
	Considering merging to VReg_64 with %vreg514 in %vreg499:sub0
		RHS = %vreg514 [1008r,1072r:0)  0@1008r
		LHS = %vreg499 [992r,1024r:0)  0@992r
		merge %vreg514:0@1008r into %vreg499:0@992r --> @992r
		erased:	1008r	%vreg514<def> = COPY %vreg499:sub0; VReg_32:%vreg514 VReg_64:%vreg499
		updated: 1072B	%vreg515<def> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg515,%vreg516 VReg_64:%vreg499
	Joined. Result = %vreg499 [992r,1072r:0)  0@992r
1024B	%vreg500<def> = COPY %vreg499:sub1; VReg_32:%vreg500 VReg_64:%vreg499
	Considering merging to VReg_64 with %vreg500 in %vreg499:sub1
		RHS = %vreg500 [1024r,1088r:0)  0@1024r
		LHS = %vreg499 [992r,1072r:0)  0@992r
		merge %vreg500:0@1024r into %vreg499:0@992r --> @992r
		erased:	1024r	%vreg500<def> = COPY %vreg499:sub1; VReg_32:%vreg500 VReg_64:%vreg499
		updated: 1088B	%vreg501<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg501,%vreg517 VReg_64:%vreg499
	Joined. Result = %vreg499 [992r,1088r:0)  0@992r
1040B	%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
	Not coalescable.
1056B	%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
	Not coalescable.
1104B	%vreg503:sub0<def,read-undef> = COPY %vreg515; VReg_64:%vreg503 VReg_32:%vreg515
	Considering merging to VReg_64 with %vreg515 in %vreg503:sub0
		RHS = %vreg515 [1072r,1104r:0)  0@1072r
		LHS = %vreg503 [1104r,1120r:1)[1120r,1152r:0)  0@1120r 1@1104r
		merge %vreg503:1@1104r into %vreg515:0@1072r --> @1072r
		erased:	1104r	%vreg503:sub0<def,read-undef> = COPY %vreg515; VReg_64:%vreg503 VReg_32:%vreg515
		updated: 1072B	%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
	Joined. Result = %vreg503 [1072r,1120r:0)[1120r,1152r:1)  0@1072r 1@1120r
1120B	%vreg503:sub1<def> = COPY %vreg501; VReg_64:%vreg503 VReg_32:%vreg501
	Considering merging to VReg_64 with %vreg501 in %vreg503:sub1
		RHS = %vreg501 [1088r,1120r:0)  0@1088r
		LHS = %vreg503 [1072r,1120r:0)[1120r,1152r:1)  0@1072r 1@1120r
		merge %vreg503:1@1120r into %vreg501:0@1088r --> @1088r
		pruned %vreg503 at 1088r: %vreg503 [1072r,1088r:0)[1120r,1152r:1)  0@1072r 1@1120r
		erased:	1120r	%vreg503:sub1<def> = COPY %vreg501; VReg_64:%vreg503 VReg_32:%vreg501
		restoring liveness to 2 points: %vreg503 [1072r,1088r:0)[1088r,1152r:1)  0@1072r 1@1088r
		updated: 1088B	%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
	Joined. Result = %vreg503 [1072r,1088r:0)[1088r,1152r:1)  0@1072r 1@1088r
1136B	%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
	Considering merging to VReg_64 with %vreg512 in %vreg503:sub0
		RHS = %vreg512 [1136r,1216r:0)  0@1136r
		LHS = %vreg503 [1072r,1088r:0)[1088r,1152r:1)  0@1072r 1@1088r
		merge %vreg512:0@1136r into %vreg503:1@1088r --> @1088r
		erased:	1136r	%vreg512<def> = COPY %vreg503:sub0; VReg_32:%vreg512 VReg_64:%vreg503
		updated: 1216B	%vreg513<def> = V_ADD_I32_e32 %vreg117, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513 SReg_32:%vreg117 VReg_64:%vreg503
	Joined. Result = %vreg503 [1072r,1088r:0)[1088r,1216r:1)  0@1072r 1@1088r
1152B	%vreg506<def> = COPY %vreg503:sub1; VReg_32:%vreg506 VReg_64:%vreg503
	Considering merging to VReg_64 with %vreg506 in %vreg503:sub1
		RHS = %vreg506 [1152r,1248r:0)  0@1152r
		LHS = %vreg503 [1072r,1088r:0)[1088r,1216r:1)  0@1072r 1@1088r
		merge %vreg506:0@1152r into %vreg503:1@1088r --> @1088r
		erased:	1152r	%vreg506<def> = COPY %vreg503:sub1; VReg_32:%vreg506 VReg_64:%vreg503
		updated: 1248B	%vreg507<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg507,%vreg508 VReg_64:%vreg503
	Joined. Result = %vreg503 [1072r,1088r:0)[1088r,1248r:1)  0@1072r 1@1088r
1184B	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
	Considering merging to SReg_64_with_sub0 with %vreg117 in %vreg116:sub0
		RHS = %vreg117 [1184r,1584r:0)  0@1184r
		LHS = %vreg116 [1168r,1200r:0)  0@1168r
		merge %vreg117:0@1184r into %vreg116:0@1168r --> @1168r
		erased:	1184r	%vreg117<def> = COPY %vreg116:sub0; SReg_32:%vreg117 SReg_64_with_sub0:%vreg116
		updated: 1216B	%vreg513<def> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg513 SReg_64_with_sub0:%vreg116 VReg_64:%vreg503
		updated: 1584B	%vreg536<def> = V_ADD_I32_e32 %vreg116:sub0, %vreg535, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536,%vreg535 SReg_64_with_sub0:%vreg116
	Joined. Result = %vreg116 [1168r,1584r:0)  0@1168r
1200B	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
	Considering merging to SGPR_64 with %vreg118 in %vreg116:sub1
		RHS = %vreg118 [1200r,1600r:0)  0@1200r
		LHS = %vreg116 [1168r,1584r:0)  0@1168r
		merge %vreg118:0@1200r into %vreg116:0@1168r --> @1168r
		erased:	1200r	%vreg118<def> = COPY %vreg116:sub1; SReg_32:%vreg118 SReg_64_with_sub0:%vreg116
		updated: 1232B	%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
		updated: 1600B	%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
	Joined. Result = %vreg116 [1168r,1600r:0)  0@1168r
1232B	%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
	Not coalescable.
1264B	%vreg509:sub0<def,read-undef> = COPY %vreg513; VReg_64:%vreg509 VReg_32:%vreg513
	Considering merging to VReg_64 with %vreg513 in %vreg509:sub0
		RHS = %vreg513 [1216r,1264r:0)  0@1216r
		LHS = %vreg509 [1264r,1280r:1)[1280r,1760r:0)  0@1280r 1@1264r
		merge %vreg509:1@1264r into %vreg513:0@1216r --> @1216r
		erased:	1264r	%vreg509:sub0<def,read-undef> = COPY %vreg513; VReg_64:%vreg509 VReg_32:%vreg513
		updated: 1216B	%vreg509:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg509,%vreg503 SGPR_64:%vreg116
	Joined. Result = %vreg509 [1216r,1280r:0)[1280r,1760r:1)  0@1216r 1@1280r
1280B	%vreg509:sub1<def> = COPY %vreg507; VReg_64:%vreg509 VReg_32:%vreg507
	Considering merging to VReg_64 with %vreg507 in %vreg509:sub1
		RHS = %vreg507 [1248r,1280r:0)  0@1248r
		LHS = %vreg509 [1216r,1280r:0)[1280r,1760r:1)  0@1216r 1@1280r
		merge %vreg509:1@1280r into %vreg507:0@1248r --> @1248r
		pruned %vreg509 at 1248r: %vreg509 [1216r,1248r:0)[1280r,1760r:1)  0@1216r 1@1280r
		erased:	1280r	%vreg509:sub1<def> = COPY %vreg507; VReg_64:%vreg509 VReg_32:%vreg507
		restoring liveness to 2 points: %vreg509 [1216r,1248r:0)[1248r,1760r:1)  0@1216r 1@1248r
		updated: 1248B	%vreg509:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg509,%vreg503 VReg_32:%vreg508
	Joined. Result = %vreg509 [1216r,1248r:0)[1248r,1760r:1)  0@1216r 1@1248r
1296B	%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
	Not coalescable.
1376B	%vreg130:sub0<def,read-undef> = COPY %vreg127; VReg_64:%vreg130 VReg_32:%vreg127
	Considering merging to VReg_64 with %vreg127 in %vreg130:sub0
		RHS = %vreg127 [1344r,1376r:0)  0@1344r
		LHS = %vreg130 [1376r,1392r:1)[1392r,1408r:0)  0@1392r 1@1376r
		merge %vreg130:1@1376r into %vreg127:0@1344r --> @1344r
		erased:	1376r	%vreg130:sub0<def,read-undef> = COPY %vreg127; VReg_64:%vreg130 VReg_32:%vreg127
		updated: 1344B	%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
		updated: 1360B	%vreg520<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_32:%vreg520 VReg_64:%vreg130
	Joined. Result = %vreg130 [1344r,1392r:0)[1392r,1408r:1)  0@1344r 1@1392r
1392B	%vreg130:sub1<def> = COPY %vreg520; VReg_64:%vreg130 VReg_32:%vreg520
	Considering merging to VReg_64 with %vreg520 in %vreg130:sub1
		RHS = %vreg520 [1360r,1392r:0)  0@1360r
		LHS = %vreg130 [1344r,1392r:0)[1392r,1408r:1)  0@1344r 1@1392r
		merge %vreg130:1@1392r into %vreg520:0@1360r --> @1360r
		pruned %vreg130 at 1360r: %vreg130 [1344r,1360r:0)[1392r,1408r:1)  0@1344r 1@1392r
		erased:	1392r	%vreg130:sub1<def> = COPY %vreg520; VReg_64:%vreg130 VReg_32:%vreg520
		restoring liveness to 2 points: %vreg130 [1344r,1360r:0)[1360r,1408r:1)  0@1344r 1@1360r
		updated: 1360B	%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_64:%vreg130
	Joined. Result = %vreg130 [1344r,1360r:0)[1360r,1408r:1)  0@1344r 1@1360r
1424B	%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
	Considering merging to VReg_64 with %vreg537 in %vreg522:sub0
		RHS = %vreg537 [1424r,1488r:0)  0@1424r
		LHS = %vreg522 [1408r,1440r:0)  0@1408r
		merge %vreg537:0@1424r into %vreg522:0@1408r --> @1408r
		erased:	1424r	%vreg537<def> = COPY %vreg522:sub0; VReg_32:%vreg537 VReg_64:%vreg522
		updated: 1488B	%vreg538<def> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg538,%vreg539 VReg_64:%vreg522
	Joined. Result = %vreg522 [1408r,1488r:0)  0@1408r
1440B	%vreg523<def> = COPY %vreg522:sub1; VReg_32:%vreg523 VReg_64:%vreg522
	Considering merging to VReg_64 with %vreg523 in %vreg522:sub1
		RHS = %vreg523 [1440r,1504r:0)  0@1440r
		LHS = %vreg522 [1408r,1488r:0)  0@1408r
		merge %vreg523:0@1440r into %vreg522:0@1408r --> @1408r
		erased:	1440r	%vreg523<def> = COPY %vreg522:sub1; VReg_32:%vreg523 VReg_64:%vreg522
		updated: 1504B	%vreg524<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg524,%vreg540 VReg_64:%vreg522
	Joined. Result = %vreg522 [1408r,1504r:0)  0@1408r
1456B	%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
	Not coalescable.
1472B	%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
	Not coalescable.
1520B	%vreg526:sub0<def,read-undef> = COPY %vreg538; VReg_64:%vreg526 VReg_32:%vreg538
	Considering merging to VReg_64 with %vreg538 in %vreg526:sub0
		RHS = %vreg538 [1488r,1520r:0)  0@1488r
		LHS = %vreg526 [1520r,1536r:1)[1536r,1568r:0)  0@1536r 1@1520r
		merge %vreg526:1@1520r into %vreg538:0@1488r --> @1488r
		erased:	1520r	%vreg526:sub0<def,read-undef> = COPY %vreg538; VReg_64:%vreg526 VReg_32:%vreg538
		updated: 1488B	%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
	Joined. Result = %vreg526 [1488r,1536r:0)[1536r,1568r:1)  0@1488r 1@1536r
1536B	%vreg526:sub1<def> = COPY %vreg524; VReg_64:%vreg526 VReg_32:%vreg524
	Considering merging to VReg_64 with %vreg524 in %vreg526:sub1
		RHS = %vreg524 [1504r,1536r:0)  0@1504r
		LHS = %vreg526 [1488r,1536r:0)[1536r,1568r:1)  0@1488r 1@1536r
		merge %vreg526:1@1536r into %vreg524:0@1504r --> @1504r
		pruned %vreg526 at 1504r: %vreg526 [1488r,1504r:0)[1536r,1568r:1)  0@1488r 1@1536r
		erased:	1536r	%vreg526:sub1<def> = COPY %vreg524; VReg_64:%vreg526 VReg_32:%vreg524
		restoring liveness to 2 points: %vreg526 [1488r,1504r:0)[1504r,1568r:1)  0@1488r 1@1504r
		updated: 1504B	%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
	Joined. Result = %vreg526 [1488r,1504r:0)[1504r,1568r:1)  0@1488r 1@1504r
1552B	%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
	Considering merging to VReg_64 with %vreg535 in %vreg526:sub0
		RHS = %vreg535 [1552r,1584r:0)  0@1552r
		LHS = %vreg526 [1488r,1504r:0)[1504r,1568r:1)  0@1488r 1@1504r
		merge %vreg535:0@1552r into %vreg526:1@1504r --> @1504r
		erased:	1552r	%vreg535<def> = COPY %vreg526:sub0; VReg_32:%vreg535 VReg_64:%vreg526
		updated: 1584B	%vreg536<def> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg536 SGPR_64:%vreg116 VReg_64:%vreg526
	Joined. Result = %vreg526 [1488r,1504r:0)[1504r,1584r:1)  0@1488r 1@1504r
1568B	%vreg529<def> = COPY %vreg526:sub1; VReg_32:%vreg529 VReg_64:%vreg526
	Considering merging to VReg_64 with %vreg529 in %vreg526:sub1
		RHS = %vreg529 [1568r,1616r:0)  0@1568r
		LHS = %vreg526 [1488r,1504r:0)[1504r,1584r:1)  0@1488r 1@1504r
		merge %vreg529:0@1568r into %vreg526:1@1504r --> @1504r
		erased:	1568r	%vreg529<def> = COPY %vreg526:sub1; VReg_32:%vreg529 VReg_64:%vreg526
		updated: 1616B	%vreg530<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg530,%vreg531 VReg_64:%vreg526
	Joined. Result = %vreg526 [1488r,1504r:0)[1504r,1616r:1)  0@1488r 1@1504r
1600B	%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
	Not coalescable.
1632B	%vreg532:sub0<def,read-undef> = COPY %vreg536; VReg_64:%vreg532 VReg_32:%vreg536
	Considering merging to VReg_64 with %vreg536 in %vreg532:sub0
		RHS = %vreg536 [1584r,1632r:0)  0@1584r
		LHS = %vreg532 [1632r,1648r:1)[1648r,1776r:0)  0@1648r 1@1632r
		merge %vreg532:1@1632r into %vreg536:0@1584r --> @1584r
		erased:	1632r	%vreg532:sub0<def,read-undef> = COPY %vreg536; VReg_64:%vreg532 VReg_32:%vreg536
		updated: 1584B	%vreg532:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg532,%vreg526 SGPR_64:%vreg116
	Joined. Result = %vreg532 [1584r,1648r:0)[1648r,1776r:1)  0@1584r 1@1648r
1648B	%vreg532:sub1<def> = COPY %vreg530; VReg_64:%vreg532 VReg_32:%vreg530
	Considering merging to VReg_64 with %vreg530 in %vreg532:sub1
		RHS = %vreg530 [1616r,1648r:0)  0@1616r
		LHS = %vreg532 [1584r,1648r:0)[1648r,1776r:1)  0@1584r 1@1648r
		merge %vreg532:1@1648r into %vreg530:0@1616r --> @1616r
		pruned %vreg532 at 1616r: %vreg532 [1584r,1616r:0)[1648r,1776r:1)  0@1584r 1@1648r
		erased:	1648r	%vreg532:sub1<def> = COPY %vreg530; VReg_64:%vreg532 VReg_32:%vreg530
		restoring liveness to 2 points: %vreg532 [1584r,1616r:0)[1616r,1776r:1)  0@1584r 1@1616r
		updated: 1616B	%vreg532:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg532,%vreg526 VReg_32:%vreg531
	Joined. Result = %vreg532 [1584r,1616r:0)[1616r,1776r:1)  0@1584r 1@1616r
1680B	%vreg95<def> = COPY %vreg145; VGPR_32:%vreg95,%vreg145
	Considering merging to VGPR_32 with %vreg145 in %vreg95
		RHS = %vreg145 [1664r,1680r:0)  0@1664r
		LHS = %vreg95 [1680r,2064r:0)  0@1680r
		merge %vreg95:0@1680r into %vreg145:0@1664r --> @1664r
		erased:	1680r	%vreg95<def> = COPY %vreg145; VGPR_32:%vreg95,%vreg145
		updated: 1664B	%vreg95<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg95
	Joined. Result = %vreg95 [1664r,2064r:0)  0@1664r
1712B	%vreg541<def> = COPY %vreg146; VReg_32:%vreg541,%vreg146
	Considering merging to VReg_32 with %vreg146 in %vreg541
		RHS = %vreg146 [1696r,1712r:0)  0@1696r
		LHS = %vreg541 [1712r,1984r:0)  0@1712r
		merge %vreg541:0@1712r into %vreg146:0@1696r --> @1696r
		erased:	1712r	%vreg541<def> = COPY %vreg146; VReg_32:%vreg541,%vreg146
		updated: 1696B	%vreg541<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg541
	Joined. Result = %vreg541 [1696r,1984r:0)  0@1696r
1744B	%vreg93<def> = COPY %vreg676:sub0_sub1; SGPR_64:%vreg93 SReg_128:%vreg676
	Considering merging to SReg_128 with %vreg93 in %vreg676:sub0_sub1
		RHS = %vreg93 [1744r,2000r:0)  0@1744r
		LHS = %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
		merge %vreg93:0@1744r into %vreg676:1@1728r --> @1728r
		pruned %vreg93 at 1792r: %vreg93 [1744r,1792r:0)  0@1744r
		pruned %vreg93 at 1808r: %vreg93 [1744r,1792r:0)  0@1744r
		pruned all of %vreg93 at 1744r: %vreg93 EMPTY  0@1744r
		erased:	1744r	%vreg93<def> = COPY %vreg676:sub0_sub1; SGPR_64:%vreg93 SReg_128:%vreg676
		restoring liveness to 4 points: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
		updated: 2000B	%vreg851<def> = COPY %vreg676:sub0_sub1; SReg_64:%vreg851 SReg_128:%vreg676
	Joined. Result = %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
1760B	%vreg12<def> = COPY %vreg509; VReg_64:%vreg12,%vreg509
	Considering merging to VReg_64 with %vreg509 in %vreg12
		RHS = %vreg12 [1760r,2016r:0)  0@1760r
		LHS = %vreg509 [1216r,1248r:0)[1248r,1760r:1)  0@1216r 1@1248r
		merge %vreg12:0@1760r into %vreg509:1@1248r --> @1248r
		erased:	1760r	%vreg12<def> = COPY %vreg509; VReg_64:%vreg12,%vreg509
		updated: 2016B	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg509; VReg_128:%vreg687 VReg_64:%vreg509
	Joined. Result = %vreg509 [1216r,1248r:0)[1248r,2016r:1)  0@1216r 1@1248r
1776B	%vreg11<def> = COPY %vreg532; VReg_64:%vreg11,%vreg532
	Considering merging to VReg_64 with %vreg532 in %vreg11
		RHS = %vreg11 [1776r,2032r:0)  0@1776r
		LHS = %vreg532 [1584r,1616r:0)[1616r,1776r:1)  0@1584r 1@1616r
		merge %vreg11:0@1776r into %vreg532:1@1616r --> @1616r
		erased:	1776r	%vreg11<def> = COPY %vreg532; VReg_64:%vreg11,%vreg532
		updated: 2032B	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg532; VReg_128:%vreg562 VReg_64:%vreg532
	Joined. Result = %vreg532 [1584r,1616r:0)[1616r,2032r:1)  0@1584r 1@1616r
1984B	%vreg543<def> = COPY %vreg541; VReg_32:%vreg543,%vreg541
	Considering merging to VReg_32 with %vreg541 in %vreg543
		RHS = %vreg541 [1696r,1984r:0)  0@1696r
		LHS = %vreg543 [1984r,2048r:0)  0@1984r
		merge %vreg543:0@1984r into %vreg541:0@1696r --> @1696r
		erased:	1984r	%vreg543<def> = COPY %vreg541; VReg_32:%vreg543,%vreg541
		updated: 1696B	%vreg543<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg543
	Joined. Result = %vreg543 [1696r,2048r:0)  0@1696r
2000B	%vreg851<def> = COPY %vreg676:sub0_sub1; SReg_64:%vreg851 SReg_128:%vreg676
	Considering merging to SReg_128 with %vreg851 in %vreg676:sub0_sub1
		RHS = %vreg851 [2000r,2096B:0)[2096B,2112r:2)[3552B,9600r:1)[9600r,9808B:2)  0@2000r 1@3552B-phi 2@9600r
		LHS = %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
		merge %vreg851:0@2000r into %vreg676:3@1808r --> @1808r
		merge %vreg851:1@3552B into %vreg676:0@3552B --> @3552B
		interference at %vreg851:2@9600r
  %vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
Checking if cheap as move
Checking if remat as move
Checking if safe to move
Checking sub-regChecking idxs
		updated: 2000B	%vreg851:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg851
		updated: 9600B	%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297, %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
		updated: 2112B	SI_END_CF %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
		updated: 9776B	SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
Remat: %vreg851:sub3<def,read-undef> = S_MOV_B32 61440; SReg_128:%vreg851
Shrink: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
Shrunk: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
2016B	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg509; VReg_128:%vreg687 VReg_64:%vreg509
	Considering merging to VReg_128 with %vreg509 in %vreg687:sub0_sub1
		RHS = %vreg509 [1216r,1248r:0)[1248r,2016r:1)  0@1216r 1@1248r
		LHS = %vreg687 [2016r,2096B:2)[3552B,4640r:0)[4640r,9360r:1)[9360r,9392r:3)[9392r,9808B:4)  0@3552B-phi 1@4640r 2@2016r 3@9360r 4@9392r
		merge %vreg687:2@2016r into %vreg509:1@1248r --> @1248r
		erased:	2016r	%vreg687:sub0_sub1<def,read-undef> = COPY %vreg509; VReg_128:%vreg687 VReg_64:%vreg509
		updated: 1248B	%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
		updated: 1216B	%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
	Joined. Result = %vreg687 [1216r,1248r:2)[1248r,2096B:3)[3552B,4640r:0)[4640r,9360r:1)[9360r,9392r:4)[9392r,9808B:5)  0@3552B-phi 1@4640r 2@1216r 3@1248r 4@9360r 5@9392r
2032B	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg532; VReg_128:%vreg562 VReg_64:%vreg532
	Considering merging to VReg_128 with %vreg532 in %vreg562:sub0_sub1
		RHS = %vreg532 [1584r,1616r:0)[1616r,2032r:1)  0@1584r 1@1616r
		LHS = %vreg562 [2032r,2096B:2)[3552B,4288r:0)[4288r,9472r:1)[9472r,9504r:3)[9504r,9808B:4)  0@3552B-phi 1@4288r 2@2032r 3@9472r 4@9504r
		merge %vreg562:2@2032r into %vreg532:1@1616r --> @1616r
		erased:	2032r	%vreg562:sub0_sub1<def,read-undef> = COPY %vreg532; VReg_128:%vreg562 VReg_64:%vreg532
		updated: 1616B	%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
		updated: 1584B	%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
	Joined. Result = %vreg562 [1584r,1616r:2)[1616r,2096B:3)[3552B,4288r:0)[4288r,9472r:1)[9472r,9504r:4)[9504r,9808B:5)  0@3552B-phi 1@4288r 2@1584r 3@1616r 4@9472r 5@9504r
2048B	%vreg854<def> = COPY %vreg543; VReg_32:%vreg854,%vreg543
	Considering merging to VReg_32 with %vreg543 in %vreg854
		RHS = %vreg543 [1696r,2048r:0)  0@1696r
		LHS = %vreg854 [2048r,2096B:0)[3552B,9568r:1)[9568r,9808B:2)  0@2048r 1@3552B-phi 2@9568r
		merge %vreg854:0@2048r into %vreg543:0@1696r --> @1696r
		erased:	2048r	%vreg854<def> = COPY %vreg543; VReg_32:%vreg854,%vreg543
		updated: 1696B	%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
	Joined. Result = %vreg854 [1696r,2096B:0)[3552B,9568r:1)[9568r,9808B:2)  0@1696r 1@3552B-phi 2@9568r
2064B	%vreg855<def> = COPY %vreg95; VGPR_32:%vreg855,%vreg95
	Considering merging to VGPR_32 with %vreg95 in %vreg855
		RHS = %vreg95 [1664r,2064r:0)  0@1664r
		LHS = %vreg855 [2064r,2096B:0)[2096B,2176r:2)[3552B,9280r:1)[9280r,9808B:2)  0@2064r 1@3552B-phi 2@9280r
		merge %vreg855:0@2064r into %vreg95:0@1664r --> @1664r
		erased:	2064r	%vreg855<def> = COPY %vreg95; VGPR_32:%vreg855,%vreg95
		updated: 1664B	%vreg855<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg855
	Joined. Result = %vreg855 [1664r,2096B:0)[2096B,2176r:2)[3552B,9280r:1)[9280r,9808B:2)  0@1664r 1@3552B-phi 2@9280r
for.cond.for.cond29.preheader_crit_edge:
2160B	%vreg451<def> = COPY %vreg13; VReg_32:%vreg451 SReg_32:%vreg13
	Not coalescable.
2176B	%vreg856<def> = COPY %vreg855; VGPR_32:%vreg856,%vreg855
	Considering merging to VGPR_32 with %vreg855 in %vreg856
		RHS = %vreg855 [1664r,2096B:0)[2096B,2176r:2)[3552B,9280r:1)[9280r,9808B:2)  0@1664r 1@3552B-phi 2@9280r
		LHS = %vreg856 [752r,864B:3)[2176r,2224B:4)[2272B,3376r:0)[3408B,3552B:0)[9808B,9872B:2)[10624r,10656B:1)[10656B,10912r:2)  0@3408B-phi 1@10624r 2@9808B-phi 3@752r 4@2176r
		merge %vreg856:4@2176r into %vreg855:2@9280r --> @9280r
		erased:	2176r	%vreg856<def> = COPY %vreg855; VGPR_32:%vreg856,%vreg855
		updated: 1664B	%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
		updated: 9280B	%vreg856<def> = V_ADD_F32_e32 %vreg856, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
	Joined. Result = %vreg856 [752r,864B:3)[1664r,2096B:5)[2096B,2224B:4)[2272B,3376r:0)[3408B,3552B:0)[3552B,9280r:6)[9280r,9808B:4)[9808B,9872B:2)[10624r,10656B:1)[10656B,10912r:2)  0@3408B-phi 1@10624r 2@9808B-phi 3@752r 4@9280r 5@1664r 6@3552B-phi
2192B	%vreg850<def> = COPY %vreg451; VReg_32:%vreg850,%vreg451
	Considering merging to VReg_32 with %vreg451 in %vreg850
		RHS = %vreg451 [2160r,2192r:0)  0@2160r
		LHS = %vreg850 [720r,864B:0)[2192r,2224B:1)[2272B,3168r:2)[3408B,3552B:2)  0@720r 1@2192r 2@3408B-phi
		merge %vreg850:1@2192r into %vreg451:0@2160r --> @2160r
		erased:	2192r	%vreg850<def> = COPY %vreg451; VReg_32:%vreg850,%vreg451
		updated: 2160B	%vreg850<def> = COPY %vreg13; VReg_32:%vreg850 SReg_32:%vreg13
	Joined. Result = %vreg850 [720r,864B:0)[2160r,2224B:1)[2272B,3168r:2)[3408B,3552B:2)  0@720r 1@2160r 2@3408B-phi
for.body31.lr.ph:
2384B	%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
	Not coalescable.
2464B	%vreg312:sub0<def,read-undef> = COPY %vreg309; VReg_64:%vreg312 VReg_32:%vreg309
	Considering merging to VReg_64 with %vreg309 in %vreg312:sub0
		RHS = %vreg309 [2432r,2464r:0)  0@2432r
		LHS = %vreg312 [2464r,2480r:1)[2480r,2512r:0)  0@2480r 1@2464r
		merge %vreg312:1@2464r into %vreg309:0@2432r --> @2432r
		erased:	2464r	%vreg312:sub0<def,read-undef> = COPY %vreg309; VReg_64:%vreg312 VReg_32:%vreg309
		updated: 2432B	%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
		updated: 2448B	%vreg548<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_32:%vreg548 VReg_64:%vreg312
	Joined. Result = %vreg312 [2432r,2480r:0)[2480r,2512r:1)  0@2432r 1@2480r
2480B	%vreg312:sub1<def> = COPY %vreg548; VReg_64:%vreg312 VReg_32:%vreg548
	Considering merging to VReg_64 with %vreg548 in %vreg312:sub1
		RHS = %vreg548 [2448r,2480r:0)  0@2448r
		LHS = %vreg312 [2432r,2480r:0)[2480r,2512r:1)  0@2432r 1@2480r
		merge %vreg312:1@2480r into %vreg548:0@2448r --> @2448r
		pruned %vreg312 at 2448r: %vreg312 [2432r,2448r:0)[2480r,2512r:1)  0@2432r 1@2480r
		erased:	2480r	%vreg312:sub1<def> = COPY %vreg548; VReg_64:%vreg312 VReg_32:%vreg548
		restoring liveness to 2 points: %vreg312 [2432r,2448r:0)[2448r,2512r:1)  0@2432r 1@2448r
		updated: 2448B	%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_64:%vreg312
	Joined. Result = %vreg312 [2432r,2448r:0)[2448r,2512r:1)  0@2432r 1@2448r
2496B	%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
	Considering merging to VReg_64 with %vreg549 in %vreg312:sub0
		RHS = %vreg549 [2496r,2608r:0)  0@2496r
		LHS = %vreg312 [2432r,2448r:0)[2448r,2512r:1)  0@2432r 1@2448r
		merge %vreg549:0@2496r into %vreg312:1@2448r --> @2448r
		erased:	2496r	%vreg549<def> = COPY %vreg312:sub0; VReg_32:%vreg549 VReg_64:%vreg312
		updated: 2608B	%vreg493<def> = V_ADD_I32_e32 %vreg312:sub0, %vreg491, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493,%vreg491 VReg_64:%vreg312
	Joined. Result = %vreg312 [2432r,2448r:0)[2448r,2608r:1)  0@2432r 1@2448r
2512B	%vreg550<def> = COPY %vreg312:sub1; VReg_32:%vreg550 VReg_64:%vreg312
	Considering merging to VReg_64 with %vreg550 in %vreg312:sub1
		RHS = %vreg550 [2512r,2624r:0)  0@2512r
		LHS = %vreg312 [2432r,2448r:0)[2448r,2608r:1)  0@2432r 1@2448r
		merge %vreg550:0@2512r into %vreg312:1@2448r --> @2448r
		erased:	2512r	%vreg550<def> = COPY %vreg312:sub1; VReg_32:%vreg550 VReg_64:%vreg312
		updated: 2624B	%vreg477<def> = V_ADDC_U32_e32 %vreg462, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg477,%vreg462 VReg_64:%vreg312
	Joined. Result = %vreg312 [2432r,2448r:0)[2448r,2624r:1)  0@2432r 1@2448r
2544B	%vreg459:sub0<def,read-undef> = COPY %vreg850; VReg_64:%vreg459 VReg_32:%vreg850
	Considering merging to VReg_64 with %vreg850 in %vreg459:sub0
		RHS = %vreg850 [720r,864B:0)[2160r,2224B:1)[2272B,3168r:2)[3408B,3552B:2)  0@720r 1@2160r 2@3408B-phi
		LHS = %vreg459 [2544r,2560r:1)[2560r,2592r:0)  0@2560r 1@2544r
		merge %vreg459:1@2544r into %vreg850:2@3408B --> @3408B
		pruned %vreg850 at 2560r: %vreg850 [720r,864B:0)[2160r,2224B:1)[2272B,2560r:2)[3408B,3552B:2)  0@720r 1@2160r 2@3408B-phi
		pruned all of %vreg459 at 2544r: %vreg459 [2560r,2592r:0)  0@2560r 1@2544r
		erased:	2544r	%vreg459:sub0<def,read-undef> = COPY %vreg850; VReg_64:%vreg459 VReg_32:%vreg850
		restoring liveness to 3 points: %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2560r:0)[2560r,2592r:1)[3408B,3552B:0)  0@3408B-phi 1@2560r 2@720r 3@2160r
		updated: 2160B	%vreg459:sub0<def,read-undef> = COPY %vreg13; VReg_64:%vreg459 SReg_32:%vreg13
		updated: 720B	%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
		updated: 2304B	%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
		updated: 3168B	%vreg454<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg454 SGPR_32:%vreg55 VReg_64:%vreg459
		updated: 2528B	%vreg494<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_32:%vreg494 VReg_64:%vreg459
	Joined. Result = %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2560r:0)[2560r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2560r 2@720r 3@2160r
2560B	%vreg459:sub1<def> = COPY %vreg494; VReg_64:%vreg459 VReg_32:%vreg494
	Considering merging to VReg_64 with %vreg494 in %vreg459:sub1
		RHS = %vreg494 [2528r,2560r:0)  0@2528r
		LHS = %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2560r:0)[2560r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2560r 2@720r 3@2160r
		merge %vreg459:1@2560r into %vreg494:0@2528r --> @2528r
		conflict at %vreg494:0@2528r
		taints local %vreg459:0@2272B to 2560r
		pruned %vreg459 at 2528r: %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2560r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2560r 2@720r 3@2160r
		erased:	2560r	%vreg459:sub1<def> = COPY %vreg494; VReg_64:%vreg459 VReg_32:%vreg494
		restoring liveness to 2 points: %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2528r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2528r 2@720r 3@2160r
		updated: 2528B	%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_64:%vreg459
	Joined. Result = %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2528r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2528r 2@720r 3@2160r
2576B	%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
	Considering merging to VReg_64 with %vreg491 in %vreg459:sub0
		RHS = %vreg491 [2576r,2960r:0)  0@2576r
		LHS = %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2528r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2528r 2@720r 3@2160r
		merge %vreg491:0@2576r into %vreg459:1@2528r --> @2528r
		erased:	2576r	%vreg491<def> = COPY %vreg459:sub0; VReg_32:%vreg491 VReg_64:%vreg459
		updated: 2608B	%vreg493<def> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg493 VReg_64:%vreg312,%vreg459
		updated: 2960B	%vreg492<def> = V_ADD_I32_e32 %vreg556, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492,%vreg556 VReg_64:%vreg459
	Joined. Result = %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2528r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2528r 2@720r 3@2160r
2592B	%vreg462<def> = COPY %vreg459:sub1; VReg_32:%vreg462 VReg_64:%vreg459
	Considering merging to VReg_64 with %vreg462 in %vreg459:sub1
		RHS = %vreg462 [2592r,2976r:0)  0@2592r
		LHS = %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2528r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2528r 2@720r 3@2160r
		merge %vreg462:0@2592r into %vreg459:1@2528r --> @2528r
		erased:	2592r	%vreg462<def> = COPY %vreg459:sub1; VReg_32:%vreg462 VReg_64:%vreg459
		updated: 2624B	%vreg477<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg477 VReg_64:%vreg459,%vreg312
		updated: 2976B	%vreg463<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg557, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg463,%vreg557 VReg_64:%vreg459
	Joined. Result = %vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2528r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2528r 2@720r 3@2160r
2640B	%vreg479:sub0<def,read-undef> = COPY %vreg493; VReg_64:%vreg479 VReg_32:%vreg493
	Considering merging to VReg_64 with %vreg493 in %vreg479:sub0
		RHS = %vreg493 [2608r,2640r:0)  0@2608r
		LHS = %vreg479 [2640r,2656r:1)[2656r,2672r:0)  0@2656r 1@2640r
		merge %vreg479:1@2640r into %vreg493:0@2608r --> @2608r
		erased:	2640r	%vreg479:sub0<def,read-undef> = COPY %vreg493; VReg_64:%vreg479 VReg_32:%vreg493
		updated: 2608B	%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
	Joined. Result = %vreg479 [2608r,2656r:0)[2656r,2672r:1)  0@2608r 1@2656r
2656B	%vreg479:sub1<def> = COPY %vreg477; VReg_64:%vreg479 VReg_32:%vreg477
	Considering merging to VReg_64 with %vreg477 in %vreg479:sub1
		RHS = %vreg477 [2624r,2656r:0)  0@2624r
		LHS = %vreg479 [2608r,2656r:0)[2656r,2672r:1)  0@2608r 1@2656r
		merge %vreg479:1@2656r into %vreg477:0@2624r --> @2624r
		pruned %vreg479 at 2624r: %vreg479 [2608r,2624r:0)[2656r,2672r:1)  0@2608r 1@2656r
		erased:	2656r	%vreg479:sub1<def> = COPY %vreg477; VReg_64:%vreg479 VReg_32:%vreg477
		restoring liveness to 2 points: %vreg479 [2608r,2624r:0)[2624r,2672r:1)  0@2608r 1@2624r
		updated: 2624B	%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
	Joined. Result = %vreg479 [2608r,2624r:0)[2624r,2672r:1)  0@2608r 1@2624r
2688B	%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
	Considering merging to VReg_64 with %vreg489 in %vreg482:sub0
		RHS = %vreg489 [2688r,2752r:0)  0@2688r
		LHS = %vreg482 [2672r,2704r:0)  0@2672r
		merge %vreg489:0@2688r into %vreg482:0@2672r --> @2672r
		erased:	2688r	%vreg489<def> = COPY %vreg482:sub0; VReg_32:%vreg489 VReg_64:%vreg482
		updated: 2752B	%vreg490<def> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg490,%vreg551 VReg_64:%vreg482
	Joined. Result = %vreg482 [2672r,2752r:0)  0@2672r
2704B	%vreg483<def> = COPY %vreg482:sub1; VReg_32:%vreg483 VReg_64:%vreg482
	Considering merging to VReg_64 with %vreg483 in %vreg482:sub1
		RHS = %vreg483 [2704r,2768r:0)  0@2704r
		LHS = %vreg482 [2672r,2752r:0)  0@2672r
		merge %vreg483:0@2704r into %vreg482:0@2672r --> @2672r
		erased:	2704r	%vreg483<def> = COPY %vreg482:sub1; VReg_32:%vreg483 VReg_64:%vreg482
		updated: 2768B	%vreg484<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg484,%vreg552 VReg_64:%vreg482
	Joined. Result = %vreg482 [2672r,2768r:0)  0@2672r
2720B	%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
	Not coalescable.
2736B	%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
	Not coalescable.
2784B	%vreg486:sub0<def,read-undef> = COPY %vreg490; VReg_64:%vreg486 VReg_32:%vreg490
	Considering merging to VReg_64 with %vreg490 in %vreg486:sub0
		RHS = %vreg490 [2752r,2784r:0)  0@2752r
		LHS = %vreg486 [2784r,2800r:1)[2800r,3216r:0)  0@2800r 1@2784r
		merge %vreg486:1@2784r into %vreg490:0@2752r --> @2752r
		erased:	2784r	%vreg486:sub0<def,read-undef> = COPY %vreg490; VReg_64:%vreg486 VReg_32:%vreg490
		updated: 2752B	%vreg486:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg486,%vreg482 VReg_32:%vreg551
	Joined. Result = %vreg486 [2752r,2800r:0)[2800r,3216r:1)  0@2752r 1@2800r
2800B	%vreg486:sub1<def> = COPY %vreg484; VReg_64:%vreg486 VReg_32:%vreg484
	Considering merging to VReg_64 with %vreg484 in %vreg486:sub1
		RHS = %vreg484 [2768r,2800r:0)  0@2768r
		LHS = %vreg486 [2752r,2800r:0)[2800r,3216r:1)  0@2752r 1@2800r
		merge %vreg486:1@2800r into %vreg484:0@2768r --> @2768r
		pruned %vreg486 at 2768r: %vreg486 [2752r,2768r:0)[2800r,3216r:1)  0@2752r 1@2800r
		erased:	2800r	%vreg486:sub1<def> = COPY %vreg484; VReg_64:%vreg486 VReg_32:%vreg484
		restoring liveness to 2 points: %vreg486 [2752r,2768r:0)[2768r,3216r:1)  0@2752r 1@2768r
		updated: 2768B	%vreg486:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg486,%vreg482 VReg_32:%vreg552
	Joined. Result = %vreg486 [2752r,2768r:0)[2768r,3216r:1)  0@2752r 1@2768r
2816B	%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
	Not coalescable.
2896B	%vreg338:sub0<def,read-undef> = COPY %vreg335; VReg_64:%vreg338 VReg_32:%vreg335
	Considering merging to VReg_64 with %vreg335 in %vreg338:sub0
		RHS = %vreg335 [2864r,2896r:0)  0@2864r
		LHS = %vreg338 [2896r,2912r:1)[2912r,2944r:0)  0@2912r 1@2896r
		merge %vreg338:1@2896r into %vreg335:0@2864r --> @2864r
		erased:	2896r	%vreg338:sub0<def,read-undef> = COPY %vreg335; VReg_64:%vreg338 VReg_32:%vreg335
		updated: 2864B	%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
		updated: 2880B	%vreg555<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_32:%vreg555 VReg_64:%vreg338
	Joined. Result = %vreg338 [2864r,2912r:0)[2912r,2944r:1)  0@2864r 1@2912r
2912B	%vreg338:sub1<def> = COPY %vreg555; VReg_64:%vreg338 VReg_32:%vreg555
	Considering merging to VReg_64 with %vreg555 in %vreg338:sub1
		RHS = %vreg555 [2880r,2912r:0)  0@2880r
		LHS = %vreg338 [2864r,2912r:0)[2912r,2944r:1)  0@2864r 1@2912r
		merge %vreg338:1@2912r into %vreg555:0@2880r --> @2880r
		pruned %vreg338 at 2880r: %vreg338 [2864r,2880r:0)[2912r,2944r:1)  0@2864r 1@2912r
		erased:	2912r	%vreg338:sub1<def> = COPY %vreg555; VReg_64:%vreg338 VReg_32:%vreg555
		restoring liveness to 2 points: %vreg338 [2864r,2880r:0)[2880r,2944r:1)  0@2864r 1@2880r
		updated: 2880B	%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_64:%vreg338
	Joined. Result = %vreg338 [2864r,2880r:0)[2880r,2944r:1)  0@2864r 1@2880r
2928B	%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
	Considering merging to VReg_64 with %vreg556 in %vreg338:sub0
		RHS = %vreg556 [2928r,2960r:0)  0@2928r
		LHS = %vreg338 [2864r,2880r:0)[2880r,2944r:1)  0@2864r 1@2880r
		merge %vreg556:0@2928r into %vreg338:1@2880r --> @2880r
		erased:	2928r	%vreg556<def> = COPY %vreg338:sub0; VReg_32:%vreg556 VReg_64:%vreg338
		updated: 2960B	%vreg492<def> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg492 VReg_64:%vreg338,%vreg459
	Joined. Result = %vreg338 [2864r,2880r:0)[2880r,2960r:1)  0@2864r 1@2880r
2944B	%vreg557<def> = COPY %vreg338:sub1; VReg_32:%vreg557 VReg_64:%vreg338
	Considering merging to VReg_64 with %vreg557 in %vreg338:sub1
		RHS = %vreg557 [2944r,2976r:0)  0@2944r
		LHS = %vreg338 [2864r,2880r:0)[2880r,2960r:1)  0@2864r 1@2880r
		merge %vreg557:0@2944r into %vreg338:1@2880r --> @2880r
		erased:	2944r	%vreg557<def> = COPY %vreg338:sub1; VReg_32:%vreg557 VReg_64:%vreg338
		updated: 2976B	%vreg463<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg463 VReg_64:%vreg459,%vreg338
	Joined. Result = %vreg338 [2864r,2880r:0)[2880r,2976r:1)  0@2864r 1@2880r
2992B	%vreg465:sub0<def,read-undef> = COPY %vreg492; VReg_64:%vreg465 VReg_32:%vreg492
	Considering merging to VReg_64 with %vreg492 in %vreg465:sub0
		RHS = %vreg492 [2960r,2992r:0)  0@2960r
		LHS = %vreg465 [2992r,3008r:1)[3008r,3024r:0)  0@3008r 1@2992r
		merge %vreg465:1@2992r into %vreg492:0@2960r --> @2960r
		erased:	2992r	%vreg465:sub0<def,read-undef> = COPY %vreg492; VReg_64:%vreg465 VReg_32:%vreg492
		updated: 2960B	%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
	Joined. Result = %vreg465 [2960r,3008r:0)[3008r,3024r:1)  0@2960r 1@3008r
3008B	%vreg465:sub1<def> = COPY %vreg463; VReg_64:%vreg465 VReg_32:%vreg463
	Considering merging to VReg_64 with %vreg463 in %vreg465:sub1
		RHS = %vreg463 [2976r,3008r:0)  0@2976r
		LHS = %vreg465 [2960r,3008r:0)[3008r,3024r:1)  0@2960r 1@3008r
		merge %vreg465:1@3008r into %vreg463:0@2976r --> @2976r
		pruned %vreg465 at 2976r: %vreg465 [2960r,2976r:0)[3008r,3024r:1)  0@2960r 1@3008r
		erased:	3008r	%vreg465:sub1<def> = COPY %vreg463; VReg_64:%vreg465 VReg_32:%vreg463
		restoring liveness to 2 points: %vreg465 [2960r,2976r:0)[2976r,3024r:1)  0@2960r 1@2976r
		updated: 2976B	%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
	Joined. Result = %vreg465 [2960r,2976r:0)[2976r,3024r:1)  0@2960r 1@2976r
3040B	%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
	Considering merging to VReg_64 with %vreg475 in %vreg468:sub0
		RHS = %vreg475 [3040r,3104r:0)  0@3040r
		LHS = %vreg468 [3024r,3056r:0)  0@3024r
		merge %vreg475:0@3040r into %vreg468:0@3024r --> @3024r
		erased:	3040r	%vreg475<def> = COPY %vreg468:sub0; VReg_32:%vreg475 VReg_64:%vreg468
		updated: 3104B	%vreg476<def> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_32:%vreg476,%vreg558 VReg_64:%vreg468
	Joined. Result = %vreg468 [3024r,3104r:0)  0@3024r
3056B	%vreg469<def> = COPY %vreg468:sub1; VReg_32:%vreg469 VReg_64:%vreg468
	Considering merging to VReg_64 with %vreg469 in %vreg468:sub1
		RHS = %vreg469 [3056r,3120r:0)  0@3056r
		LHS = %vreg468 [3024r,3104r:0)  0@3024r
		merge %vreg469:0@3056r into %vreg468:0@3024r --> @3024r
		erased:	3056r	%vreg469<def> = COPY %vreg468:sub1; VReg_32:%vreg469 VReg_64:%vreg468
		updated: 3120B	%vreg470<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_32:%vreg470,%vreg559 VReg_64:%vreg468
	Joined. Result = %vreg468 [3024r,3120r:0)  0@3024r
3072B	%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
	Not coalescable.
3088B	%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
	Not coalescable.
3136B	%vreg472:sub0<def,read-undef> = COPY %vreg476; VReg_64:%vreg472 VReg_32:%vreg476
	Considering merging to VReg_64 with %vreg476 in %vreg472:sub0
		RHS = %vreg476 [3104r,3136r:0)  0@3104r
		LHS = %vreg472 [3136r,3152r:1)[3152r,3232r:0)  0@3152r 1@3136r
		merge %vreg472:1@3136r into %vreg476:0@3104r --> @3104r
		erased:	3136r	%vreg472:sub0<def,read-undef> = COPY %vreg476; VReg_64:%vreg472 VReg_32:%vreg476
		updated: 3104B	%vreg472:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg472,%vreg468 VReg_32:%vreg558
	Joined. Result = %vreg472 [3104r,3152r:0)[3152r,3232r:1)  0@3104r 1@3152r
3152B	%vreg472:sub1<def> = COPY %vreg470; VReg_64:%vreg472 VReg_32:%vreg470
	Considering merging to VReg_64 with %vreg470 in %vreg472:sub1
		RHS = %vreg470 [3120r,3152r:0)  0@3120r
		LHS = %vreg472 [3104r,3152r:0)[3152r,3232r:1)  0@3104r 1@3152r
		merge %vreg472:1@3152r into %vreg470:0@3120r --> @3120r
		pruned %vreg472 at 3120r: %vreg472 [3104r,3120r:0)[3152r,3232r:1)  0@3104r 1@3152r
		erased:	3152r	%vreg472:sub1<def> = COPY %vreg470; VReg_64:%vreg472 VReg_32:%vreg470
		restoring liveness to 2 points: %vreg472 [3104r,3120r:0)[3120r,3232r:1)  0@3104r 1@3120r
		updated: 3120B	%vreg472:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg472,%vreg468 VReg_32:%vreg559
	Joined. Result = %vreg472 [3104r,3120r:0)[3120r,3232r:1)  0@3104r 1@3120r
3200B	%vreg303<def> = COPY %vreg366:sub0_sub1; SGPR_64:%vreg303 SReg_128:%vreg366
	Considering merging to SReg_128 with %vreg303 in %vreg366:sub0_sub1
		RHS = %vreg303 [3200r,3312r:0)  0@3200r
		LHS = %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
		merge %vreg303:0@3200r into %vreg366:0@3184r --> @3184r
		pruned %vreg303 at 3264r: %vreg303 [3200r,3264r:0)  0@3200r
		pruned %vreg303 at 3280r: %vreg303 [3200r,3264r:0)  0@3200r
		pruned all of %vreg303 at 3200r: %vreg303 EMPTY  0@3200r
		erased:	3200r	%vreg303<def> = COPY %vreg366:sub0_sub1; SGPR_64:%vreg303 SReg_128:%vreg366
		restoring liveness to 4 points: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
		updated: 3312B	%vreg857<def> = COPY %vreg366:sub0_sub1; SReg_64:%vreg857 SReg_128:%vreg366
	Joined. Result = %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
3216B	%vreg19<def> = COPY %vreg486; VReg_64:%vreg19,%vreg486
	Considering merging to VReg_64 with %vreg486 in %vreg19
		RHS = %vreg19 [3216r,3328r:0)  0@3216r
		LHS = %vreg486 [2752r,2768r:0)[2768r,3216r:1)  0@2752r 1@2768r
		merge %vreg19:0@3216r into %vreg486:1@2768r --> @2768r
		erased:	3216r	%vreg19<def> = COPY %vreg486; VReg_64:%vreg19,%vreg486
		updated: 3328B	%vreg858<def> = COPY %vreg486; VReg_64:%vreg858,%vreg486
	Joined. Result = %vreg486 [2752r,2768r:0)[2768r,3328r:1)  0@2752r 1@2768r
3232B	%vreg18<def> = COPY %vreg472; VReg_64:%vreg18,%vreg472
	Considering merging to VReg_64 with %vreg472 in %vreg18
		RHS = %vreg18 [3232r,3344r:0)  0@3232r
		LHS = %vreg472 [3104r,3120r:0)[3120r,3232r:1)  0@3104r 1@3120r
		merge %vreg18:0@3232r into %vreg472:1@3120r --> @3120r
		erased:	3232r	%vreg18<def> = COPY %vreg472; VReg_64:%vreg18,%vreg472
		updated: 3344B	%vreg859<def> = COPY %vreg472; VReg_64:%vreg859,%vreg472
	Joined. Result = %vreg472 [3104r,3120r:0)[3120r,3344r:1)  0@3104r 1@3120r
3296B	%vreg456<def> = COPY %vreg454; VReg_32:%vreg456,%vreg454
	Considering merging to VReg_32 with %vreg454 in %vreg456
		RHS = %vreg454 [3168r,3296r:0)  0@3168r
		LHS = %vreg456 [3296r,3360r:0)  0@3296r
		merge %vreg456:0@3296r into %vreg454:0@3168r --> @3168r
		erased:	3296r	%vreg456<def> = COPY %vreg454; VReg_32:%vreg456,%vreg454
		updated: 3168B	%vreg456<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg456 SGPR_32:%vreg55 VReg_64:%vreg459
	Joined. Result = %vreg456 [3168r,3360r:0)  0@3168r

***BUG BEGIN:

* We have a sequence like this:

BB#6:
  %vreg366:sub0_sub1 = S_MOV_B64 0 ; SReg_128:%vreg366
  %vreg857<def> = COPY %vreg366:sub0_sub1 ; SReg_64:%vreg847,SReg_128:%vreg366
  BRANCH BB#10

BB#10:

  %vreg857<def> = SI_IF_BREAK %vreg371, %vreg857 ; SReg_64: %vreg857, %vreg371
  SI_LOOP %vreg857, <BB#10> ; SReg_64:%vreg857  ; This is a conditional branch instruction
  BRANCH <BB#11>


* Then we perform a register coalesce with a rematerialization:

3312B	%vreg857<def> = COPY %vreg366:sub0_sub1; SReg_64:%vreg857 SReg_128:%vreg366
	Considering merging to SReg_128 with %vreg857 in %vreg366:sub0_sub1
		RHS = %vreg857 [3312r,3408B:0)[9872B,10384r:1)[10384r,10608r:2)  0@3312r 1@9872B-phi 2@10384r
		LHS = %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
		merge %vreg857:0@3312r into %vreg366:3@3280r --> @3280r
		merge %vreg857:1@9872B into %vreg366:1@9872B --> @9872B
		interference at %vreg857:2@10384r
  %vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
		updated: 3312B	%vreg857:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg857
		updated: 10384B	%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371, %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
		updated: 10608B	SI_END_CF %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
		updated: 10560B	SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
Remat: %vreg857:sub3<def,read-undef> = S_MOV_B32 61440; SReg_128:%vreg857
Shrink: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
Shrunk: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r

* The problem now is that the second operand of SI_IF_BREAK
  %vreg857:sub0_sub1 is undefined on the first iteration of the loop.
  In the process of coalescing we seem to have lost this definition.
  %vreg857<def> = COPY %vreg366:sub0_sub1 has disappeared and
  %vreg857:sub3<def,read-undef> = S_MOV_B32 61440; SReg_128:%vreg857 has been
  added.

***BUG END


3328B	%vreg858<def> = COPY %vreg486; VReg_64:%vreg858,%vreg486
	Considering merging to VReg_64 with %vreg486 in %vreg858
		RHS = %vreg486 [2752r,2768r:0)[2768r,3328r:1)  0@2752r 1@2768r
		LHS = %vreg858 [3328r,3408B:0)[9872B,10304r:2)[10496r,10592B:1)  0@3328r 1@10496r 2@9872B-phi
		merge %vreg858:0@3328r into %vreg486:1@2768r --> @2768r
		erased:	3328r	%vreg858<def> = COPY %vreg486; VReg_64:%vreg858,%vreg486
		updated: 2768B	%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
		updated: 2752B	%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
	Joined. Result = %vreg858 [2752r,2768r:0)[2768r,3408B:1)[9872B,10304r:3)[10496r,10592B:2)  0@2752r 1@2768r 2@10496r 3@9872B-phi
3344B	%vreg859<def> = COPY %vreg472; VReg_64:%vreg859,%vreg472
	Considering merging to VReg_64 with %vreg472 in %vreg859
		RHS = %vreg472 [3104r,3120r:0)[3120r,3344r:1)  0@3104r 1@3120r
		LHS = %vreg859 [3344r,3408B:0)[9872B,10288r:2)[10512r,10592B:1)  0@3344r 1@10512r 2@9872B-phi
		merge %vreg859:0@3344r into %vreg472:1@3120r --> @3120r
		erased:	3344r	%vreg859<def> = COPY %vreg472; VReg_64:%vreg859,%vreg472
		updated: 3120B	%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
		updated: 3104B	%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
	Joined. Result = %vreg859 [3104r,3120r:0)[3120r,3408B:1)[9872B,10288r:3)[10512r,10592B:2)  0@3104r 1@3120r 2@10512r 3@9872B-phi
3360B	%vreg860<def> = COPY %vreg456; VReg_32:%vreg860,%vreg456
	Considering merging to VReg_32 with %vreg456 in %vreg860
		RHS = %vreg456 [3168r,3360r:0)  0@3168r
		LHS = %vreg860 [3360r,3408B:0)[9872B,10352r:1)[10352r,10592B:2)  0@3360r 1@9872B-phi 2@10352r
		merge %vreg860:0@3360r into %vreg456:0@3168r --> @3168r
		erased:	3360r	%vreg860<def> = COPY %vreg456; VReg_32:%vreg860,%vreg456
		updated: 3168B	%vreg860<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
	Joined. Result = %vreg860 [3168r,3408B:0)[9872B,10352r:1)[10352r,10592B:2)  0@3168r 1@9872B-phi 2@10352r
3376B	%vreg861<def> = COPY %vreg856; VGPR_32:%vreg861,%vreg856
	Considering merging to VGPR_32 with %vreg856 in %vreg861
		RHS = %vreg861 [3376r,3408B:0)[9872B,10336r:1)[10336r,10624r:2)  0@3376r 1@9872B-phi 2@10336r
		LHS = %vreg856 [752r,864B:3)[1664r,2096B:5)[2096B,2224B:4)[2272B,3376r:0)[3408B,3552B:0)[3552B,9280r:6)[9280r,9808B:4)[9808B,9872B:2)[10624r,10656B:1)[10656B,10912r:2)  0@3408B-phi 1@10624r 2@9808B-phi 3@752r 4@9280r 5@1664r 6@3552B-phi
		merge %vreg856:1@10624r into %vreg861:2@10336r --> @10336r
		merge %vreg861:0@3376r into %vreg856:0@3408B --> @3408B
		erased:	10624r	%vreg856<def> = COPY %vreg861; VGPR_32:%vreg856,%vreg861
		erased:	3376r	%vreg861<def> = COPY %vreg856; VGPR_32:%vreg861,%vreg856
		updated: 10336B	%vreg856<def> = V_MAD_F32 %vreg369, %vreg369, %vreg856, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
	Joined. Result = %vreg856 [752r,864B:3)[1664r,2096B:5)[2096B,2224B:4)[2272B,3552B:0)[3552B,9280r:6)[9280r,9808B:4)[9808B,9872B:2)[9872B,10336r:7)[10336r,10656B:1)[10656B,10912r:2)  0@3408B-phi 1@10336r 2@9808B-phi 3@752r 4@9280r 5@1664r 6@3552B-phi 7@9872B-phi
Flow45:
if.then51:
11168B	%vreg415:sub0<def,read-undef> = COPY %vreg417; SGPR_64:%vreg415 SGPR_32:%vreg417
	Considering merging to SGPR_64 with %vreg417 in %vreg415:sub0
		RHS = %vreg417 [11136r,11168r:0)  0@11136r
		LHS = %vreg415 [11168r,11184r:1)[11184r,11216r:0)  0@11184r 1@11168r
		merge %vreg415:1@11168r into %vreg417:0@11136r --> @11136r
		erased:	11168r	%vreg415:sub0<def,read-undef> = COPY %vreg417; SGPR_64:%vreg415 SGPR_32:%vreg417
		updated: 11136B	%vreg415:sub0<def,read-undef> = S_MOV_B32 0; SGPR_64:%vreg415
	Joined. Result = %vreg415 [11136r,11184r:0)[11184r,11216r:1)  0@11136r 1@11184r
11184B	%vreg415:sub1<def> = COPY %vreg416; SGPR_64:%vreg415 SGPR_32:%vreg416
	Considering merging to SGPR_64 with %vreg416 in %vreg415:sub1
		RHS = %vreg416 [11152r,11184r:0)  0@11152r
		LHS = %vreg415 [11136r,11184r:0)[11184r,11216r:1)  0@11136r 1@11184r
		merge %vreg415:1@11184r into %vreg416:0@11152r --> @11152r
		pruned %vreg415 at 11152r: %vreg415 [11136r,11152r:0)[11184r,11216r:1)  0@11136r 1@11184r
		erased:	11184r	%vreg415:sub1<def> = COPY %vreg416; SGPR_64:%vreg415 SGPR_32:%vreg416
		restoring liveness to 2 points: %vreg415 [11136r,11152r:0)[11152r,11216r:1)  0@11136r 1@11152r
		updated: 11152B	%vreg415:sub1<def> = S_MOV_B32 61440; SGPR_64:%vreg415
	Joined. Result = %vreg415 [11136r,11152r:0)[11152r,11216r:1)  0@11136r 1@11152r
11200B	%vreg396:sub0_sub1<def,read-undef> = COPY %vreg414; SReg_128:%vreg396 SGPR_64:%vreg414
	Considering merging to SReg_128 with %vreg414 in %vreg396:sub0_sub1
		RHS = %vreg414 [11120r,11200r:0)  0@11120r
		LHS = %vreg396 [11200r,11216r:1)[11216r,11248r:0)  0@11216r 1@11200r
		merge %vreg396:1@11200r into %vreg414:0@11120r --> @11120r
		erased:	11200r	%vreg396:sub0_sub1<def,read-undef> = COPY %vreg414; SReg_128:%vreg396 SGPR_64:%vreg414
		updated: 11120B	%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
	Joined. Result = %vreg396 [11120r,11216r:0)[11216r,11248r:1)  0@11120r 1@11216r
11216B	%vreg396:sub2_sub3<def> = COPY %vreg415; SReg_128:%vreg396 SGPR_64:%vreg415
	Considering merging to SReg_128 with %vreg415 in %vreg396:sub2_sub3
		RHS = %vreg415 [11136r,11152r:0)[11152r,11216r:1)  0@11136r 1@11152r
		LHS = %vreg396 [11120r,11216r:0)[11216r,11248r:1)  0@11120r 1@11216r
		merge %vreg396:1@11216r into %vreg415:1@11152r --> @11152r
		pruned %vreg396 at 11136r: %vreg396 [11120r,11136r:0)[11216r,11248r:1)  0@11120r 1@11216r
		pruned %vreg396 at 11152r: %vreg396 [11120r,11136r:0)[11216r,11248r:1)  0@11120r 1@11216r
		erased:	11216r	%vreg396:sub2_sub3<def> = COPY %vreg415; SReg_128:%vreg396 SGPR_64:%vreg415
		restoring liveness to 3 points: %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
		updated: 11152B	%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
		updated: 11136B	%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
	Joined. Result = %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
if.else:
11296B	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
	Considering merging to VGPR_32 with %vreg388 in %vreg44
		RHS = %vreg44 [11296r,11424r:0)  0@11296r
		LHS = %vreg388 [10912r,11040B:0)[11280B,11296r:0)  0@10912r
		merge %vreg44:0@11296r into %vreg388:0@10912r --> @10912r
		erased:	11296r	%vreg44<def> = COPY %vreg388; VGPR_32:%vreg44,%vreg388
		updated: 11424B	BUFFER_STORE_DWORD %vreg388, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
	Joined. Result = %vreg388 [10912r,11040B:0)[11280B,11424r:0)  0@10912r
11360B	%vreg419:sub0<def,read-undef> = COPY %vreg421; SGPR_64:%vreg419 SGPR_32:%vreg421
	Considering merging to SGPR_64 with %vreg421 in %vreg419:sub0
		RHS = %vreg421 [11328r,11360r:0)  0@11328r
		LHS = %vreg419 [11360r,11376r:1)[11376r,11408r:0)  0@11376r 1@11360r
		merge %vreg419:1@11360r into %vreg421:0@11328r --> @11328r
		erased:	11360r	%vreg419:sub0<def,read-undef> = COPY %vreg421; SGPR_64:%vreg419 SGPR_32:%vreg421
		updated: 11328B	%vreg419:sub0<def,read-undef> = S_MOV_B32 0; SGPR_64:%vreg419
	Joined. Result = %vreg419 [11328r,11376r:0)[11376r,11408r:1)  0@11328r 1@11376r
11376B	%vreg419:sub1<def> = COPY %vreg420; SGPR_64:%vreg419 SGPR_32:%vreg420
	Considering merging to SGPR_64 with %vreg420 in %vreg419:sub1
		RHS = %vreg420 [11344r,11376r:0)  0@11344r
		LHS = %vreg419 [11328r,11376r:0)[11376r,11408r:1)  0@11328r 1@11376r
		merge %vreg419:1@11376r into %vreg420:0@11344r --> @11344r
		pruned %vreg419 at 11344r: %vreg419 [11328r,11344r:0)[11376r,11408r:1)  0@11328r 1@11376r
		erased:	11376r	%vreg419:sub1<def> = COPY %vreg420; SGPR_64:%vreg419 SGPR_32:%vreg420
		restoring liveness to 2 points: %vreg419 [11328r,11344r:0)[11344r,11408r:1)  0@11328r 1@11344r
		updated: 11344B	%vreg419:sub1<def> = S_MOV_B32 61440; SGPR_64:%vreg419
	Joined. Result = %vreg419 [11328r,11344r:0)[11344r,11408r:1)  0@11328r 1@11344r
11392B	%vreg394:sub0_sub1<def,read-undef> = COPY %vreg418; SReg_128:%vreg394 SGPR_64:%vreg418
	Considering merging to SReg_128 with %vreg418 in %vreg394:sub0_sub1
		RHS = %vreg418 [11312r,11392r:0)  0@11312r
		LHS = %vreg394 [11392r,11408r:1)[11408r,11424r:0)  0@11408r 1@11392r
		merge %vreg394:1@11392r into %vreg418:0@11312r --> @11312r
		erased:	11392r	%vreg394:sub0_sub1<def,read-undef> = COPY %vreg418; SReg_128:%vreg394 SGPR_64:%vreg418
		updated: 11312B	%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
	Joined. Result = %vreg394 [11312r,11408r:0)[11408r,11424r:1)  0@11312r 1@11408r
11408B	%vreg394:sub2_sub3<def> = COPY %vreg419; SReg_128:%vreg394 SGPR_64:%vreg419
	Considering merging to SReg_128 with %vreg419 in %vreg394:sub2_sub3
		RHS = %vreg419 [11328r,11344r:0)[11344r,11408r:1)  0@11328r 1@11344r
		LHS = %vreg394 [11312r,11408r:0)[11408r,11424r:1)  0@11312r 1@11408r
		merge %vreg394:1@11408r into %vreg419:1@11344r --> @11344r
		pruned %vreg394 at 11328r: %vreg394 [11312r,11328r:0)[11408r,11424r:1)  0@11312r 1@11408r
		pruned %vreg394 at 11344r: %vreg394 [11312r,11328r:0)[11408r,11424r:1)  0@11312r 1@11408r
		erased:	11408r	%vreg394:sub2_sub3<def> = COPY %vreg419; SReg_128:%vreg394 SGPR_64:%vreg419
		restoring liveness to 3 points: %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
		updated: 11344B	%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
		updated: 11328B	%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
	Joined. Result = %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
if.end58:
4960B	%vreg195:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg195,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg195
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
		interference at %vreg195:0@1856r
	Interference!
5472B	%vreg203:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg203,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg203
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
		interference at %vreg203:0@1872r
	Interference!
5984B	%vreg211:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg211,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg211
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
		interference at %vreg211:0@1888r
	Interference!
6496B	%vreg219:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg219,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg219
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
		interference at %vreg219:0@1904r
	Interference!
7008B	%vreg227:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg227,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg227
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
		interference at %vreg227:0@1920r
	Interference!
7520B	%vreg235:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg235,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg235
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
		interference at %vreg235:0@1936r
	Interference!
8032B	%vreg243:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg243,%vreg183
	Considering merging to SGPR_64 with %vreg183 in %vreg243
		RHS = %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
		LHS = %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
		interference at %vreg243:0@1952r
	Interference!
10496B	%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
	Considering merging to VReg_64 with %vreg830 in %vreg858
		RHS = %vreg830 [10032r,10064r:0)[10064r,10496r:1)  0@10032r 1@10064r
		LHS = %vreg858 [2752r,2768r:0)[2768r,3408B:1)[9872B,10304r:3)[10496r,10592B:2)  0@2752r 1@2768r 2@10496r 3@9872B-phi
		merge %vreg858:2@10496r into %vreg830:1@10064r --> @10064r
		conflict at %vreg830:0@10032r
		taints local %vreg858:3@9872B to 10304r
		tainted lanes used by: %vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
  %vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
Checking if cheap as move
	Interference!
10512B	%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
	Considering merging to VReg_64 with %vreg839 in %vreg859
		RHS = %vreg839 [10144r,10176r:0)[10176r,10512r:1)  0@10144r 1@10176r
		LHS = %vreg859 [3104r,3120r:0)[3120r,3408B:1)[9872B,10288r:3)[10512r,10592B:2)  0@3104r 1@3120r 2@10512r 3@9872B-phi
		merge %vreg859:2@10512r into %vreg839:1@10176r --> @10176r
		conflict at %vreg839:0@10144r
		taints local %vreg859:3@9872B to 10288r
		tainted lanes used by: %vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
  %vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
Checking if cheap as move
	Interference!
Trying to inflate 0 regs.
********** INTERVALS **********
SGPR0 [0B,80r:0)  0@0B-phi
SGPR1 [0B,80r:0)  0@0B-phi
SGPR2 [0B,16r:0)  0@0B-phi
SGPR3 [0B,48r:0)  0@0B-phi
VGPR0 [0B,32r:0)  0@0B-phi
VGPR1 [0B,64r:0)  0@0B-phi
%vreg0 [16r,2224B:0)[2272B,2816r:0)[3408B,9808B:0)  0@16r
%vreg1 [112r,2224B:0)[2272B,2832r:0)[3408B,9808B:0)  0@112r
%vreg4 [48r,2224B:0)[2272B,2384r:0)[3408B,9808B:0)  0@48r
%vreg5 [224r,2224B:0)[2272B,2400r:0)[3408B,9808B:0)  0@224r
%vreg9 [688r,2096B:0)[3552B,9808B:0)  0@688r
%vreg13 [2144r,2160r:0)  0@2144r
%vreg45 [10848r,10864r:0)[10864r,11248r:1)[11280B,11456B:1)  0@10848r 1@10864r
%vreg48 [80r,448r:0)  0@80r
%vreg49 [448r,2224B:0)[2272B,2736r:0)[3408B,9808B:0)  0@448r
%vreg50 [432r,2224B:0)[2272B,2432r:0)[3408B,9808B:0)  0@432r
%vreg51 [416r,2224B:0)[2272B,3088r:0)[3408B,9808B:0)  0@416r
%vreg52 [400r,2224B:0)[2272B,2864r:0)[3408B,9808B:0)  0@400r
%vreg53 [384r,2224B:0)[2272B,10832r:0)  0@384r
%vreg54 [368r,2224B:0)[2272B,10672r:0)  0@368r
%vreg55 [352r,2224B:0)[2272B,3168r:0)[3408B,9808B:0)  0@352r
%vreg56 [2272B,3408B:0)[3456r,3552B:0)[9808B,10912r:0)  0@3456r
%vreg61 [96r,128r:0)  0@96r
%vreg63 [128r,144r:0)  0@128r
%vreg66 [160r,176r:0)  0@160r
%vreg67 [176r,192r:0)  0@176r
%vreg68 [192r,320r:0)  0@192r
%vreg69 [208r,240r:0)  0@208r
%vreg71 [240r,256r:0)  0@240r
%vreg74 [272r,288r:0)  0@272r
%vreg75 [288r,304r:0)  0@288r
%vreg76 [304r,320r:0)  0@304r
%vreg77 [320r,464r:0)  0@320r
%vreg78 [336r,2224B:0)[3408B,3456r:0)[3552B,9808B:0)  0@336r
%vreg86 [464r,2240r:0)[2272B,11504B:0)  0@464r
%vreg89 [704r,832r:0)  0@704r
%vreg92 [832r,2224B:0)[3408B,3504r:0)[3552B,9808B:0)  0@832r
%vreg96 [880r,896r:0)  0@880r
%vreg97 [896r,912r:0)  0@896r
%vreg104 [928r,944r:0)[944r,992r:1)  0@928r 1@944r
%vreg116 [1168r,1600r:0)  0@1168r
%vreg122 [1296r,1312r:0)  0@1296r
%vreg123 [1312r,1328r:0)  0@1312r
%vreg130 [1344r,1360r:0)[1360r,1408r:1)  0@1344r 1@1360r
%vreg149 [3712r,3744r:0)  0@3712r
%vreg150 [3728r,3744r:0)  0@3728r
%vreg151 [3744r,3760r:0)  0@3744r
%vreg153 [3776r,3808r:0)  0@3776r
%vreg154 [3792r,3808r:0)  0@3792r
%vreg155 [3808r,3824r:0)  0@3808r
%vreg157 [3840r,3872r:0)  0@3840r
%vreg158 [3856r,3872r:0)  0@3856r
%vreg159 [3872r,3888r:0)  0@3872r
%vreg161 [3904r,3936r:0)  0@3904r
%vreg162 [3920r,3936r:0)  0@3920r
%vreg163 [3936r,3952r:0)  0@3936r
%vreg165 [3968r,4000r:0)  0@3968r
%vreg166 [3984r,4000r:0)  0@3984r
%vreg167 [4000r,4016r:0)  0@4000r
%vreg169 [4032r,4064r:0)  0@4032r
%vreg170 [4048r,4064r:0)  0@4048r
%vreg171 [4064r,4080r:0)  0@4064r
%vreg173 [4096r,4128r:0)  0@4096r
%vreg174 [4112r,4128r:0)  0@4112r
%vreg175 [4128r,4144r:0)  0@4128r
%vreg177 [4160r,4192r:0)  0@4160r
%vreg178 [4176r,4192r:0)  0@4176r
%vreg179 [4192r,4208r:0)  0@4192r
%vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
%vreg186 [4592r,4912r:0)  0@4592r
%vreg190 [4896r,4912r:0)  0@4896r
%vreg192 [4912r,4928r:0)  0@4912r
%vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
%vreg196 [5184r,5424r:0)  0@5184r
%vreg198 [5408r,5424r:0)  0@5408r
%vreg200 [5424r,5440r:0)  0@5424r
%vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
%vreg204 [5696r,5936r:0)  0@5696r
%vreg206 [5920r,5936r:0)  0@5920r
%vreg208 [5936r,5952r:0)  0@5936r
%vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
%vreg212 [6208r,6448r:0)  0@6208r
%vreg214 [6432r,6448r:0)  0@6432r
%vreg216 [6448r,6464r:0)  0@6448r
%vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
%vreg220 [6720r,6960r:0)  0@6720r
%vreg222 [6944r,6960r:0)  0@6944r
%vreg224 [6960r,6976r:0)  0@6960r
%vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
%vreg228 [7232r,7472r:0)  0@7232r
%vreg230 [7456r,7472r:0)  0@7456r
%vreg232 [7472r,7488r:0)  0@7472r
%vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
%vreg236 [7744r,7984r:0)  0@7744r
%vreg238 [7968r,7984r:0)  0@7968r
%vreg240 [7984r,8000r:0)  0@7984r
%vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
%vreg244 [8256r,8496r:0)  0@8256r
%vreg246 [8480r,8496r:0)  0@8480r
%vreg248 [8496r,8512r:0)  0@8496r
%vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9264r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
%vreg253 [8816r,8848r:0)  0@8816r
%vreg255 [8848r,8880r:0)  0@8848r
%vreg257 [8880r,8912r:0)  0@8880r
%vreg259 [8912r,8944r:0)  0@8912r
%vreg261 [8944r,8976r:0)  0@8944r
%vreg263 [8976r,9008r:0)  0@8976r
%vreg265 [9008r,9040r:0)  0@9008r
%vreg267 [9040r,9072r:0)  0@9040r
%vreg269 [9072r,9104r:0)  0@9072r
%vreg271 [9104r,9136r:0)  0@9104r
%vreg273 [9136r,9168r:0)  0@9136r
%vreg275 [9168r,9200r:0)  0@9168r
%vreg277 [9200r,9232r:0)  0@9200r
%vreg279 [9232r,9264r:0)  0@9232r
%vreg281 [9264r,9280r:0)  0@9264r
%vreg283 [1968r,2096B:0)[3552B,9808B:0)  0@1968r
%vreg296 [9552r,9584r:0)  0@9552r
%vreg297 [9584r,9600r:0)  0@9584r
%vreg299 [2128r,2144r:0)  0@2128r
%vreg300 [2288r,2304r:0)  0@2288r
%vreg301 [2304r,2336r:0)  0@2304r
%vreg302 [2336r,3408B:0)[9808B,9840r:0)[9872B,10656B:0)  0@2336r
%vreg304 [2384r,2400r:0)  0@2384r
%vreg305 [2400r,2416r:0)  0@2400r
%vreg312 [2432r,2448r:0)[2448r,2624r:1)  0@2432r 1@2448r
%vreg330 [2816r,2832r:0)  0@2816r
%vreg331 [2832r,2848r:0)  0@2832r
%vreg338 [2864r,2880r:0)[2880r,2976r:1)  0@2864r 1@2880r
%vreg353 [3248r,3408B:0)[9872B,10592B:0)  0@3248r
%vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
%vreg367 [10288r,10320r:0)  0@10288r
%vreg368 [10304r,10320r:0)  0@10304r
%vreg369 [10320r,10336r:0)  0@10320r
%vreg371 [10368r,10384r:0)  0@10368r
%vreg373 [10672r,10688r:0)  0@10672r
%vreg374 [10688r,10704r:0)  0@10688r
%vreg388 [10912r,11040B:0)[11280B,11424r:0)  0@10912r
%vreg389 [10928r,10944r:0)  0@10928r
%vreg390 [10944r,10976r:0)  0@10944r
%vreg391 [10960r,10976r:0)  0@10960r
%vreg392 [10976r,11008r:0)  0@10976r
%vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
%vreg395 [11008r,11072r:0)[11072r,11280B:1)[11280B,11456B:0)[11456B,11472r:1)  0@11008r 1@11072r
%vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
%vreg397 [11232r,11248r:0)  0@11232r
%vreg423 [144r,2224B:0)[2272B,10704r:0)  0@144r
%vreg425 [10704r,10720r:0)[10720r,10768r:1)  0@10704r 1@10720r
%vreg428 [10768r,10864r:0)  0@10768r
%vreg440 [256r,2224B:0)[2272B,10688r:0)  0@256r
%vreg442 [64r,2224B:0)[2272B,2416r:0)[3408B,9808B:0)  0@64r
%vreg443 [912r,928r:0)  0@912r
%vreg444 [2416r,2432r:0)  0@2416r
%vreg445 [32r,2224B:0)[2272B,2848r:0)[3408B,9808B:0)  0@32r
%vreg446 [1328r,1344r:0)  0@1328r
%vreg447 [2848r,2864r:0)  0@2848r
%vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2528r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2528r 2@720r 3@2160r
%vreg465 [2960r,2976r:0)[2976r,3024r:1)  0@2960r 1@2976r
%vreg468 [3024r,3120r:0)  0@3024r
%vreg479 [2608r,2624r:0)[2624r,2672r:1)  0@2608r 1@2624r
%vreg482 [2672r,2768r:0)  0@2672r
%vreg499 [992r,1088r:0)  0@992r
%vreg503 [1072r,1088r:0)[1088r,1248r:1)  0@1072r 1@1088r
%vreg508 [1232r,1248r:0)  0@1232r
%vreg516 [1040r,1072r:0)  0@1040r
%vreg517 [1056r,1088r:0)  0@1056r
%vreg522 [1408r,1504r:0)  0@1408r
%vreg526 [1488r,1504r:0)[1504r,1616r:1)  0@1488r 1@1504r
%vreg531 [1600r,1616r:0)  0@1600r
%vreg539 [1456r,1488r:0)  0@1456r
%vreg540 [1472r,1504r:0)  0@1472r
%vreg551 [2720r,2752r:0)  0@2720r
%vreg552 [2736r,2768r:0)  0@2736r
%vreg558 [3072r,3104r:0)  0@3072r
%vreg559 [3088r,3120r:0)  0@3088r
%vreg562 [1584r,1616r:2)[1616r,2096B:3)[3552B,4288r:0)[4288r,9472r:1)[9472r,9504r:4)[9504r,9808B:5)  0@3552B-phi 1@4288r 2@1584r 3@1616r 4@9472r 5@9504r
%vreg567 [8192r,8208r:0)[8208r,8256r:1)  0@8192r 1@8208r
%vreg578 [8048r,8208r:0)  0@8048r
%vreg582 [7680r,7696r:0)[7696r,7744r:1)  0@7680r 1@7696r
%vreg593 [7536r,7696r:0)  0@7536r
%vreg597 [7168r,7184r:0)[7184r,7232r:1)  0@7168r 1@7184r
%vreg608 [7024r,7184r:0)  0@7024r
%vreg612 [6656r,6672r:0)[6672r,6720r:1)  0@6656r 1@6672r
%vreg623 [6512r,6672r:0)  0@6512r
%vreg627 [6144r,6160r:0)[6160r,6208r:1)  0@6144r 1@6160r
%vreg638 [6000r,6160r:0)  0@6000r
%vreg642 [5632r,5648r:0)[5648r,5696r:1)  0@5632r 1@5648r
%vreg653 [5488r,5648r:0)  0@5488r
%vreg657 [5120r,5136r:0)[5136r,5184r:1)  0@5120r 1@5136r
%vreg668 [4976r,5136r:0)  0@4976r
%vreg672 [4480r,4496r:0)[4496r,4592r:1)  0@4480r 1@4496r
%vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
%vreg683 [4336r,4496r:0)  0@4336r
%vreg687 [1216r,1248r:2)[1248r,2096B:3)[3552B,4640r:0)[4640r,9360r:1)[9360r,9392r:4)[9392r,9808B:5)  0@3552B-phi 1@4640r 2@1216r 3@1248r 4@9360r 5@9392r
%vreg692 [8416r,8432r:0)[8432r,8480r:1)  0@8416r 1@8432r
%vreg703 [8272r,8432r:0)  0@8272r
%vreg707 [7904r,7920r:0)[7920r,7968r:1)  0@7904r 1@7920r
%vreg718 [7760r,7920r:0)  0@7760r
%vreg722 [7392r,7408r:0)[7408r,7456r:1)  0@7392r 1@7408r
%vreg733 [7248r,7408r:0)  0@7248r
%vreg737 [6880r,6896r:0)[6896r,6944r:1)  0@6880r 1@6896r
%vreg748 [6736r,6896r:0)  0@6736r
%vreg752 [6368r,6384r:0)[6384r,6432r:1)  0@6368r 1@6384r
%vreg763 [6224r,6384r:0)  0@6224r
%vreg767 [5856r,5872r:0)[5872r,5920r:1)  0@5856r 1@5872r
%vreg778 [5712r,5872r:0)  0@5712r
%vreg782 [5344r,5360r:0)[5360r,5408r:1)  0@5344r 1@5360r
%vreg793 [5200r,5360r:0)  0@5200r
%vreg797 [4832r,4848r:0)[4848r,4896r:1)  0@4832r 1@4848r
%vreg808 [4688r,4848r:0)  0@4688r
%vreg818 [9376r,9392r:0)  0@9376r
%vreg827 [9488r,9504r:0)  0@9488r
%vreg830 [10032r,10064r:0)[10064r,10496r:1)  0@10032r 1@10064r
%vreg836 [10048r,10064r:0)  0@10048r
%vreg839 [10144r,10176r:0)[10176r,10512r:1)  0@10144r 1@10176r
%vreg845 [10160r,10176r:0)  0@10160r
%vreg847 [10816r,10848r:0)  0@10816r
%vreg848 [10832r,10864r:0)  0@10832r
%vreg851 [2000r,2096B:0)[2096B,2112r:2)[3552B,9600r:1)[9600r,9808B:2)  0@2000r 1@3552B-phi 2@9600r
%vreg854 [1696r,2096B:0)[3552B,9568r:1)[9568r,9808B:2)  0@1696r 1@3552B-phi 2@9568r
%vreg856 [752r,864B:3)[1664r,2096B:5)[2096B,2224B:4)[2272B,3552B:0)[3552B,9280r:6)[9280r,9808B:4)[9808B,9872B:2)[9872B,10336r:7)[10336r,10656B:1)[10656B,10912r:2)  0@3408B-phi 1@10336r 2@9808B-phi 3@752r 4@9280r 5@1664r 6@3552B-phi 7@9872B-phi
%vreg857 [3312r,3408B:0)[9872B,10384r:1)[10384r,10608r:2)  0@3312r 1@9872B-phi 2@10384r
%vreg858 [2752r,2768r:0)[2768r,3408B:1)[9872B,10304r:3)[10496r,10592B:2)  0@2752r 1@2768r 2@10496r 3@9872B-phi
%vreg859 [3104r,3120r:0)[3120r,3408B:1)[9872B,10288r:3)[10512r,10592B:2)  0@3104r 1@3120r 2@10512r 3@9872B-phi
%vreg860 [3168r,3408B:0)[9872B,10352r:1)[10352r,10592B:2)  0@3168r 1@9872B-phi 2@10352r
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
32B		%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
48B		%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
64B		%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
112B		%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
224B		%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
368B		%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
384B		%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
400B		%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
416B		%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
432B		%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
448B		%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9 SGPR_32:%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
752B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SGPR_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
944B		%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_64:%vreg104
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
1072B		%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
1088B		%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
1168B		%vreg116<def> = S_MOV_B64 32; SGPR_64:%vreg116
1216B		%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
1232B		%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
1248B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SGPR_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_64:%vreg130
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
1488B		%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
1504B		%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
1584B		%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
1600B		%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
1616B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
1664B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
1696B		%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
1728B		%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
1792B		%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
1808B		%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
1824B		%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
1840B		%vreg183:sub0<def> = S_MOV_B32 -4; SGPR_64:%vreg183
1856B		%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
1872B		%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
1888B		%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
1904B		%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
1920B		%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
1936B		%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
1952B		%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
1968B		%vreg283<def> = S_MOV_B64 64; SGPR_64:%vreg283
2000B		%vreg851:sub3<def,read-undef> = S_MOV_B32 61440; SReg_128:%vreg851
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299 SGPR_32:%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg459:sub0<def,read-undef> = COPY %vreg13; VReg_64:%vreg459 SReg_32:%vreg13
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SGPR_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_64:%vreg312
2528B		%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_64:%vreg459
2608B		%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
2624B		%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
2752B		%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
2768B		%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SGPR_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_64:%vreg338
2960B		%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
2976B		%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
3104B		%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
3120B		%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
3168B		%vreg860<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
3184B		%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
3248B		%vreg353<def> = S_MOV_B64 4; SGPR_64:%vreg353
3264B		%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
3280B		%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
3312B		%vreg857:sub3<def,read-undef> = S_MOV_B32 61440; SReg_128:%vreg857
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg250:sub14<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg250:sub13<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg250:sub12<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg250:sub11<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg250:sub10<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg250:sub9<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg250:sub8<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
4288B		%vreg562:sub2_sub3<def> = COPY %vreg676:sub2_sub3; VReg_128:%vreg562 SReg_128:%vreg676
4336B		%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
4480B		%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4496B		%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4640B		%vreg687:sub2_sub3<def> = COPY %vreg676:sub2_sub3; VReg_128:%vreg687 SReg_128:%vreg676
4688B		%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
4832B		%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4848B		%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg250:sub7<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
4960B		%vreg195:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg195,%vreg183
4976B		%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
5120B		%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5136B		%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
5344B		%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5360B		%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg250:sub6<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
5472B		%vreg203:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg203,%vreg183
5488B		%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
5632B		%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5648B		%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
5856B		%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5872B		%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg250:sub5<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
5984B		%vreg211:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg211,%vreg183
6000B		%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
6144B		%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6160B		%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
6368B		%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6384B		%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg250:sub4<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
6496B		%vreg219:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg219,%vreg183
6512B		%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
6656B		%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6672B		%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
6880B		%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6896B		%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg250:sub3<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
7008B		%vreg227:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg227,%vreg183
7024B		%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
7168B		%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7184B		%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
7392B		%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7408B		%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg250:sub2<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
7520B		%vreg235:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg235,%vreg183
7536B		%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
7680B		%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7696B		%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
7904B		%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7920B		%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg250:sub1<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
8032B		%vreg243:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg243,%vreg183
8048B		%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
8192B		%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8208B		%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
8416B		%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8432B		%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg250:sub0<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
9280B		%vreg856<def> = V_ADD_F32_e32 %vreg856, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
9360B		%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
9376B		%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
9392B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
9472B		%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
9488B		%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
9504B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg854<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
9600B		%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297, %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
9776B		SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
10032B		%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
10048B		%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
10064B		%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
10144B		%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
10160B		%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
10176B		%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg856<def> = V_MAD_F32 %vreg369, %vreg369, %vreg856, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
10352B		%vreg860<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
10384B		%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371, %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
10496B		%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
10512B		%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
10560B		SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SGPR_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
10720B		%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_64:%vreg425
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
10848B		%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
10864B		%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg856, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
11008B		%vreg395<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
11136B		%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
11152B		%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11312B		%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
11328B		%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
11344B		%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
11424B		BUFFER_STORE_DWORD %vreg388, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before SI Fix Extra Moves ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
32B		%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
48B		%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
64B		%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
112B		%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
224B		%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
368B		%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
384B		%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
400B		%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
416B		%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
432B		%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
448B		%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9 SGPR_32:%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
752B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SGPR_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
944B		%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_64:%vreg104
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
1072B		%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
1088B		%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
1168B		%vreg116<def> = S_MOV_B64 32; SGPR_64:%vreg116
1216B		%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
1232B		%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
1248B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SGPR_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_64:%vreg130
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
1488B		%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
1504B		%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
1584B		%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
1600B		%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
1616B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
1664B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
1696B		%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
1728B		%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
1792B		%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
1808B		%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
1824B		%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
1840B		%vreg183:sub0<def> = S_MOV_B32 -4; SGPR_64:%vreg183
1856B		%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
1872B		%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
1888B		%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
1904B		%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
1920B		%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
1936B		%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
1952B		%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
1968B		%vreg283<def> = S_MOV_B64 64; SGPR_64:%vreg283
2000B		%vreg851:sub3<def,read-undef> = S_MOV_B32 61440; SReg_128:%vreg851
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299 SGPR_32:%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg459:sub0<def,read-undef> = COPY %vreg13; VReg_64:%vreg459 SReg_32:%vreg13
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SGPR_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_64:%vreg312
2528B		%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_64:%vreg459
2608B		%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
2624B		%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
2752B		%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
2768B		%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SGPR_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_64:%vreg338
2960B		%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
2976B		%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
3104B		%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
3120B		%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
3168B		%vreg860<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
3184B		%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
3248B		%vreg353<def> = S_MOV_B64 4; SGPR_64:%vreg353
3264B		%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
3280B		%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
3312B		%vreg857:sub3<def,read-undef> = S_MOV_B32 61440; SReg_128:%vreg857
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg250:sub14<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg250:sub13<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg250:sub12<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg250:sub11<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg250:sub10<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg250:sub9<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg250:sub8<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
4288B		%vreg562:sub2_sub3<def> = COPY %vreg676:sub2_sub3; VReg_128:%vreg562 SReg_128:%vreg676
4336B		%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
4480B		%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4496B		%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4640B		%vreg687:sub2_sub3<def> = COPY %vreg676:sub2_sub3; VReg_128:%vreg687 SReg_128:%vreg676
4688B		%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
4832B		%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4848B		%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg250:sub7<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
4960B		%vreg195:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg195,%vreg183
4976B		%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
5120B		%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5136B		%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
5344B		%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5360B		%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg250:sub6<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
5472B		%vreg203:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg203,%vreg183
5488B		%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
5632B		%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5648B		%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
5856B		%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5872B		%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg250:sub5<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
5984B		%vreg211:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg211,%vreg183
6000B		%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
6144B		%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6160B		%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
6368B		%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6384B		%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg250:sub4<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
6496B		%vreg219:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg219,%vreg183
6512B		%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
6656B		%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6672B		%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
6880B		%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6896B		%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg250:sub3<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
7008B		%vreg227:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg227,%vreg183
7024B		%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
7168B		%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7184B		%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
7392B		%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7408B		%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg250:sub2<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
7520B		%vreg235:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg235,%vreg183
7536B		%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
7680B		%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7696B		%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
7904B		%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7920B		%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg250:sub1<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
8032B		%vreg243:sub1<def> = COPY %vreg183:sub1; SGPR_64:%vreg243,%vreg183
8048B		%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
8192B		%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8208B		%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
8416B		%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8432B		%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg250:sub0<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
9280B		%vreg856<def> = V_ADD_F32_e32 %vreg856, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
9360B		%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
9376B		%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
9392B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
9472B		%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
9488B		%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
9504B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg854<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
9600B		%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297, %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
9776B		SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
10032B		%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
10048B		%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
10064B		%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
10144B		%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
10160B		%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
10176B		%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg856<def> = V_MAD_F32 %vreg369, %vreg369, %vreg856, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
10352B		%vreg860<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
10384B		%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371, %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
10496B		%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
10512B		%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
10560B		SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SGPR_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
10720B		%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_64:%vreg425
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
10848B		%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
10864B		%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg856, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
11008B		%vreg395<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
11136B		%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
11152B		%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11312B		%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
11328B		%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
11344B		%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
11424B		BUFFER_STORE_DWORD %vreg388, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

Shrink: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
Shrunk: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
Shrink: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
Shrunk: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
Shrink: %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
Shrunk: %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
Shrink: %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
Shrunk: %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
Shrink: %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
Shrunk: %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
Shrink: %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
Shrunk: %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
Shrink: %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
Shrunk: %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
Shrink: %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
Shrunk: %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
Shrink: %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
Shrunk: %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
Shrink: %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
Shrunk: %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
Shrink: %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
Shrunk: %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
Shrink: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
Shrunk: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
Shrink: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
Shrunk: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
Shrink: %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
Shrunk: %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
Shrink: %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
Shrunk: %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
Shrink: %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
Shrunk: %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
Shrink: %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
Shrunk: %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
Shrink: %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
Shrunk: %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
Shrink: %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
Shrunk: %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
Shrink: %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
Shrunk: %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
Shrink: %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
Shrunk: %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
Shrink: %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
Shrunk: %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
Shrink: %vreg397 [11232r,11248r:0)  0@11232r
Shrunk: %vreg397 [11232r,11248r:0)  0@11232r
Shrink: %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
Shrunk: %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
Shrink: %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
Shrunk: %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
Shrink: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
Shrunk: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
Shrink: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
Shrunk: %vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
Shrink: %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
Shrunk: %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
Shrink: %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
Shrunk: %vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
Shrink: %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
Shrunk: %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
Shrink: %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
Shrunk: %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
Shrink: %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
Shrunk: %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
Shrink: %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
Shrunk: %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
Shrink: %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
Shrunk: %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
Shrink: %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
Shrunk: %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
Shrink: %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
Shrunk: %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
Shrink: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
Shrunk: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
Shrink: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
Shrunk: %vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
Shrink: %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
Shrunk: %vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
Shrink: %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
Shrunk: %vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
Shrink: %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
Shrunk: %vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
Shrink: %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
Shrunk: %vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
Shrink: %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
Shrunk: %vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
Shrink: %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
Shrunk: %vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
Shrink: %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
Shrunk: %vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
Shrink: %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
Shrunk: %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
Shrink: %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
Shrunk: %vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
Shrink: %vreg397 [11232r,11248r:0)  0@11232r
Shrunk: %vreg397 [11232r,11248r:0)  0@11232r
Shrink: %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
Shrunk: %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
Shrink: %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
Shrunk: %vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
# *** IR Dump Before Debug Variable Analysis ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
32B		%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
48B		%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
64B		%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
112B		%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
224B		%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
368B		%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
384B		%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
400B		%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
416B		%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
432B		%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
448B		%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9 SGPR_32:%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
752B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SGPR_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
944B		%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_64:%vreg104
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
1072B		%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
1088B		%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
1168B		%vreg116<def> = S_MOV_B64 32; SGPR_64:%vreg116
1216B		%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
1232B		%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
1248B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SGPR_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_64:%vreg130
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
1488B		%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
1504B		%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
1584B		%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
1600B		%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
1616B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
1664B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
1696B		%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
1728B		%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
1792B		%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
1808B		%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
1824B		%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
1840B		%vreg183:sub0<def> = S_MOV_B32 -4; SGPR_64:%vreg183
1856B		%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
1872B		%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
1888B		%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
1904B		%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
1920B		%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
1936B		%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
1952B		%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
1968B		%vreg283<def> = S_MOV_B64 64; SGPR_64:%vreg283
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299 SGPR_32:%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg459:sub0<def,read-undef> = COPY %vreg13; VReg_64:%vreg459 SReg_32:%vreg13
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SGPR_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_64:%vreg312
2528B		%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_64:%vreg459
2608B		%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
2624B		%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
2752B		%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
2768B		%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SGPR_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_64:%vreg338
2960B		%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
2976B		%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
3104B		%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
3120B		%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
3168B		%vreg860<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
3184B		%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
3248B		%vreg353<def> = S_MOV_B64 4; SGPR_64:%vreg353
3264B		%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
3280B		%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg250:sub14<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg250:sub13<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg250:sub12<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg250:sub11<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg250:sub10<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg250:sub9<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg250:sub8<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
4336B		%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
4480B		%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4496B		%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4688B		%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
4832B		%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4848B		%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg250:sub7<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
4960B		%vreg195:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg195
4976B		%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
5120B		%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5136B		%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
5344B		%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5360B		%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg250:sub6<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
5472B		%vreg203:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg203
5488B		%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
5632B		%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5648B		%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
5856B		%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5872B		%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg250:sub5<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
5984B		%vreg211:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg211
6000B		%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
6144B		%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6160B		%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
6368B		%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6384B		%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg250:sub4<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
6496B		%vreg219:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg219
6512B		%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
6656B		%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6672B		%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
6880B		%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6896B		%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg250:sub3<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
7008B		%vreg227:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg227
7024B		%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
7168B		%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7184B		%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
7392B		%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7408B		%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg250:sub2<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
7520B		%vreg235:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg235
7536B		%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
7680B		%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7696B		%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
7904B		%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7920B		%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg250:sub1<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
8032B		%vreg243:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg243
8048B		%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
8192B		%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8208B		%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
8416B		%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8432B		%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg250:sub0<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
9280B		%vreg856<def> = V_ADD_F32_e32 %vreg856, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
9360B		%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
9376B		%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
9392B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
9472B		%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
9488B		%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
9504B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg854<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
9600B		%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297, %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
9776B		SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
10032B		%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
10048B		%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
10064B		%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
10144B		%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
10160B		%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
10176B		%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg856<def> = V_MAD_F32 %vreg369, %vreg369, %vreg856, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
10352B		%vreg860<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
10384B		%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371, %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
10496B		%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
10512B		%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
10560B		SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SGPR_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
10720B		%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_64:%vreg425
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
10848B		%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
10864B		%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg856, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
11008B		%vreg395<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
11136B		%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
11152B		%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11312B		%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
11328B		%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
11344B		%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
11424B		BUFFER_STORE_DWORD %vreg388, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Live Stack Slot Analysis ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
32B		%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
48B		%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
64B		%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
112B		%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
224B		%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
368B		%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
384B		%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
400B		%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
416B		%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
432B		%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
448B		%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9 SGPR_32:%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
752B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SGPR_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
944B		%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_64:%vreg104
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
1072B		%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
1088B		%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
1168B		%vreg116<def> = S_MOV_B64 32; SGPR_64:%vreg116
1216B		%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
1232B		%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
1248B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SGPR_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_64:%vreg130
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
1488B		%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
1504B		%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
1584B		%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
1600B		%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
1616B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
1664B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
1696B		%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
1728B		%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
1792B		%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
1808B		%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
1824B		%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
1840B		%vreg183:sub0<def> = S_MOV_B32 -4; SGPR_64:%vreg183
1856B		%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
1872B		%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
1888B		%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
1904B		%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
1920B		%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
1936B		%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
1952B		%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
1968B		%vreg283<def> = S_MOV_B64 64; SGPR_64:%vreg283
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299 SGPR_32:%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg459:sub0<def,read-undef> = COPY %vreg13; VReg_64:%vreg459 SReg_32:%vreg13
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SGPR_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_64:%vreg312
2528B		%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_64:%vreg459
2608B		%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
2624B		%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
2752B		%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
2768B		%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SGPR_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_64:%vreg338
2960B		%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
2976B		%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
3104B		%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
3120B		%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
3168B		%vreg860<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
3184B		%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
3248B		%vreg353<def> = S_MOV_B64 4; SGPR_64:%vreg353
3264B		%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
3280B		%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg250:sub14<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg250:sub13<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg250:sub12<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg250:sub11<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg250:sub10<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg250:sub9<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg250:sub8<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
4336B		%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
4480B		%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4496B		%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4688B		%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
4832B		%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4848B		%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg250:sub7<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
4960B		%vreg195:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg195
4976B		%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
5120B		%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5136B		%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
5344B		%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5360B		%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg250:sub6<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
5472B		%vreg203:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg203
5488B		%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
5632B		%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5648B		%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
5856B		%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5872B		%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg250:sub5<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
5984B		%vreg211:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg211
6000B		%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
6144B		%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6160B		%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
6368B		%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6384B		%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg250:sub4<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
6496B		%vreg219:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg219
6512B		%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
6656B		%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6672B		%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
6880B		%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6896B		%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg250:sub3<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
7008B		%vreg227:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg227
7024B		%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
7168B		%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7184B		%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
7392B		%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7408B		%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg250:sub2<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
7520B		%vreg235:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg235
7536B		%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
7680B		%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7696B		%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
7904B		%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7920B		%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg250:sub1<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
8032B		%vreg243:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg243
8048B		%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
8192B		%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8208B		%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
8416B		%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8432B		%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg250:sub0<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
9280B		%vreg856<def> = V_ADD_F32_e32 %vreg856, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
9360B		%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
9376B		%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
9392B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
9472B		%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
9488B		%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
9504B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg854<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
9600B		%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297, %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
9776B		SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
10032B		%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
10048B		%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
10064B		%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
10144B		%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
10160B		%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
10176B		%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg856<def> = V_MAD_F32 %vreg369, %vreg369, %vreg856, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
10352B		%vreg860<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
10384B		%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371, %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
10496B		%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
10512B		%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
10560B		SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SGPR_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
10720B		%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_64:%vreg425
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
10848B		%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
10864B		%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg856, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
11008B		%vreg395<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
11136B		%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
11152B		%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11312B		%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
11328B		%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
11344B		%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
11424B		BUFFER_STORE_DWORD %vreg388, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Virtual Register Map ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
32B		%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
48B		%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
64B		%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
112B		%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
224B		%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
368B		%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
384B		%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
400B		%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
416B		%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
432B		%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
448B		%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9 SGPR_32:%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
752B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SGPR_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
944B		%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_64:%vreg104
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
1072B		%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
1088B		%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
1168B		%vreg116<def> = S_MOV_B64 32; SGPR_64:%vreg116
1216B		%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
1232B		%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
1248B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SGPR_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_64:%vreg130
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
1488B		%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
1504B		%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
1584B		%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
1600B		%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
1616B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
1664B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
1696B		%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
1728B		%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
1792B		%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
1808B		%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
1824B		%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
1840B		%vreg183:sub0<def> = S_MOV_B32 -4; SGPR_64:%vreg183
1856B		%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
1872B		%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
1888B		%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
1904B		%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
1920B		%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
1936B		%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
1952B		%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
1968B		%vreg283<def> = S_MOV_B64 64; SGPR_64:%vreg283
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299 SGPR_32:%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg459:sub0<def,read-undef> = COPY %vreg13; VReg_64:%vreg459 SReg_32:%vreg13
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SGPR_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_64:%vreg312
2528B		%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_64:%vreg459
2608B		%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
2624B		%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
2752B		%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
2768B		%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SGPR_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_64:%vreg338
2960B		%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
2976B		%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
3104B		%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
3120B		%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
3168B		%vreg860<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
3184B		%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
3248B		%vreg353<def> = S_MOV_B64 4; SGPR_64:%vreg353
3264B		%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
3280B		%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg250:sub14<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg250:sub13<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg250:sub12<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg250:sub11<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg250:sub10<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg250:sub9<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg250:sub8<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
4336B		%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
4480B		%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4496B		%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4688B		%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
4832B		%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4848B		%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg250:sub7<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
4960B		%vreg195:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg195
4976B		%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
5120B		%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5136B		%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
5344B		%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5360B		%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg250:sub6<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
5472B		%vreg203:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg203
5488B		%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
5632B		%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5648B		%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
5856B		%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5872B		%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg250:sub5<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
5984B		%vreg211:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg211
6000B		%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
6144B		%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6160B		%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
6368B		%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6384B		%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg250:sub4<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
6496B		%vreg219:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg219
6512B		%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
6656B		%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6672B		%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
6880B		%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6896B		%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg250:sub3<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
7008B		%vreg227:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg227
7024B		%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
7168B		%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7184B		%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
7392B		%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7408B		%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg250:sub2<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
7520B		%vreg235:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg235
7536B		%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
7680B		%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7696B		%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
7904B		%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7920B		%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg250:sub1<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
8032B		%vreg243:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg243
8048B		%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
8192B		%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8208B		%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
8416B		%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8432B		%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg250:sub0<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
9280B		%vreg856<def> = V_ADD_F32_e32 %vreg856, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
9360B		%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
9376B		%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
9392B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
9472B		%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
9488B		%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
9504B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg854<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
9600B		%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297, %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
9776B		SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
10032B		%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
10048B		%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
10064B		%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
10144B		%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
10160B		%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
10176B		%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg856<def> = V_MAD_F32 %vreg369, %vreg369, %vreg856, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
10352B		%vreg860<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
10384B		%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371, %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
10496B		%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
10512B		%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
10560B		SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SGPR_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
10720B		%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_64:%vreg425
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
10848B		%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
10864B		%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg856, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
11008B		%vreg395<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
11136B		%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
11152B		%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11312B		%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
11328B		%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
11344B		%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
11424B		BUFFER_STORE_DWORD %vreg388, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Live Register Matrix ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
32B		%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
48B		%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
64B		%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
112B		%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
224B		%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
368B		%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
384B		%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
400B		%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
416B		%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
432B		%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
448B		%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9 SGPR_32:%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
752B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SGPR_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
944B		%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_64:%vreg104
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
1072B		%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
1088B		%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
1168B		%vreg116<def> = S_MOV_B64 32; SGPR_64:%vreg116
1216B		%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
1232B		%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
1248B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SGPR_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_64:%vreg130
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
1488B		%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
1504B		%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
1584B		%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
1600B		%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
1616B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
1664B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
1696B		%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
1728B		%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
1792B		%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
1808B		%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
1824B		%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
1840B		%vreg183:sub0<def> = S_MOV_B32 -4; SGPR_64:%vreg183
1856B		%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
1872B		%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
1888B		%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
1904B		%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
1920B		%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
1936B		%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
1952B		%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
1968B		%vreg283<def> = S_MOV_B64 64; SGPR_64:%vreg283
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299 SGPR_32:%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg459:sub0<def,read-undef> = COPY %vreg13; VReg_64:%vreg459 SReg_32:%vreg13
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SGPR_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_64:%vreg312
2528B		%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_64:%vreg459
2608B		%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
2624B		%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
2752B		%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
2768B		%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SGPR_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_64:%vreg338
2960B		%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
2976B		%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
3104B		%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
3120B		%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
3168B		%vreg860<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
3184B		%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
3248B		%vreg353<def> = S_MOV_B64 4; SGPR_64:%vreg353
3264B		%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
3280B		%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg250:sub14<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg250:sub13<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg250:sub12<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg250:sub11<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg250:sub10<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg250:sub9<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg250:sub8<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
4336B		%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
4480B		%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4496B		%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4688B		%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
4832B		%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4848B		%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg250:sub7<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
4960B		%vreg195:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg195
4976B		%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
5120B		%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5136B		%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
5344B		%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5360B		%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg250:sub6<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
5472B		%vreg203:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg203
5488B		%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
5632B		%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5648B		%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
5856B		%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5872B		%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg250:sub5<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
5984B		%vreg211:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg211
6000B		%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
6144B		%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6160B		%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
6368B		%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6384B		%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg250:sub4<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
6496B		%vreg219:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg219
6512B		%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
6656B		%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6672B		%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
6880B		%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6896B		%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg250:sub3<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
7008B		%vreg227:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg227
7024B		%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
7168B		%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7184B		%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
7392B		%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7408B		%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg250:sub2<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
7520B		%vreg235:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg235
7536B		%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
7680B		%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7696B		%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
7904B		%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7920B		%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg250:sub1<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
8032B		%vreg243:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg243
8048B		%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
8192B		%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8208B		%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
8416B		%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8432B		%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg250:sub0<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
9280B		%vreg856<def> = V_ADD_F32_e32 %vreg856, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
9360B		%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
9376B		%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
9392B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
9472B		%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
9488B		%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
9504B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg854<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
9600B		%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297, %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
9776B		SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
10032B		%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
10048B		%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
10064B		%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
10144B		%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
10160B		%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
10176B		%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg856<def> = V_MAD_F32 %vreg369, %vreg369, %vreg856, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
10352B		%vreg860<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
10384B		%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371, %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
10496B		%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
10512B		%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
10560B		SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SGPR_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
10720B		%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_64:%vreg425
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
10848B		%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
10864B		%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg856, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
11008B		%vreg395<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
11136B		%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
11152B		%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11312B		%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
11328B		%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
11344B		%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
11424B		BUFFER_STORE_DWORD %vreg388, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

********** GREEDY REGISTER ALLOCATION **********
********** Function: svm_rbf
********** INTERVALS **********
SGPR0 [0B,80r:0)  0@0B-phi
SGPR1 [0B,80r:0)  0@0B-phi
SGPR2 [0B,16r:0)  0@0B-phi
SGPR3 [0B,48r:0)  0@0B-phi
VGPR0 [0B,32r:0)  0@0B-phi
VGPR1 [0B,64r:0)  0@0B-phi
%vreg0 [16r,2224B:0)[2272B,2816r:0)[3408B,9808B:0)  0@16r
%vreg1 [112r,2224B:0)[2272B,2832r:0)[3408B,9808B:0)  0@112r
%vreg4 [48r,2224B:0)[2272B,2384r:0)[3408B,9808B:0)  0@48r
%vreg5 [224r,2224B:0)[2272B,2400r:0)[3408B,9808B:0)  0@224r
%vreg9 [688r,2096B:0)[3552B,9808B:0)  0@688r
%vreg13 [2144r,2160r:0)  0@2144r
%vreg45 [10848r,10864r:0)[10864r,11248r:1)[11280B,11456B:1)  0@10848r 1@10864r
%vreg48 [80r,448r:0)  0@80r
%vreg49 [448r,2224B:0)[2272B,2736r:0)[3408B,9808B:0)  0@448r
%vreg50 [432r,2224B:0)[2272B,2432r:0)[3408B,9808B:0)  0@432r
%vreg51 [416r,2224B:0)[2272B,3088r:0)[3408B,9808B:0)  0@416r
%vreg52 [400r,2224B:0)[2272B,2864r:0)[3408B,9808B:0)  0@400r
%vreg53 [384r,2224B:0)[2272B,10832r:0)  0@384r
%vreg54 [368r,2224B:0)[2272B,10672r:0)  0@368r
%vreg55 [352r,2224B:0)[2272B,3168r:0)[3408B,9808B:0)  0@352r
%vreg56 [2272B,3408B:0)[3456r,3552B:0)[9808B,10912r:0)  0@3456r
%vreg61 [96r,128r:0)  0@96r
%vreg63 [128r,144r:0)  0@128r
%vreg66 [160r,176r:0)  0@160r
%vreg67 [176r,192r:0)  0@176r
%vreg68 [192r,320r:0)  0@192r
%vreg69 [208r,240r:0)  0@208r
%vreg71 [240r,256r:0)  0@240r
%vreg74 [272r,288r:0)  0@272r
%vreg75 [288r,304r:0)  0@288r
%vreg76 [304r,320r:0)  0@304r
%vreg77 [320r,464r:0)  0@320r
%vreg78 [336r,2224B:0)[3408B,3456r:0)[3552B,9808B:0)  0@336r
%vreg86 [464r,2240r:0)[2272B,11504B:0)  0@464r
%vreg89 [704r,832r:0)  0@704r
%vreg92 [832r,2224B:0)[3408B,3504r:0)[3552B,9808B:0)  0@832r
%vreg96 [880r,896r:0)  0@880r
%vreg97 [896r,912r:0)  0@896r
%vreg104 [928r,944r:0)[944r,992r:1)  0@928r 1@944r
%vreg116 [1168r,1600r:0)  0@1168r
%vreg122 [1296r,1312r:0)  0@1296r
%vreg123 [1312r,1328r:0)  0@1312r
%vreg130 [1344r,1360r:0)[1360r,1408r:1)  0@1344r 1@1360r
%vreg149 [3712r,3744r:0)  0@3712r
%vreg150 [3728r,3744r:0)  0@3728r
%vreg151 [3744r,3760r:0)  0@3744r
%vreg153 [3776r,3808r:0)  0@3776r
%vreg154 [3792r,3808r:0)  0@3792r
%vreg155 [3808r,3824r:0)  0@3808r
%vreg157 [3840r,3872r:0)  0@3840r
%vreg158 [3856r,3872r:0)  0@3856r
%vreg159 [3872r,3888r:0)  0@3872r
%vreg161 [3904r,3936r:0)  0@3904r
%vreg162 [3920r,3936r:0)  0@3920r
%vreg163 [3936r,3952r:0)  0@3936r
%vreg165 [3968r,4000r:0)  0@3968r
%vreg166 [3984r,4000r:0)  0@3984r
%vreg167 [4000r,4016r:0)  0@4000r
%vreg169 [4032r,4064r:0)  0@4032r
%vreg170 [4048r,4064r:0)  0@4048r
%vreg171 [4064r,4080r:0)  0@4064r
%vreg173 [4096r,4128r:0)  0@4096r
%vreg174 [4112r,4128r:0)  0@4112r
%vreg175 [4128r,4144r:0)  0@4128r
%vreg177 [4160r,4192r:0)  0@4160r
%vreg178 [4176r,4192r:0)  0@4176r
%vreg179 [4192r,4208r:0)  0@4192r
%vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi
%vreg186 [4592r,4912r:0)  0@4592r
%vreg190 [4896r,4912r:0)  0@4896r
%vreg192 [4912r,4928r:0)  0@4912r
%vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi
%vreg196 [5184r,5424r:0)  0@5184r
%vreg198 [5408r,5424r:0)  0@5408r
%vreg200 [5424r,5440r:0)  0@5424r
%vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi
%vreg204 [5696r,5936r:0)  0@5696r
%vreg206 [5920r,5936r:0)  0@5920r
%vreg208 [5936r,5952r:0)  0@5936r
%vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi
%vreg212 [6208r,6448r:0)  0@6208r
%vreg214 [6432r,6448r:0)  0@6432r
%vreg216 [6448r,6464r:0)  0@6448r
%vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi
%vreg220 [6720r,6960r:0)  0@6720r
%vreg222 [6944r,6960r:0)  0@6944r
%vreg224 [6960r,6976r:0)  0@6960r
%vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi
%vreg228 [7232r,7472r:0)  0@7232r
%vreg230 [7456r,7472r:0)  0@7456r
%vreg232 [7472r,7488r:0)  0@7472r
%vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi
%vreg236 [7744r,7984r:0)  0@7744r
%vreg238 [7968r,7984r:0)  0@7968r
%vreg240 [7984r,8000r:0)  0@7984r
%vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi
%vreg244 [8256r,8496r:0)  0@8256r
%vreg246 [8480r,8496r:0)  0@8480r
%vreg248 [8496r,8512r:0)  0@8496r
%vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9264r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r
%vreg253 [8816r,8848r:0)  0@8816r
%vreg255 [8848r,8880r:0)  0@8848r
%vreg257 [8880r,8912r:0)  0@8880r
%vreg259 [8912r,8944r:0)  0@8912r
%vreg261 [8944r,8976r:0)  0@8944r
%vreg263 [8976r,9008r:0)  0@8976r
%vreg265 [9008r,9040r:0)  0@9008r
%vreg267 [9040r,9072r:0)  0@9040r
%vreg269 [9072r,9104r:0)  0@9072r
%vreg271 [9104r,9136r:0)  0@9104r
%vreg273 [9136r,9168r:0)  0@9136r
%vreg275 [9168r,9200r:0)  0@9168r
%vreg277 [9200r,9232r:0)  0@9200r
%vreg279 [9232r,9264r:0)  0@9232r
%vreg281 [9264r,9280r:0)  0@9264r
%vreg283 [1968r,2096B:0)[3552B,9808B:0)  0@1968r
%vreg296 [9552r,9584r:0)  0@9552r
%vreg297 [9584r,9600r:0)  0@9584r
%vreg299 [2128r,2144r:0)  0@2128r
%vreg300 [2288r,2304r:0)  0@2288r
%vreg301 [2304r,2336r:0)  0@2304r
%vreg302 [2336r,3408B:0)[9808B,9840r:0)[9872B,10656B:0)  0@2336r
%vreg304 [2384r,2400r:0)  0@2384r
%vreg305 [2400r,2416r:0)  0@2400r
%vreg312 [2432r,2448r:0)[2448r,2624r:1)  0@2432r 1@2448r
%vreg330 [2816r,2832r:0)  0@2816r
%vreg331 [2832r,2848r:0)  0@2832r
%vreg338 [2864r,2880r:0)[2880r,2976r:1)  0@2864r 1@2880r
%vreg353 [3248r,3408B:0)[9872B,10592B:0)  0@3248r
%vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r
%vreg367 [10288r,10320r:0)  0@10288r
%vreg368 [10304r,10320r:0)  0@10304r
%vreg369 [10320r,10336r:0)  0@10320r
%vreg371 [10368r,10384r:0)  0@10368r
%vreg373 [10672r,10688r:0)  0@10672r
%vreg374 [10688r,10704r:0)  0@10688r
%vreg388 [10912r,11040B:0)[11280B,11424r:0)  0@10912r
%vreg389 [10928r,10944r:0)  0@10928r
%vreg390 [10944r,10976r:0)  0@10944r
%vreg391 [10960r,10976r:0)  0@10960r
%vreg392 [10976r,11008r:0)  0@10976r
%vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r
%vreg395 [11008r,11072r:0)[11072r,11280B:1)[11280B,11456B:0)[11456B,11472r:1)  0@11008r 1@11072r
%vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r
%vreg397 [11232r,11248r:0)  0@11232r
%vreg423 [144r,2224B:0)[2272B,10704r:0)  0@144r
%vreg425 [10704r,10720r:0)[10720r,10768r:1)  0@10704r 1@10720r
%vreg428 [10768r,10864r:0)  0@10768r
%vreg440 [256r,2224B:0)[2272B,10688r:0)  0@256r
%vreg442 [64r,2224B:0)[2272B,2416r:0)[3408B,9808B:0)  0@64r
%vreg443 [912r,928r:0)  0@912r
%vreg444 [2416r,2432r:0)  0@2416r
%vreg445 [32r,2224B:0)[2272B,2848r:0)[3408B,9808B:0)  0@32r
%vreg446 [1328r,1344r:0)  0@1328r
%vreg447 [2848r,2864r:0)  0@2848r
%vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2528r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2528r 2@720r 3@2160r
%vreg465 [2960r,2976r:0)[2976r,3024r:1)  0@2960r 1@2976r
%vreg468 [3024r,3120r:0)  0@3024r
%vreg479 [2608r,2624r:0)[2624r,2672r:1)  0@2608r 1@2624r
%vreg482 [2672r,2768r:0)  0@2672r
%vreg499 [992r,1088r:0)  0@992r
%vreg503 [1072r,1088r:0)[1088r,1248r:1)  0@1072r 1@1088r
%vreg508 [1232r,1248r:0)  0@1232r
%vreg516 [1040r,1072r:0)  0@1040r
%vreg517 [1056r,1088r:0)  0@1056r
%vreg522 [1408r,1504r:0)  0@1408r
%vreg526 [1488r,1504r:0)[1504r,1616r:1)  0@1488r 1@1504r
%vreg531 [1600r,1616r:0)  0@1600r
%vreg539 [1456r,1488r:0)  0@1456r
%vreg540 [1472r,1504r:0)  0@1472r
%vreg551 [2720r,2752r:0)  0@2720r
%vreg552 [2736r,2768r:0)  0@2736r
%vreg558 [3072r,3104r:0)  0@3072r
%vreg559 [3088r,3120r:0)  0@3088r
%vreg562 [1584r,1616r:2)[1616r,2096B:3)[3552B,9472r:0)[9472r,9504r:4)[9504r,9808B:5)  0@3552B-phi 1@x 2@1584r 3@1616r 4@9472r 5@9504r
%vreg567 [8192r,8208r:0)[8208r,8256r:1)  0@8192r 1@8208r
%vreg578 [8048r,8208r:0)  0@8048r
%vreg582 [7680r,7696r:0)[7696r,7744r:1)  0@7680r 1@7696r
%vreg593 [7536r,7696r:0)  0@7536r
%vreg597 [7168r,7184r:0)[7184r,7232r:1)  0@7168r 1@7184r
%vreg608 [7024r,7184r:0)  0@7024r
%vreg612 [6656r,6672r:0)[6672r,6720r:1)  0@6656r 1@6672r
%vreg623 [6512r,6672r:0)  0@6512r
%vreg627 [6144r,6160r:0)[6160r,6208r:1)  0@6144r 1@6160r
%vreg638 [6000r,6160r:0)  0@6000r
%vreg642 [5632r,5648r:0)[5648r,5696r:1)  0@5632r 1@5648r
%vreg653 [5488r,5648r:0)  0@5488r
%vreg657 [5120r,5136r:0)[5136r,5184r:1)  0@5120r 1@5136r
%vreg668 [4976r,5136r:0)  0@4976r
%vreg672 [4480r,4496r:0)[4496r,4592r:1)  0@4480r 1@4496r
%vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r
%vreg683 [4336r,4496r:0)  0@4336r
%vreg687 [1216r,1248r:2)[1248r,2096B:3)[3552B,9360r:0)[9360r,9392r:4)[9392r,9808B:5)  0@3552B-phi 1@x 2@1216r 3@1248r 4@9360r 5@9392r
%vreg692 [8416r,8432r:0)[8432r,8480r:1)  0@8416r 1@8432r
%vreg703 [8272r,8432r:0)  0@8272r
%vreg707 [7904r,7920r:0)[7920r,7968r:1)  0@7904r 1@7920r
%vreg718 [7760r,7920r:0)  0@7760r
%vreg722 [7392r,7408r:0)[7408r,7456r:1)  0@7392r 1@7408r
%vreg733 [7248r,7408r:0)  0@7248r
%vreg737 [6880r,6896r:0)[6896r,6944r:1)  0@6880r 1@6896r
%vreg748 [6736r,6896r:0)  0@6736r
%vreg752 [6368r,6384r:0)[6384r,6432r:1)  0@6368r 1@6384r
%vreg763 [6224r,6384r:0)  0@6224r
%vreg767 [5856r,5872r:0)[5872r,5920r:1)  0@5856r 1@5872r
%vreg778 [5712r,5872r:0)  0@5712r
%vreg782 [5344r,5360r:0)[5360r,5408r:1)  0@5344r 1@5360r
%vreg793 [5200r,5360r:0)  0@5200r
%vreg797 [4832r,4848r:0)[4848r,4896r:1)  0@4832r 1@4848r
%vreg808 [4688r,4848r:0)  0@4688r
%vreg818 [9376r,9392r:0)  0@9376r
%vreg827 [9488r,9504r:0)  0@9488r
%vreg830 [10032r,10064r:0)[10064r,10496r:1)  0@10032r 1@10064r
%vreg836 [10048r,10064r:0)  0@10048r
%vreg839 [10144r,10176r:0)[10176r,10512r:1)  0@10144r 1@10176r
%vreg845 [10160r,10176r:0)  0@10160r
%vreg847 [10816r,10848r:0)  0@10816r
%vreg848 [10832r,10864r:0)  0@10832r
%vreg851 [2096B,2112r:2)[3552B,9600r:1)[9600r,9808B:2)  0@x 1@3552B-phi 2@9600r
%vreg854 [1696r,2096B:0)[3552B,9568r:1)[9568r,9808B:2)  0@1696r 1@3552B-phi 2@9568r
%vreg856 [752r,864B:3)[1664r,2096B:5)[2096B,2224B:4)[2272B,3552B:0)[3552B,9280r:6)[9280r,9808B:4)[9808B,9872B:2)[9872B,10336r:7)[10336r,10656B:1)[10656B,10912r:2)  0@3408B-phi 1@10336r 2@9808B-phi 3@752r 4@9280r 5@1664r 6@3552B-phi 7@9872B-phi
%vreg857 [9872B,10384r:1)[10384r,10608r:2)  0@x 1@9872B-phi 2@10384r
%vreg858 [2752r,2768r:0)[2768r,3408B:1)[9872B,10304r:3)[10496r,10592B:2)  0@2752r 1@2768r 2@10496r 3@9872B-phi
%vreg859 [3104r,3120r:0)[3120r,3408B:1)[9872B,10288r:3)[10512r,10592B:2)  0@3104r 1@3120r 2@10512r 3@9872B-phi
%vreg860 [3168r,3408B:0)[9872B,10352r:1)[10352r,10592B:2)  0@3168r 1@9872B-phi 2@10352r
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
32B		%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
48B		%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
64B		%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
112B		%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
224B		%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
368B		%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
384B		%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
400B		%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
416B		%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
432B		%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
448B		%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9 SGPR_32:%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
752B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SGPR_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
944B		%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_64:%vreg104
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
1072B		%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
1088B		%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
1168B		%vreg116<def> = S_MOV_B64 32; SGPR_64:%vreg116
1216B		%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
1232B		%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
1248B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SGPR_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_64:%vreg130
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
1488B		%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
1504B		%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
1584B		%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
1600B		%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
1616B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
1664B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
1696B		%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
1728B		%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
1792B		%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
1808B		%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
1824B		%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
1840B		%vreg183:sub0<def> = S_MOV_B32 -4; SGPR_64:%vreg183
1856B		%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
1872B		%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
1888B		%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
1904B		%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
1920B		%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
1936B		%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
1952B		%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
1968B		%vreg283<def> = S_MOV_B64 64; SGPR_64:%vreg283
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299 SGPR_32:%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg459:sub0<def,read-undef> = COPY %vreg13; VReg_64:%vreg459 SReg_32:%vreg13
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SGPR_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_64:%vreg312
2528B		%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_64:%vreg459
2608B		%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
2624B		%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
2752B		%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
2768B		%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SGPR_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_64:%vreg338
2960B		%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
2976B		%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
3104B		%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
3120B		%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
3168B		%vreg860<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
3184B		%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
3248B		%vreg353<def> = S_MOV_B64 4; SGPR_64:%vreg353
3264B		%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
3280B		%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg250:sub14<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg250:sub13<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg250:sub12<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg250:sub11<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg250:sub10<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg250:sub9<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg250:sub8<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
4336B		%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
4480B		%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4496B		%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4688B		%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
4832B		%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4848B		%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg250:sub7<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
4960B		%vreg195:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg195
4976B		%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
5120B		%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5136B		%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
5344B		%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5360B		%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg250:sub6<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
5472B		%vreg203:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg203
5488B		%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
5632B		%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5648B		%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
5856B		%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5872B		%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg250:sub5<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
5984B		%vreg211:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg211
6000B		%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
6144B		%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6160B		%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
6368B		%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6384B		%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg250:sub4<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
6496B		%vreg219:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg219
6512B		%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
6656B		%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6672B		%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
6880B		%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6896B		%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg250:sub3<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
7008B		%vreg227:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg227
7024B		%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
7168B		%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7184B		%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
7392B		%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7408B		%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg250:sub2<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
7520B		%vreg235:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg235
7536B		%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
7680B		%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7696B		%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
7904B		%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7920B		%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg250:sub1<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
8032B		%vreg243:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg243
8048B		%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
8192B		%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8208B		%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
8416B		%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8432B		%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg250:sub0<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
9280B		%vreg856<def> = V_ADD_F32_e32 %vreg856, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
9360B		%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
9376B		%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
9392B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
9472B		%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
9488B		%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
9504B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg854<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
9600B		%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297, %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
9776B		SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
10032B		%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
10048B		%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
10064B		%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
10144B		%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
10160B		%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
10176B		%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg856<def> = V_MAD_F32 %vreg369, %vreg369, %vreg856, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
10352B		%vreg860<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
10384B		%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371, %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
10496B		%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
10512B		%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
10560B		SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SGPR_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
10720B		%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_64:%vreg425
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
10848B		%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
10864B		%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg856, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
11008B		%vreg395<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
11136B		%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
11152B		%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11312B		%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
11328B		%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
11344B		%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
11424B		BUFFER_STORE_DWORD %vreg388, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.


selectOrSplit VReg_32:%vreg445 [32r,2224B:0)[2272B,2848r:0)[3408B,9808B:0)  0@32r w=2.639005e-04
AllocationOrder(VReg_32) = [ %VGPR0 %VGPR1 %VGPR2 %VGPR3 %VGPR4 %VGPR5 %VGPR6 %VGPR7 %VGPR8 %VGPR9 %VGPR10 %VGPR11 %VGPR12 %VGPR13 %VGPR14 %VGPR15 %VGPR16 %VGPR17 %VGPR18 %VGPR19 %VGPR20 %VGPR21 %VGPR22 %VGPR23 %VGPR24 %VGPR25 %VGPR26 %VGPR27 %VGPR28 %VGPR29 %VGPR30 %VGPR31 %VGPR32 %VGPR33 %VGPR34 %VGPR35 %VGPR36 %VGPR37 %VGPR38 %VGPR39 %VGPR40 %VGPR41 %VGPR42 %VGPR43 %VGPR44 %VGPR45 %VGPR46 %VGPR47 %VGPR48 %VGPR49 %VGPR50 %VGPR51 %VGPR52 %VGPR53 %VGPR54 %VGPR55 %VGPR56 %VGPR57 %VGPR58 %VGPR59 %VGPR60 %VGPR61 %VGPR62 %VGPR63 %VGPR64 %VGPR65 %VGPR66 %VGPR67 %VGPR68 %VGPR69 %VGPR70 %VGPR71 %VGPR72 %VGPR73 %VGPR74 %VGPR75 %VGPR76 %VGPR77 %VGPR78 %VGPR79 %VGPR80 %VGPR81 %VGPR82 %VGPR83 %VGPR84 %VGPR85 %VGPR86 %VGPR87 %VGPR88 %VGPR89 %VGPR90 %VGPR91 %VGPR92 %VGPR93 %VGPR94 %VGPR95 %VGPR96 %VGPR97 %VGPR98 %VGPR99 %VGPR100 %VGPR101 %VGPR102 %VGPR103 %VGPR104 %VGPR105 %VGPR106 %VGPR107 %VGPR108 %VGPR109 %VGPR110 %VGPR111 %VGPR112 %VGPR113 %VGPR114 %VGPR115 %VGPR116 %VGPR117 %VGPR118 %VGPR119 %VGPR120 %VGPR121 %VGPR122 %VGPR123 %VGPR124 %VGPR125 %VGPR126 %VGPR127 %VGPR128 %VGPR129 %VGPR130 %VGPR131 %VGPR132 %VGPR133 %VGPR134 %VGPR135 %VGPR136 %VGPR137 %VGPR138 %VGPR139 %VGPR140 %VGPR141 %VGPR142 %VGPR143 %VGPR144 %VGPR145 %VGPR146 %VGPR147 %VGPR148 %VGPR149 %VGPR150 %VGPR151 %VGPR152 %VGPR153 %VGPR154 %VGPR155 %VGPR156 %VGPR157 %VGPR158 %VGPR159 %VGPR160 %VGPR161 %VGPR162 %VGPR163 %VGPR164 %VGPR165 %VGPR166 %VGPR167 %VGPR168 %VGPR169 %VGPR170 %VGPR171 %VGPR172 %VGPR173 %VGPR174 %VGPR175 %VGPR176 %VGPR177 %VGPR178 %VGPR179 %VGPR180 %VGPR181 %VGPR182 %VGPR183 %VGPR184 %VGPR185 %VGPR186 %VGPR187 %VGPR188 %VGPR189 %VGPR190 %VGPR191 %VGPR192 %VGPR193 %VGPR194 %VGPR195 %VGPR196 %VGPR197 %VGPR198 %VGPR199 %VGPR200 %VGPR201 %VGPR202 %VGPR203 %VGPR204 %VGPR205 %VGPR206 %VGPR207 %VGPR208 %VGPR209 %VGPR210 %VGPR211 %VGPR212 %VGPR213 %VGPR214 %VGPR215 %VGPR216 %VGPR217 %VGPR218 %VGPR219 %VGPR220 %VGPR221 %VGPR222 %VGPR223 %VGPR224 %VGPR225 %VGPR226 %VGPR227 %VGPR228 %VGPR229 %VGPR230 %VGPR231 %VGPR232 %VGPR233 %VGPR234 %VGPR235 %VGPR236 %VGPR237 %VGPR238 %VGPR239 %VGPR240 %VGPR241 %VGPR242 %VGPR243 %VGPR244 %VGPR245 %VGPR246 %VGPR247 %VGPR248 %VGPR249 %VGPR250 %VGPR251 %VGPR252 %VGPR253 %VGPR254 %VGPR255 ]
hints: %VGPR0
assigning %vreg445 to %VGPR0: VGPR0

selectOrSplit SReg_32:%vreg0 [16r,2224B:0)[2272B,2816r:0)[3408B,9808B:0)  0@16r w=2.643426e-04
AllocationOrder(SReg_32) = [ %SGPR0 %SGPR1 %SGPR2 %SGPR3 %SGPR4 %SGPR5 %SGPR6 %SGPR7 %SGPR8 %SGPR9 %SGPR10 %SGPR11 %SGPR12 %SGPR13 %SGPR14 %SGPR15 %SGPR16 %SGPR17 %SGPR18 %SGPR19 %SGPR20 %SGPR21 %SGPR22 %SGPR23 %SGPR24 %SGPR25 %SGPR26 %SGPR27 %SGPR28 %SGPR29 %SGPR30 %SGPR31 %SGPR32 %SGPR33 %SGPR34 %SGPR35 %SGPR36 %SGPR37 %SGPR38 %SGPR39 %SGPR40 %SGPR41 %SGPR42 %SGPR43 %SGPR44 %SGPR45 %SGPR46 %SGPR47 %SGPR48 %SGPR49 %SGPR50 %SGPR51 %SGPR52 %SGPR53 %SGPR54 %SGPR55 %SGPR56 %SGPR57 %SGPR58 %SGPR59 %SGPR60 %SGPR61 %SGPR62 %SGPR63 %SGPR64 %SGPR65 %SGPR66 %SGPR67 %SGPR68 %SGPR69 %SGPR70 %SGPR71 %SGPR72 %SGPR73 %SGPR74 %SGPR75 %SGPR76 %SGPR77 %SGPR78 %SGPR79 %SGPR80 %SGPR81 %SGPR82 %SGPR83 %SGPR84 %SGPR85 %SGPR86 %SGPR87 %SGPR88 %SGPR89 %SGPR90 %SGPR91 %SGPR92 %SGPR93 %SGPR94 %SGPR95 %SGPR96 %SGPR97 %SGPR98 %SGPR99 %SGPR100 %SGPR101 %M0 %VCC_LO ]
hints: %SGPR2
assigning %vreg0 to %SGPR2: SGPR2

selectOrSplit VReg_32:%vreg442 [64r,2224B:0)[2272B,2416r:0)[3408B,9808B:0)  0@64r w=2.773506e-04
hints: %VGPR1
assigning %vreg442 to %VGPR1: VGPR1

selectOrSplit SReg_32:%vreg4 [48r,2224B:0)[2272B,2384r:0)[3408B,9808B:0)  0@48r w=2.778389e-04
hints: %SGPR3
assigning %vreg4 to %SGPR3: SGPR3

selectOrSplit SReg_64:%vreg48 [80r,448r:0)  0@80r w=1.709635e-02
AllocationOrder(SReg_64) = [ %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR10_SGPR11 %SGPR12_SGPR13 %SGPR14_SGPR15 %SGPR16_SGPR17 %SGPR18_SGPR19 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %SGPR42_SGPR43 %SGPR44_SGPR45 %SGPR46_SGPR47 %SGPR48_SGPR49 %SGPR50_SGPR51 %SGPR52_SGPR53 %SGPR54_SGPR55 %SGPR56_SGPR57 %SGPR58_SGPR59 %SGPR60_SGPR61 %SGPR62_SGPR63 %SGPR64_SGPR65 %SGPR66_SGPR67 %SGPR68_SGPR69 %SGPR70_SGPR71 %SGPR72_SGPR73 %SGPR74_SGPR75 %SGPR76_SGPR77 %SGPR78_SGPR79 %SGPR80_SGPR81 %SGPR82_SGPR83 %SGPR84_SGPR85 %SGPR86_SGPR87 %SGPR88_SGPR89 %SGPR90_SGPR91 %SGPR92_SGPR93 %SGPR94_SGPR95 %SGPR96_SGPR97 %SGPR98_SGPR99 %SGPR100_SGPR101 %VCC ]
hints: %SGPR0_SGPR1
assigning %vreg48 to %SGPR0_SGPR1: SGPR0 SGPR1

selectOrSplit SReg_64:%vreg86 [464r,2240r:0)[2272B,11504B:0)  0@464r w=1.753156e-04
assigning %vreg86 to %SGPR0_SGPR1: SGPR0 SGPR1

selectOrSplit VReg_32:%vreg423 [144r,2224B:0)[2272B,10704r:0)  0@144r w=2.291056e-04
assigning %vreg423 to %VGPR2: VGPR2

selectOrSplit SReg_64_with_sub0:%vreg53 [384r,2224B:0)[2272B,10832r:0)  0@384r w=1.851852e-04
AllocationOrder(SReg_64_with_sub0) = [ %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR10_SGPR11 %SGPR12_SGPR13 %SGPR14_SGPR15 %SGPR16_SGPR17 %SGPR18_SGPR19 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %SGPR42_SGPR43 %SGPR44_SGPR45 %SGPR46_SGPR47 %SGPR48_SGPR49 %SGPR50_SGPR51 %SGPR52_SGPR53 %SGPR54_SGPR55 %SGPR56_SGPR57 %SGPR58_SGPR59 %SGPR60_SGPR61 %SGPR62_SGPR63 %SGPR64_SGPR65 %SGPR66_SGPR67 %SGPR68_SGPR69 %SGPR70_SGPR71 %SGPR72_SGPR73 %SGPR74_SGPR75 %SGPR76_SGPR77 %SGPR78_SGPR79 %SGPR80_SGPR81 %SGPR82_SGPR83 %SGPR84_SGPR85 %SGPR86_SGPR87 %SGPR88_SGPR89 %SGPR90_SGPR91 %SGPR92_SGPR93 %SGPR94_SGPR95 %SGPR96_SGPR97 %SGPR98_SGPR99 %SGPR100_SGPR101 %VCC ]
assigning %vreg53 to %SGPR4_SGPR5: SGPR4 SGPR5

selectOrSplit VReg_32:%vreg440 [256r,2224B:0)[2272B,10688r:0)  0@256r w=2.318249e-04
assigning %vreg440 to %VGPR3: VGPR3

selectOrSplit SGPR_32:%vreg54 [368r,2224B:0)[2272B,10672r:0)  0@368r w=1.421734e-04
AllocationOrder(SGPR_32) = [ %SGPR0 %SGPR1 %SGPR2 %SGPR3 %SGPR4 %SGPR5 %SGPR6 %SGPR7 %SGPR8 %SGPR9 %SGPR10 %SGPR11 %SGPR12 %SGPR13 %SGPR14 %SGPR15 %SGPR16 %SGPR17 %SGPR18 %SGPR19 %SGPR20 %SGPR21 %SGPR22 %SGPR23 %SGPR24 %SGPR25 %SGPR26 %SGPR27 %SGPR28 %SGPR29 %SGPR30 %SGPR31 %SGPR32 %SGPR33 %SGPR34 %SGPR35 %SGPR36 %SGPR37 %SGPR38 %SGPR39 %SGPR40 %SGPR41 %SGPR42 %SGPR43 %SGPR44 %SGPR45 %SGPR46 %SGPR47 %SGPR48 %SGPR49 %SGPR50 %SGPR51 %SGPR52 %SGPR53 %SGPR54 %SGPR55 %SGPR56 %SGPR57 %SGPR58 %SGPR59 %SGPR60 %SGPR61 %SGPR62 %SGPR63 %SGPR64 %SGPR65 %SGPR66 %SGPR67 %SGPR68 %SGPR69 %SGPR70 %SGPR71 %SGPR72 %SGPR73 %SGPR74 %SGPR75 %SGPR76 %SGPR77 %SGPR78 %SGPR79 %SGPR80 %SGPR81 %SGPR82 %SGPR83 %SGPR84 %SGPR85 %SGPR86 %SGPR87 %SGPR88 %SGPR89 %SGPR90 %SGPR91 %SGPR92 %SGPR93 %SGPR94 %SGPR95 %SGPR96 %SGPR97 %SGPR98 %SGPR99 %SGPR100 %SGPR101 ]
assigning %vreg54 to %SGPR6: SGPR6

selectOrSplit VGPR_32:%vreg856 [752r,864B:3)[1664r,2096B:5)[2096B,2224B:4)[2272B,3552B:0)[3552B,9280r:6)[9280r,9808B:4)[9808B,9872B:2)[9872B,10336r:7)[10336r,10656B:1)[10656B,10912r:2)  0@3408B-phi 1@10336r 2@9808B-phi 3@752r 4@9280r 5@1664r 6@3552B-phi 7@9872B-phi w=1.001545e-02
AllocationOrder(VGPR_32) = [ %VGPR0 %VGPR1 %VGPR2 %VGPR3 %VGPR4 %VGPR5 %VGPR6 %VGPR7 %VGPR8 %VGPR9 %VGPR10 %VGPR11 %VGPR12 %VGPR13 %VGPR14 %VGPR15 %VGPR16 %VGPR17 %VGPR18 %VGPR19 %VGPR20 %VGPR21 %VGPR22 %VGPR23 %VGPR24 %VGPR25 %VGPR26 %VGPR27 %VGPR28 %VGPR29 %VGPR30 %VGPR31 %VGPR32 %VGPR33 %VGPR34 %VGPR35 %VGPR36 %VGPR37 %VGPR38 %VGPR39 %VGPR40 %VGPR41 %VGPR42 %VGPR43 %VGPR44 %VGPR45 %VGPR46 %VGPR47 %VGPR48 %VGPR49 %VGPR50 %VGPR51 %VGPR52 %VGPR53 %VGPR54 %VGPR55 %VGPR56 %VGPR57 %VGPR58 %VGPR59 %VGPR60 %VGPR61 %VGPR62 %VGPR63 %VGPR64 %VGPR65 %VGPR66 %VGPR67 %VGPR68 %VGPR69 %VGPR70 %VGPR71 %VGPR72 %VGPR73 %VGPR74 %VGPR75 %VGPR76 %VGPR77 %VGPR78 %VGPR79 %VGPR80 %VGPR81 %VGPR82 %VGPR83 %VGPR84 %VGPR85 %VGPR86 %VGPR87 %VGPR88 %VGPR89 %VGPR90 %VGPR91 %VGPR92 %VGPR93 %VGPR94 %VGPR95 %VGPR96 %VGPR97 %VGPR98 %VGPR99 %VGPR100 %VGPR101 %VGPR102 %VGPR103 %VGPR104 %VGPR105 %VGPR106 %VGPR107 %VGPR108 %VGPR109 %VGPR110 %VGPR111 %VGPR112 %VGPR113 %VGPR114 %VGPR115 %VGPR116 %VGPR117 %VGPR118 %VGPR119 %VGPR120 %VGPR121 %VGPR122 %VGPR123 %VGPR124 %VGPR125 %VGPR126 %VGPR127 %VGPR128 %VGPR129 %VGPR130 %VGPR131 %VGPR132 %VGPR133 %VGPR134 %VGPR135 %VGPR136 %VGPR137 %VGPR138 %VGPR139 %VGPR140 %VGPR141 %VGPR142 %VGPR143 %VGPR144 %VGPR145 %VGPR146 %VGPR147 %VGPR148 %VGPR149 %VGPR150 %VGPR151 %VGPR152 %VGPR153 %VGPR154 %VGPR155 %VGPR156 %VGPR157 %VGPR158 %VGPR159 %VGPR160 %VGPR161 %VGPR162 %VGPR163 %VGPR164 %VGPR165 %VGPR166 %VGPR167 %VGPR168 %VGPR169 %VGPR170 %VGPR171 %VGPR172 %VGPR173 %VGPR174 %VGPR175 %VGPR176 %VGPR177 %VGPR178 %VGPR179 %VGPR180 %VGPR181 %VGPR182 %VGPR183 %VGPR184 %VGPR185 %VGPR186 %VGPR187 %VGPR188 %VGPR189 %VGPR190 %VGPR191 %VGPR192 %VGPR193 %VGPR194 %VGPR195 %VGPR196 %VGPR197 %VGPR198 %VGPR199 %VGPR200 %VGPR201 %VGPR202 %VGPR203 %VGPR204 %VGPR205 %VGPR206 %VGPR207 %VGPR208 %VGPR209 %VGPR210 %VGPR211 %VGPR212 %VGPR213 %VGPR214 %VGPR215 %VGPR216 %VGPR217 %VGPR218 %VGPR219 %VGPR220 %VGPR221 %VGPR222 %VGPR223 %VGPR224 %VGPR225 %VGPR226 %VGPR227 %VGPR228 %VGPR229 %VGPR230 %VGPR231 %VGPR232 %VGPR233 %VGPR234 %VGPR235 %VGPR236 %VGPR237 %VGPR238 %VGPR239 %VGPR240 %VGPR241 %VGPR242 %VGPR243 %VGPR244 %VGPR245 %VGPR246 %VGPR247 %VGPR248 %VGPR249 %VGPR250 %VGPR251 %VGPR252 %VGPR253 %VGPR254 %VGPR255 ]
assigning %vreg856 to %VGPR4: VGPR4

selectOrSplit SGPR_32:%vreg55 [352r,2224B:0)[2272B,3168r:0)[3408B,9808B:0)  0@352r w=2.639005e-04
assigning %vreg55 to %SGPR7: SGPR7

selectOrSplit SGPR_32:%vreg1 [112r,2224B:0)[2272B,2832r:0)[3408B,9808B:0)  0@112r w=2.639358e-04
assigning %vreg1 to %SGPR8: SGPR8

selectOrSplit SReg_64_with_sub0:%vreg51 [416r,2224B:0)[2272B,3088r:0)[3408B,9808B:0)  0@416r w=2.122241e-04
assigning %vreg51 to %SGPR10_SGPR11: SGPR10 SGPR11

selectOrSplit SGPR_32:%vreg52 [400r,2224B:0)[2272B,2864r:0)[3408B,9808B:0)  0@400r w=1.627604e-04
assigning %vreg52 to %SGPR9: SGPR9

selectOrSplit SReg_64_with_sub0:%vreg49 [448r,2224B:0)[2272B,2736r:0)[3408B,9808B:0)  0@448r w=2.212389e-04
assigning %vreg49 to %SGPR12_SGPR13: SGPR12 SGPR13

selectOrSplit SGPR_32:%vreg5 [224r,2224B:0)[2272B,2400r:0)[3408B,9808B:0)  0@224r w=2.800179e-04
assigning %vreg5 to %SGPR14: SGPR14

selectOrSplit SGPR_32:%vreg50 [432r,2224B:0)[2272B,2432r:0)[3408B,9808B:0)  0@432r w=1.713894e-04
assigning %vreg50 to %SGPR15: SGPR15

selectOrSplit SGPR_32:%vreg78 [336r,2224B:0)[3408B,3456r:0)[3552B,9808B:0)  0@336r w=1.763268e-04
assigning %vreg78 to %SGPR16: SGPR16

selectOrSplit SReg_64:%vreg92 [832r,2224B:0)[3408B,3504r:0)[3552B,9808B:0)  0@832r w=1.227898e-04
assigning %vreg92 to %SGPR18_SGPR19: SGPR18 SGPR19

selectOrSplit SReg_32:%vreg9 [688r,2096B:0)[3552B,9808B:0)  0@688r w=1.127512e-03
assigning %vreg9 to %SGPR17: SGPR17

selectOrSplit VReg_128:%vreg687 [1216r,1248r:2)[1248r,2096B:3)[3552B,9360r:0)[9360r,9392r:4)[9392r,9808B:5)  0@3552B-phi 1@x 2@1216r 3@1248r 4@9360r 5@9392r w=3.832626e-02
AllocationOrder(VReg_128) = [ %VGPR0_VGPR1_VGPR2_VGPR3 %VGPR1_VGPR2_VGPR3_VGPR4 %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR3_VGPR4_VGPR5_VGPR6 %VGPR4_VGPR5_VGPR6_VGPR7 %VGPR5_VGPR6_VGPR7_VGPR8 %VGPR6_VGPR7_VGPR8_VGPR9 %VGPR7_VGPR8_VGPR9_VGPR10 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR9_VGPR10_VGPR11_VGPR12 %VGPR10_VGPR11_VGPR12_VGPR13 %VGPR11_VGPR12_VGPR13_VGPR14 %VGPR12_VGPR13_VGPR14_VGPR15 %VGPR13_VGPR14_VGPR15_VGPR16 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR15_VGPR16_VGPR17_VGPR18 %VGPR16_VGPR17_VGPR18_VGPR19 %VGPR17_VGPR18_VGPR19_VGPR20 %VGPR18_VGPR19_VGPR20_VGPR21 %VGPR19_VGPR20_VGPR21_VGPR22 %VGPR20_VGPR21_VGPR22_VGPR23 %VGPR21_VGPR22_VGPR23_VGPR24 %VGPR22_VGPR23_VGPR24_VGPR25 %VGPR23_VGPR24_VGPR25_VGPR26 %VGPR24_VGPR25_VGPR26_VGPR27 %VGPR25_VGPR26_VGPR27_VGPR28 %VGPR26_VGPR27_VGPR28_VGPR29 %VGPR27_VGPR28_VGPR29_VGPR30 %VGPR28_VGPR29_VGPR30_VGPR31 %VGPR29_VGPR30_VGPR31_VGPR32 %VGPR30_VGPR31_VGPR32_VGPR33 %VGPR31_VGPR32_VGPR33_VGPR34 %VGPR32_VGPR33_VGPR34_VGPR35 %VGPR33_VGPR34_VGPR35_VGPR36 %VGPR34_VGPR35_VGPR36_VGPR37 %VGPR35_VGPR36_VGPR37_VGPR38 %VGPR36_VGPR37_VGPR38_VGPR39 %VGPR37_VGPR38_VGPR39_VGPR40 %VGPR38_VGPR39_VGPR40_VGPR41 %VGPR39_VGPR40_VGPR41_VGPR42 %VGPR40_VGPR41_VGPR42_VGPR43 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR42_VGPR43_VGPR44_VGPR45 %VGPR43_VGPR44_VGPR45_VGPR46 %VGPR44_VGPR45_VGPR46_VGPR47 %VGPR45_VGPR46_VGPR47_VGPR48 %VGPR46_VGPR47_VGPR48_VGPR49 %VGPR47_VGPR48_VGPR49_VGPR50 %VGPR48_VGPR49_VGPR50_VGPR51 %VGPR49_VGPR50_VGPR51_VGPR52 %VGPR50_VGPR51_VGPR52_VGPR53 %VGPR51_VGPR52_VGPR53_VGPR54 %VGPR52_VGPR53_VGPR54_VGPR55 %VGPR53_VGPR54_VGPR55_VGPR56 %VGPR54_VGPR55_VGPR56_VGPR57 %VGPR55_VGPR56_VGPR57_VGPR58 %VGPR56_VGPR57_VGPR58_VGPR59 %VGPR57_VGPR58_VGPR59_VGPR60 %VGPR58_VGPR59_VGPR60_VGPR61 %VGPR59_VGPR60_VGPR61_VGPR62 %VGPR60_VGPR61_VGPR62_VGPR63 %VGPR61_VGPR62_VGPR63_VGPR64 %VGPR62_VGPR63_VGPR64_VGPR65 %VGPR63_VGPR64_VGPR65_VGPR66 %VGPR64_VGPR65_VGPR66_VGPR67 %VGPR65_VGPR66_VGPR67_VGPR68 %VGPR66_VGPR67_VGPR68_VGPR69 %VGPR67_VGPR68_VGPR69_VGPR70 %VGPR68_VGPR69_VGPR70_VGPR71 %VGPR69_VGPR70_VGPR71_VGPR72 %VGPR70_VGPR71_VGPR72_VGPR73 %VGPR71_VGPR72_VGPR73_VGPR74 %VGPR72_VGPR73_VGPR74_VGPR75 %VGPR73_VGPR74_VGPR75_VGPR76 %VGPR74_VGPR75_VGPR76_VGPR77 %VGPR75_VGPR76_VGPR77_VGPR78 %VGPR76_VGPR77_VGPR78_VGPR79 %VGPR77_VGPR78_VGPR79_VGPR80 %VGPR78_VGPR79_VGPR80_VGPR81 %VGPR79_VGPR80_VGPR81_VGPR82 %VGPR80_VGPR81_VGPR82_VGPR83 %VGPR81_VGPR82_VGPR83_VGPR84 %VGPR82_VGPR83_VGPR84_VGPR85 %VGPR83_VGPR84_VGPR85_VGPR86 %VGPR84_VGPR85_VGPR86_VGPR87 %VGPR85_VGPR86_VGPR87_VGPR88 %VGPR86_VGPR87_VGPR88_VGPR89 %VGPR87_VGPR88_VGPR89_VGPR90 %VGPR88_VGPR89_VGPR90_VGPR91 %VGPR89_VGPR90_VGPR91_VGPR92 %VGPR90_VGPR91_VGPR92_VGPR93 %VGPR91_VGPR92_VGPR93_VGPR94 %VGPR92_VGPR93_VGPR94_VGPR95 %VGPR93_VGPR94_VGPR95_VGPR96 %VGPR94_VGPR95_VGPR96_VGPR97 %VGPR95_VGPR96_VGPR97_VGPR98 %VGPR96_VGPR97_VGPR98_VGPR99 %VGPR97_VGPR98_VGPR99_VGPR100 %VGPR98_VGPR99_VGPR100_VGPR101 %VGPR99_VGPR100_VGPR101_VGPR102 %VGPR100_VGPR101_VGPR102_VGPR103 %VGPR101_VGPR102_VGPR103_VGPR104 %VGPR102_VGPR103_VGPR104_VGPR105 %VGPR103_VGPR104_VGPR105_VGPR106 %VGPR104_VGPR105_VGPR106_VGPR107 %VGPR105_VGPR106_VGPR107_VGPR108 %VGPR106_VGPR107_VGPR108_VGPR109 %VGPR107_VGPR108_VGPR109_VGPR110 %VGPR108_VGPR109_VGPR110_VGPR111 %VGPR109_VGPR110_VGPR111_VGPR112 %VGPR110_VGPR111_VGPR112_VGPR113 %VGPR111_VGPR112_VGPR113_VGPR114 %VGPR112_VGPR113_VGPR114_VGPR115 %VGPR113_VGPR114_VGPR115_VGPR116 %VGPR114_VGPR115_VGPR116_VGPR117 %VGPR115_VGPR116_VGPR117_VGPR118 %VGPR116_VGPR117_VGPR118_VGPR119 %VGPR117_VGPR118_VGPR119_VGPR120 %VGPR118_VGPR119_VGPR120_VGPR121 %VGPR119_VGPR120_VGPR121_VGPR122 %VGPR120_VGPR121_VGPR122_VGPR123 %VGPR121_VGPR122_VGPR123_VGPR124 %VGPR122_VGPR123_VGPR124_VGPR125 %VGPR123_VGPR124_VGPR125_VGPR126 %VGPR124_VGPR125_VGPR126_VGPR127 %VGPR125_VGPR126_VGPR127_VGPR128 %VGPR126_VGPR127_VGPR128_VGPR129 %VGPR127_VGPR128_VGPR129_VGPR130 %VGPR128_VGPR129_VGPR130_VGPR131 %VGPR129_VGPR130_VGPR131_VGPR132 %VGPR130_VGPR131_VGPR132_VGPR133 %VGPR131_VGPR132_VGPR133_VGPR134 %VGPR132_VGPR133_VGPR134_VGPR135 %VGPR133_VGPR134_VGPR135_VGPR136 %VGPR134_VGPR135_VGPR136_VGPR137 %VGPR135_VGPR136_VGPR137_VGPR138 %VGPR136_VGPR137_VGPR138_VGPR139 %VGPR137_VGPR138_VGPR139_VGPR140 %VGPR138_VGPR139_VGPR140_VGPR141 %VGPR139_VGPR140_VGPR141_VGPR142 %VGPR140_VGPR141_VGPR142_VGPR143 %VGPR141_VGPR142_VGPR143_VGPR144 %VGPR142_VGPR143_VGPR144_VGPR145 %VGPR143_VGPR144_VGPR145_VGPR146 %VGPR144_VGPR145_VGPR146_VGPR147 %VGPR145_VGPR146_VGPR147_VGPR148 %VGPR146_VGPR147_VGPR148_VGPR149 %VGPR147_VGPR148_VGPR149_VGPR150 %VGPR148_VGPR149_VGPR150_VGPR151 %VGPR149_VGPR150_VGPR151_VGPR152 %VGPR150_VGPR151_VGPR152_VGPR153 %VGPR151_VGPR152_VGPR153_VGPR154 %VGPR152_VGPR153_VGPR154_VGPR155 %VGPR153_VGPR154_VGPR155_VGPR156 %VGPR154_VGPR155_VGPR156_VGPR157 %VGPR155_VGPR156_VGPR157_VGPR158 %VGPR156_VGPR157_VGPR158_VGPR159 %VGPR157_VGPR158_VGPR159_VGPR160 %VGPR158_VGPR159_VGPR160_VGPR161 %VGPR159_VGPR160_VGPR161_VGPR162 %VGPR160_VGPR161_VGPR162_VGPR163 %VGPR161_VGPR162_VGPR163_VGPR164 %VGPR162_VGPR163_VGPR164_VGPR165 %VGPR163_VGPR164_VGPR165_VGPR166 %VGPR164_VGPR165_VGPR166_VGPR167 %VGPR165_VGPR166_VGPR167_VGPR168 %VGPR166_VGPR167_VGPR168_VGPR169 %VGPR167_VGPR168_VGPR169_VGPR170 %VGPR168_VGPR169_VGPR170_VGPR171 %VGPR169_VGPR170_VGPR171_VGPR172 %VGPR170_VGPR171_VGPR172_VGPR173 %VGPR171_VGPR172_VGPR173_VGPR174 %VGPR172_VGPR173_VGPR174_VGPR175 %VGPR173_VGPR174_VGPR175_VGPR176 %VGPR174_VGPR175_VGPR176_VGPR177 %VGPR175_VGPR176_VGPR177_VGPR178 %VGPR176_VGPR177_VGPR178_VGPR179 %VGPR177_VGPR178_VGPR179_VGPR180 %VGPR178_VGPR179_VGPR180_VGPR181 %VGPR179_VGPR180_VGPR181_VGPR182 %VGPR180_VGPR181_VGPR182_VGPR183 %VGPR181_VGPR182_VGPR183_VGPR184 %VGPR182_VGPR183_VGPR184_VGPR185 %VGPR183_VGPR184_VGPR185_VGPR186 %VGPR184_VGPR185_VGPR186_VGPR187 %VGPR185_VGPR186_VGPR187_VGPR188 %VGPR186_VGPR187_VGPR188_VGPR189 %VGPR187_VGPR188_VGPR189_VGPR190 %VGPR188_VGPR189_VGPR190_VGPR191 %VGPR189_VGPR190_VGPR191_VGPR192 %VGPR190_VGPR191_VGPR192_VGPR193 %VGPR191_VGPR192_VGPR193_VGPR194 %VGPR192_VGPR193_VGPR194_VGPR195 %VGPR193_VGPR194_VGPR195_VGPR196 %VGPR194_VGPR195_VGPR196_VGPR197 %VGPR195_VGPR196_VGPR197_VGPR198 %VGPR196_VGPR197_VGPR198_VGPR199 %VGPR197_VGPR198_VGPR199_VGPR200 %VGPR198_VGPR199_VGPR200_VGPR201 %VGPR199_VGPR200_VGPR201_VGPR202 %VGPR200_VGPR201_VGPR202_VGPR203 %VGPR201_VGPR202_VGPR203_VGPR204 %VGPR202_VGPR203_VGPR204_VGPR205 %VGPR203_VGPR204_VGPR205_VGPR206 %VGPR204_VGPR205_VGPR206_VGPR207 %VGPR205_VGPR206_VGPR207_VGPR208 %VGPR206_VGPR207_VGPR208_VGPR209 %VGPR207_VGPR208_VGPR209_VGPR210 %VGPR208_VGPR209_VGPR210_VGPR211 %VGPR209_VGPR210_VGPR211_VGPR212 %VGPR210_VGPR211_VGPR212_VGPR213 %VGPR211_VGPR212_VGPR213_VGPR214 %VGPR212_VGPR213_VGPR214_VGPR215 %VGPR213_VGPR214_VGPR215_VGPR216 %VGPR214_VGPR215_VGPR216_VGPR217 %VGPR215_VGPR216_VGPR217_VGPR218 %VGPR216_VGPR217_VGPR218_VGPR219 %VGPR217_VGPR218_VGPR219_VGPR220 %VGPR218_VGPR219_VGPR220_VGPR221 %VGPR219_VGPR220_VGPR221_VGPR222 %VGPR220_VGPR221_VGPR222_VGPR223 %VGPR221_VGPR222_VGPR223_VGPR224 %VGPR222_VGPR223_VGPR224_VGPR225 %VGPR223_VGPR224_VGPR225_VGPR226 %VGPR224_VGPR225_VGPR226_VGPR227 %VGPR225_VGPR226_VGPR227_VGPR228 %VGPR226_VGPR227_VGPR228_VGPR229 %VGPR227_VGPR228_VGPR229_VGPR230 %VGPR228_VGPR229_VGPR230_VGPR231 %VGPR229_VGPR230_VGPR231_VGPR232 %VGPR230_VGPR231_VGPR232_VGPR233 %VGPR231_VGPR232_VGPR233_VGPR234 %VGPR232_VGPR233_VGPR234_VGPR235 %VGPR233_VGPR234_VGPR235_VGPR236 %VGPR234_VGPR235_VGPR236_VGPR237 %VGPR235_VGPR236_VGPR237_VGPR238 %VGPR236_VGPR237_VGPR238_VGPR239 %VGPR237_VGPR238_VGPR239_VGPR240 %VGPR238_VGPR239_VGPR240_VGPR241 %VGPR239_VGPR240_VGPR241_VGPR242 %VGPR240_VGPR241_VGPR242_VGPR243 %VGPR241_VGPR242_VGPR243_VGPR244 %VGPR242_VGPR243_VGPR244_VGPR245 %VGPR243_VGPR244_VGPR245_VGPR246 %VGPR244_VGPR245_VGPR246_VGPR247 %VGPR245_VGPR246_VGPR247_VGPR248 %VGPR246_VGPR247_VGPR248_VGPR249 %VGPR247_VGPR248_VGPR249_VGPR250 %VGPR248_VGPR249_VGPR250_VGPR251 %VGPR249_VGPR250_VGPR251_VGPR252 %VGPR250_VGPR251_VGPR252_VGPR253 %VGPR251_VGPR252_VGPR253_VGPR254 %VGPR252_VGPR253_VGPR254_VGPR255 ]
assigning %vreg687 to %VGPR5_VGPR6_VGPR7_VGPR8: VGPR5 VGPR6 VGPR7 VGPR8

selectOrSplit VReg_128:%vreg562 [1584r,1616r:2)[1616r,2096B:3)[3552B,9472r:0)[9472r,9504r:4)[9504r,9808B:5)  0@3552B-phi 1@x 2@1584r 3@1616r 4@9472r 5@9504r w=4.029445e-02
assigning %vreg562 to %VGPR9_VGPR10_VGPR11_VGPR12: VGPR9 VGPR10 VGPR11 VGPR12

selectOrSplit VReg_32:%vreg854 [1696r,2096B:0)[3552B,9568r:1)[9568r,9808B:2)  0@1696r 1@3552B-phi 2@9568r w=7.974199e-03
assigning %vreg854 to %VGPR13: VGPR13

selectOrSplit SReg_128:%vreg676 [1728r,1792r:1)[1792r,1808r:2)[1808r,2096B:3)[3552B,9808B:0)  0@3552B-phi 1@1728r 2@1792r 3@1808r w=3.663486e-02
AllocationOrder(SReg_128) = [ %SGPR0_SGPR1_SGPR2_SGPR3 %SGPR4_SGPR5_SGPR6_SGPR7 %SGPR8_SGPR9_SGPR10_SGPR11 %SGPR12_SGPR13_SGPR14_SGPR15 %SGPR16_SGPR17_SGPR18_SGPR19 %SGPR20_SGPR21_SGPR22_SGPR23 %SGPR24_SGPR25_SGPR26_SGPR27 %SGPR28_SGPR29_SGPR30_SGPR31 %SGPR32_SGPR33_SGPR34_SGPR35 %SGPR36_SGPR37_SGPR38_SGPR39 %SGPR40_SGPR41_SGPR42_SGPR43 %SGPR44_SGPR45_SGPR46_SGPR47 %SGPR48_SGPR49_SGPR50_SGPR51 %SGPR52_SGPR53_SGPR54_SGPR55 %SGPR56_SGPR57_SGPR58_SGPR59 %SGPR60_SGPR61_SGPR62_SGPR63 %SGPR64_SGPR65_SGPR66_SGPR67 %SGPR68_SGPR69_SGPR70_SGPR71 %SGPR72_SGPR73_SGPR74_SGPR75 %SGPR76_SGPR77_SGPR78_SGPR79 %SGPR80_SGPR81_SGPR82_SGPR83 %SGPR84_SGPR85_SGPR86_SGPR87 %SGPR88_SGPR89_SGPR90_SGPR91 %SGPR92_SGPR93_SGPR94_SGPR95 %SGPR96_SGPR97_SGPR98_SGPR99 ]
assigning %vreg676 to %SGPR20_SGPR21_SGPR22_SGPR23: SGPR20 SGPR21 SGPR22 SGPR23

selectOrSplit SGPR_64:%vreg183 [1824r,1840r:0)[1840r,2096B:1)[3552B,9808B:2)  0@1824r 1@1840r 2@3552B-phi w=2.442607e-03
AllocationOrder(SGPR_64) = [ %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR10_SGPR11 %SGPR12_SGPR13 %SGPR14_SGPR15 %SGPR16_SGPR17 %SGPR18_SGPR19 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %SGPR42_SGPR43 %SGPR44_SGPR45 %SGPR46_SGPR47 %SGPR48_SGPR49 %SGPR50_SGPR51 %SGPR52_SGPR53 %SGPR54_SGPR55 %SGPR56_SGPR57 %SGPR58_SGPR59 %SGPR60_SGPR61 %SGPR62_SGPR63 %SGPR64_SGPR65 %SGPR66_SGPR67 %SGPR68_SGPR69 %SGPR70_SGPR71 %SGPR72_SGPR73 %SGPR74_SGPR75 %SGPR76_SGPR77 %SGPR78_SGPR79 %SGPR80_SGPR81 %SGPR82_SGPR83 %SGPR84_SGPR85 %SGPR86_SGPR87 %SGPR88_SGPR89 %SGPR90_SGPR91 %SGPR92_SGPR93 %SGPR94_SGPR95 %SGPR96_SGPR97 %SGPR98_SGPR99 %SGPR100_SGPR101 ]
assigning %vreg183 to %SGPR24_SGPR25: SGPR24 SGPR25

selectOrSplit SGPR_64:%vreg195 [1856r,2096B:0)[3552B,4960r:2)[4960r,9808B:1)  0@1856r 1@4960r 2@3552B-phi w=9.412896e-03
assigning %vreg195 to %SGPR26_SGPR27: SGPR26 SGPR27

selectOrSplit SGPR_64:%vreg203 [1872r,2096B:0)[3552B,5472r:2)[5472r,9808B:1)  0@1872r 1@5472r 2@3552B-phi w=9.434792e-03
assigning %vreg203 to %SGPR28_SGPR29: SGPR28 SGPR29

selectOrSplit SGPR_64:%vreg211 [1888r,2096B:0)[3552B,5984r:2)[5984r,9808B:1)  0@1888r 1@5984r 2@3552B-phi w=9.456791e-03
assigning %vreg211 to %SGPR30_SGPR31: SGPR30 SGPR31

selectOrSplit SGPR_64:%vreg219 [1904r,2096B:0)[3552B,6496r:2)[6496r,9808B:1)  0@1904r 1@6496r 2@3552B-phi w=9.478893e-03
assigning %vreg219 to %SGPR32_SGPR33: SGPR32 SGPR33

selectOrSplit SGPR_64:%vreg227 [1920r,2096B:0)[3552B,7008r:2)[7008r,9808B:1)  0@1920r 1@7008r 2@3552B-phi w=9.501099e-03
assigning %vreg227 to %SGPR34_SGPR35: SGPR34 SGPR35

selectOrSplit SGPR_64:%vreg235 [1936r,2096B:0)[3552B,7520r:2)[7520r,9808B:1)  0@1936r 1@7520r 2@3552B-phi w=9.523408e-03
assigning %vreg235 to %SGPR36_SGPR37: SGPR36 SGPR37

selectOrSplit SGPR_64:%vreg243 [1952r,2096B:0)[3552B,8032r:2)[8032r,9808B:1)  0@1952r 1@8032r 2@3552B-phi w=9.545823e-03
assigning %vreg243 to %SGPR38_SGPR39: SGPR38 SGPR39

selectOrSplit SGPR_64:%vreg283 [1968r,2096B:0)[3552B,9808B:0)  0@1968r w=2.377617e-03
assigning %vreg283 to %SGPR40_SGPR41: SGPR40 SGPR41

selectOrSplit SReg_128:%vreg851 [2096B,2112r:2)[3552B,9600r:1)[9600r,9808B:2)  0@x 1@3552B-phi 2@9600r w=8.428229e-03
assigning %vreg851 to %SGPR44_SGPR45_SGPR46_SGPR47: SGPR44 SGPR45 SGPR46 SGPR47

selectOrSplit VGPR_32:%vreg56 [2272B,3408B:0)[3456r,3552B:0)[9808B,10912r:0)  0@3456r w=3.691521e-04
assigning %vreg56 to %VGPR5: VGPR5

selectOrSplit SReg_64:%vreg302 [2336r,3408B:0)[9808B,9840r:0)[9872B,10656B:0)  0@2336r w=4.370629e-04
assigning %vreg302 to %SGPR16_SGPR17: SGPR16 SGPR17

selectOrSplit VReg_64:%vreg459 [720r,864B:2)[2160r,2224B:3)[2272B,2528r:0)[2528r,3168r:1)[3408B,3552B:0)  0@3408B-phi 1@2528r 2@720r 3@2160r w=1.822600e-03
AllocationOrder(VReg_64) = [ %VGPR0_VGPR1 %VGPR1_VGPR2 %VGPR2_VGPR3 %VGPR3_VGPR4 %VGPR4_VGPR5 %VGPR5_VGPR6 %VGPR6_VGPR7 %VGPR7_VGPR8 %VGPR8_VGPR9 %VGPR9_VGPR10 %VGPR10_VGPR11 %VGPR11_VGPR12 %VGPR12_VGPR13 %VGPR13_VGPR14 %VGPR14_VGPR15 %VGPR15_VGPR16 %VGPR16_VGPR17 %VGPR17_VGPR18 %VGPR18_VGPR19 %VGPR19_VGPR20 %VGPR20_VGPR21 %VGPR21_VGPR22 %VGPR22_VGPR23 %VGPR23_VGPR24 %VGPR24_VGPR25 %VGPR25_VGPR26 %VGPR26_VGPR27 %VGPR27_VGPR28 %VGPR28_VGPR29 %VGPR29_VGPR30 %VGPR30_VGPR31 %VGPR31_VGPR32 %VGPR32_VGPR33 %VGPR33_VGPR34 %VGPR34_VGPR35 %VGPR35_VGPR36 %VGPR36_VGPR37 %VGPR37_VGPR38 %VGPR38_VGPR39 %VGPR39_VGPR40 %VGPR40_VGPR41 %VGPR41_VGPR42 %VGPR42_VGPR43 %VGPR43_VGPR44 %VGPR44_VGPR45 %VGPR45_VGPR46 %VGPR46_VGPR47 %VGPR47_VGPR48 %VGPR48_VGPR49 %VGPR49_VGPR50 %VGPR50_VGPR51 %VGPR51_VGPR52 %VGPR52_VGPR53 %VGPR53_VGPR54 %VGPR54_VGPR55 %VGPR55_VGPR56 %VGPR56_VGPR57 %VGPR57_VGPR58 %VGPR58_VGPR59 %VGPR59_VGPR60 %VGPR60_VGPR61 %VGPR61_VGPR62 %VGPR62_VGPR63 %VGPR63_VGPR64 %VGPR64_VGPR65 %VGPR65_VGPR66 %VGPR66_VGPR67 %VGPR67_VGPR68 %VGPR68_VGPR69 %VGPR69_VGPR70 %VGPR70_VGPR71 %VGPR71_VGPR72 %VGPR72_VGPR73 %VGPR73_VGPR74 %VGPR74_VGPR75 %VGPR75_VGPR76 %VGPR76_VGPR77 %VGPR77_VGPR78 %VGPR78_VGPR79 %VGPR79_VGPR80 %VGPR80_VGPR81 %VGPR81_VGPR82 %VGPR82_VGPR83 %VGPR83_VGPR84 %VGPR84_VGPR85 %VGPR85_VGPR86 %VGPR86_VGPR87 %VGPR87_VGPR88 %VGPR88_VGPR89 %VGPR89_VGPR90 %VGPR90_VGPR91 %VGPR91_VGPR92 %VGPR92_VGPR93 %VGPR93_VGPR94 %VGPR94_VGPR95 %VGPR95_VGPR96 %VGPR96_VGPR97 %VGPR97_VGPR98 %VGPR98_VGPR99 %VGPR99_VGPR100 %VGPR100_VGPR101 %VGPR101_VGPR102 %VGPR102_VGPR103 %VGPR103_VGPR104 %VGPR104_VGPR105 %VGPR105_VGPR106 %VGPR106_VGPR107 %VGPR107_VGPR108 %VGPR108_VGPR109 %VGPR109_VGPR110 %VGPR110_VGPR111 %VGPR111_VGPR112 %VGPR112_VGPR113 %VGPR113_VGPR114 %VGPR114_VGPR115 %VGPR115_VGPR116 %VGPR116_VGPR117 %VGPR117_VGPR118 %VGPR118_VGPR119 %VGPR119_VGPR120 %VGPR120_VGPR121 %VGPR121_VGPR122 %VGPR122_VGPR123 %VGPR123_VGPR124 %VGPR124_VGPR125 %VGPR125_VGPR126 %VGPR126_VGPR127 %VGPR127_VGPR128 %VGPR128_VGPR129 %VGPR129_VGPR130 %VGPR130_VGPR131 %VGPR131_VGPR132 %VGPR132_VGPR133 %VGPR133_VGPR134 %VGPR134_VGPR135 %VGPR135_VGPR136 %VGPR136_VGPR137 %VGPR137_VGPR138 %VGPR138_VGPR139 %VGPR139_VGPR140 %VGPR140_VGPR141 %VGPR141_VGPR142 %VGPR142_VGPR143 %VGPR143_VGPR144 %VGPR144_VGPR145 %VGPR145_VGPR146 %VGPR146_VGPR147 %VGPR147_VGPR148 %VGPR148_VGPR149 %VGPR149_VGPR150 %VGPR150_VGPR151 %VGPR151_VGPR152 %VGPR152_VGPR153 %VGPR153_VGPR154 %VGPR154_VGPR155 %VGPR155_VGPR156 %VGPR156_VGPR157 %VGPR157_VGPR158 %VGPR158_VGPR159 %VGPR159_VGPR160 %VGPR160_VGPR161 %VGPR161_VGPR162 %VGPR162_VGPR163 %VGPR163_VGPR164 %VGPR164_VGPR165 %VGPR165_VGPR166 %VGPR166_VGPR167 %VGPR167_VGPR168 %VGPR168_VGPR169 %VGPR169_VGPR170 %VGPR170_VGPR171 %VGPR171_VGPR172 %VGPR172_VGPR173 %VGPR173_VGPR174 %VGPR174_VGPR175 %VGPR175_VGPR176 %VGPR176_VGPR177 %VGPR177_VGPR178 %VGPR178_VGPR179 %VGPR179_VGPR180 %VGPR180_VGPR181 %VGPR181_VGPR182 %VGPR182_VGPR183 %VGPR183_VGPR184 %VGPR184_VGPR185 %VGPR185_VGPR186 %VGPR186_VGPR187 %VGPR187_VGPR188 %VGPR188_VGPR189 %VGPR189_VGPR190 %VGPR190_VGPR191 %VGPR191_VGPR192 %VGPR192_VGPR193 %VGPR193_VGPR194 %VGPR194_VGPR195 %VGPR195_VGPR196 %VGPR196_VGPR197 %VGPR197_VGPR198 %VGPR198_VGPR199 %VGPR199_VGPR200 %VGPR200_VGPR201 %VGPR201_VGPR202 %VGPR202_VGPR203 %VGPR203_VGPR204 %VGPR204_VGPR205 %VGPR205_VGPR206 %VGPR206_VGPR207 %VGPR207_VGPR208 %VGPR208_VGPR209 %VGPR209_VGPR210 %VGPR210_VGPR211 %VGPR211_VGPR212 %VGPR212_VGPR213 %VGPR213_VGPR214 %VGPR214_VGPR215 %VGPR215_VGPR216 %VGPR216_VGPR217 %VGPR217_VGPR218 %VGPR218_VGPR219 %VGPR219_VGPR220 %VGPR220_VGPR221 %VGPR221_VGPR222 %VGPR222_VGPR223 %VGPR223_VGPR224 %VGPR224_VGPR225 %VGPR225_VGPR226 %VGPR226_VGPR227 %VGPR227_VGPR228 %VGPR228_VGPR229 %VGPR229_VGPR230 %VGPR230_VGPR231 %VGPR231_VGPR232 %VGPR232_VGPR233 %VGPR233_VGPR234 %VGPR234_VGPR235 %VGPR235_VGPR236 %VGPR236_VGPR237 %VGPR237_VGPR238 %VGPR238_VGPR239 %VGPR239_VGPR240 %VGPR240_VGPR241 %VGPR241_VGPR242 %VGPR242_VGPR243 %VGPR243_VGPR244 %VGPR244_VGPR245 %VGPR245_VGPR246 %VGPR246_VGPR247 %VGPR247_VGPR248 %VGPR248_VGPR249 %VGPR249_VGPR250 %VGPR250_VGPR251 %VGPR251_VGPR252 %VGPR252_VGPR253 %VGPR253_VGPR254 %VGPR254_VGPR255 ]
assigning %vreg459 to %VGPR6_VGPR7: VGPR6 VGPR7

selectOrSplit VReg_64:%vreg858 [2752r,2768r:0)[2768r,3408B:1)[9872B,10304r:3)[10496r,10592B:2)  0@2752r 1@2768r 2@10496r 3@9872B-phi w=3.112358e-02
assigning %vreg858 to %VGPR8_VGPR9: VGPR8 VGPR9

selectOrSplit VReg_32:%vreg860 [3168r,3408B:0)[9872B,10352r:1)[10352r,10592B:2)  0@3168r 1@9872B-phi 2@10352r w=4.142121e-02
assigning %vreg860 to %VGPR0: VGPR0

selectOrSplit SReg_128:%vreg366 [3184r,3264r:0)[3264r,3280r:2)[3280r,3408B:3)[9872B,10592B:1)  0@3184r 1@9872B-phi 2@3264r 3@3280r w=1.285395e-02
assigning %vreg366 to %SGPR8_SGPR9_SGPR10_SGPR11: SGPR8 SGPR9 SGPR10 SGPR11

selectOrSplit SGPR_64:%vreg353 [3248r,3408B:0)[9872B,10592B:0)  0@3248r w=1.261737e-02
assigning %vreg353 to %SGPR2_SGPR3: SGPR2 SGPR3

selectOrSplit VReg_64:%vreg859 [3104r,3120r:0)[3120r,3408B:1)[9872B,10288r:3)[10512r,10592B:2)  0@3104r 1@3120r 2@10512r 3@9872B-phi w=4.109975e-02
assigning %vreg859 to %VGPR10_VGPR11: VGPR10 VGPR11

selectOrSplit SReg_128:%vreg857 [9872B,10384r:1)[10384r,10608r:2)  0@x 1@9872B-phi 2@10384r w=4.942882e-02
assigning %vreg857 to %SGPR12_SGPR13_SGPR14_SGPR15: SGPR12 SGPR13 SGPR14 SGPR15

selectOrSplit VReg_64:%vreg45 [10848r,10864r:0)[10864r,11248r:1)[11280B,11456B:1)  0@10848r 1@10864r w=2.049180e-03
assigning %vreg45 to %VGPR0_VGPR1: VGPR0 VGPR1

selectOrSplit SReg_64:%vreg395 [11008r,11072r:0)[11072r,11280B:1)[11280B,11456B:0)[11456B,11472r:1)  0@11008r 1@11072r w=2.314815e-03
assigning %vreg395 to %SGPR2_SGPR3: SGPR2 SGPR3

selectOrSplit VGPR_32:%vreg388 [10912r,11040B:0)[11280B,11424r:0)  0@10912r w=2.604167e-03
assigning %vreg388 to %VGPR2: VGPR2

selectOrSplit VGPR_32:%vreg61 [96r,128r:0)  0@96r w=4.675926e-03
assigning %vreg61 to %VGPR2: VGPR2

selectOrSplit VReg_32:%vreg63 [128r,144r:0)  0@128r w=inf
assigning %vreg63 to %VGPR2: VGPR2

selectOrSplit SGPR_32:%vreg66 [160r,176r:0)  0@160r w=inf
assigning %vreg66 to %SGPR4: SGPR4

selectOrSplit VGPR_32:%vreg67 [176r,192r:0)  0@176r w=inf
assigning %vreg67 to %VGPR3: VGPR3

selectOrSplit SReg_64:%vreg68 [192r,320r:0)  0@192r w=3.787879e-03
assigning %vreg68 to %SGPR4_SGPR5: SGPR4 SGPR5

selectOrSplit VGPR_32:%vreg69 [208r,240r:0)  0@208r w=4.675926e-03
assigning %vreg69 to %VGPR3: VGPR3

selectOrSplit VReg_32:%vreg71 [240r,256r:0)  0@240r w=inf
assigning %vreg71 to %VGPR3: VGPR3

selectOrSplit SGPR_32:%vreg74 [272r,288r:0)  0@272r w=inf
assigning %vreg74 to %SGPR6: SGPR6

selectOrSplit VGPR_32:%vreg75 [288r,304r:0)  0@288r w=inf
assigning %vreg75 to %VGPR4: VGPR4

selectOrSplit SReg_64:%vreg76 [304r,320r:0)  0@304r w=inf
assigning %vreg76 to %SGPR6_SGPR7: SGPR6 SGPR7

selectOrSplit SReg_64:%vreg77 [320r,464r:0)  0@320r w=3.676471e-03
assigning %vreg77 to %SGPR18_SGPR19: SGPR18 SGPR19

selectOrSplit SReg_64:%vreg89 [704r,832r:0)  0@704r w=1.893939e-03
assigning %vreg89 to %SGPR18_SGPR19: SGPR18 SGPR19

selectOrSplit VGPR_32:%vreg96 [880r,896r:0)  0@880r w=inf
assigning %vreg96 to %VGPR4: VGPR4

selectOrSplit VReg_32:%vreg97 [896r,912r:0)  0@896r w=inf
assigning %vreg97 to %VGPR4: VGPR4

selectOrSplit VGPR_32:%vreg443 [912r,928r:0)  0@912r w=inf
assigning %vreg443 to %VGPR4: VGPR4

selectOrSplit VReg_64:%vreg104 [928r,944r:0)[944r,992r:1)  0@928r 1@944r w=inf
assigning %vreg104 to %VGPR4_VGPR5: VGPR4 VGPR5

selectOrSplit VReg_64:%vreg499 [992r,1088r:0)  0@992r w=1.512097e-03
assigning %vreg499 to %VGPR4_VGPR5: VGPR4 VGPR5

selectOrSplit VReg_32:%vreg516 [1040r,1072r:0)  0@1040r w=1.157407e-03
assigning %vreg516 to %VGPR6: VGPR6

selectOrSplit VReg_32:%vreg517 [1056r,1088r:0)  0@1056r w=1.157407e-03
assigning %vreg517 to %VGPR7: VGPR7

selectOrSplit VReg_64:%vreg503 [1072r,1088r:0)[1088r,1248r:1)  0@1072r 1@1088r w=2.170139e-03
assigning %vreg503 to %VGPR9_VGPR10: VGPR9 VGPR10

selectOrSplit SGPR_64:%vreg116 [1168r,1600r:0)  0@1168r w=7.512019e-04
assigning %vreg116 to %SGPR20_SGPR21: SGPR20 SGPR21

selectOrSplit VReg_32:%vreg508 [1232r,1248r:0)  0@1232r w=inf
assigning %vreg508 to %VGPR4: VGPR4

selectOrSplit VGPR_32:%vreg122 [1296r,1312r:0)  0@1296r w=inf
assigning %vreg122 to %VGPR4: VGPR4

selectOrSplit VReg_32:%vreg123 [1312r,1328r:0)  0@1312r w=inf
assigning %vreg123 to %VGPR4: VGPR4

selectOrSplit VGPR_32:%vreg446 [1328r,1344r:0)  0@1328r w=inf
assigning %vreg446 to %VGPR4: VGPR4

selectOrSplit VReg_64:%vreg130 [1344r,1360r:0)[1360r,1408r:1)  0@1344r 1@1360r w=inf
assigning %vreg130 to %VGPR9_VGPR10: VGPR9 VGPR10

selectOrSplit VReg_64:%vreg522 [1408r,1504r:0)  0@1408r w=1.512097e-03
assigning %vreg522 to %VGPR9_VGPR10: VGPR9 VGPR10

selectOrSplit VReg_32:%vreg539 [1456r,1488r:0)  0@1456r w=1.157407e-03
assigning %vreg539 to %VGPR4: VGPR4

selectOrSplit VReg_32:%vreg540 [1472r,1504r:0)  0@1472r w=1.157407e-03
assigning %vreg540 to %VGPR11: VGPR11

selectOrSplit VReg_64:%vreg526 [1488r,1504r:0)[1504r,1616r:1)  0@1488r 1@1504r w=2.367424e-03
assigning %vreg526 to %VGPR13_VGPR14: VGPR13 VGPR14

selectOrSplit VReg_32:%vreg531 [1600r,1616r:0)  0@1600r w=inf
assigning %vreg531 to %VGPR4: VGPR4

selectOrSplit SReg_32:%vreg299 [2128r,2144r:0)  0@2128r w=inf
assigning %vreg299 to %SGPR17: SGPR17

selectOrSplit SReg_32:%vreg13 [2144r,2160r:0)  0@2144r w=inf
assigning %vreg13 to %SGPR17: SGPR17

selectOrSplit VGPR_32:%vreg300 [2288r,2304r:0)  0@2288r w=inf
assigning %vreg300 to %VGPR8: VGPR8

selectOrSplit SReg_64:%vreg301 [2304r,2336r:0)  0@2304r w=inf
assigning %vreg301 to %SGPR16_SGPR17: SGPR16 SGPR17

selectOrSplit VGPR_32:%vreg304 [2384r,2400r:0)  0@2384r w=inf
assigning %vreg304 to %VGPR8: VGPR8

selectOrSplit VReg_32:%vreg305 [2400r,2416r:0)  0@2400r w=inf
assigning %vreg305 to %VGPR8: VGPR8

selectOrSplit VGPR_32:%vreg444 [2416r,2432r:0)  0@2416r w=inf
assigning %vreg444 to %VGPR1: VGPR1

selectOrSplit VReg_64:%vreg312 [2432r,2448r:0)[2448r,2624r:1)  0@2432r 1@2448r w=2.111486e-03
assigning %vreg312 to %VGPR8_VGPR9: VGPR8 VGPR9

selectOrSplit VReg_64:%vreg479 [2608r,2624r:0)[2624r,2672r:1)  0@2608r 1@2624r w=inf
assigning %vreg479 to %VGPR10_VGPR11: VGPR10 VGPR11

selectOrSplit VReg_64:%vreg482 [2672r,2768r:0)  0@2672r w=1.512097e-03
assigning %vreg482 to %VGPR10_VGPR11: VGPR10 VGPR11

selectOrSplit VReg_32:%vreg551 [2720r,2752r:0)  0@2720r w=1.157407e-03
assigning %vreg551 to %VGPR1: VGPR1

selectOrSplit VReg_32:%vreg552 [2736r,2768r:0)  0@2736r w=1.157407e-03
assigning %vreg552 to %VGPR12: VGPR12

selectOrSplit VGPR_32:%vreg330 [2816r,2832r:0)  0@2816r w=inf
assigning %vreg330 to %VGPR1: VGPR1

selectOrSplit VReg_32:%vreg331 [2832r,2848r:0)  0@2832r w=inf
assigning %vreg331 to %VGPR1: VGPR1

selectOrSplit VGPR_32:%vreg447 [2848r,2864r:0)  0@2848r w=inf
assigning %vreg447 to %VGPR0: VGPR0

selectOrSplit VReg_64:%vreg338 [2864r,2880r:0)[2880r,2976r:1)  0@2864r 1@2880r w=2.441406e-03
assigning %vreg338 to %VGPR0_VGPR1: VGPR0 VGPR1

selectOrSplit VReg_64:%vreg465 [2960r,2976r:0)[2976r,3024r:1)  0@2960r 1@2976r w=inf
assigning %vreg465 to %VGPR10_VGPR11: VGPR10 VGPR11

selectOrSplit VReg_64:%vreg468 [3024r,3120r:0)  0@3024r w=1.512097e-03
assigning %vreg468 to %VGPR0_VGPR1: VGPR0 VGPR1

selectOrSplit VReg_32:%vreg558 [3072r,3104r:0)  0@3072r w=1.157407e-03
assigning %vreg558 to %VGPR10: VGPR10

selectOrSplit VReg_32:%vreg559 [3088r,3120r:0)  0@3088r w=1.157407e-03
assigning %vreg559 to %VGPR12: VGPR12

selectOrSplit VReg_32:%vreg149 [3712r,3744r:0)  0@3712r w=3.703704e-02
assigning %vreg149 to %VGPR14: VGPR14

selectOrSplit VGPR_32:%vreg150 [3728r,3744r:0)  0@3728r w=inf
assigning %vreg150 to %VGPR15: VGPR15

selectOrSplit VGPR_32:%vreg151 [3744r,3760r:0)  0@3744r w=inf
assigning %vreg151 to %VGPR14: VGPR14

selectOrSplit VReg_512:%vreg250 [3760r,3824r:0)[3824r,3888r:1)[3888r,3952r:2)[3952r,4016r:3)[4016r,4080r:4)[4080r,4144r:5)[4144r,4208r:6)[4208r,4928r:7)[4928r,5440r:8)[5440r,5952r:9)[5952r,6464r:10)[6464r,6976r:11)[6976r,7488r:12)[7488r,8000r:13)[8000r,8512r:14)[8512r,9264r:15)  0@3760r 1@3824r 2@3888r 3@3952r 4@4016r 5@4080r 6@4144r 7@4208r 8@4928r 9@5440r 10@5952r 11@6464r 12@6976r 13@7488r 14@8000r 15@8512r w=6.233062e-02
AllocationOrder(VReg_512) = [ %VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15 %VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16 %VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18 %VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19 %VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20 %VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21 %VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22 %VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23 %VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24 %VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25 %VGPR11_VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26 %VGPR12_VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27 %VGPR13_VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28 %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29 %VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30 %VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31 %VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32 %VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33 %VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34 %VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35 %VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36 %VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37 %VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38 %VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39 %VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40 %VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41 %VGPR27_VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42 %VGPR28_VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43 %VGPR29_VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44 %VGPR30_VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45 %VGPR31_VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46 %VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47 %VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48 %VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49 %VGPR35_VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50 %VGPR36_VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51 %VGPR37_VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52 %VGPR38_VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53 %VGPR39_VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54 %VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55 %VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56 %VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57 %VGPR43_VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58 %VGPR44_VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59 %VGPR45_VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60 %VGPR46_VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61 %VGPR47_VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62 %VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63 %VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64 %VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65 %VGPR51_VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66 %VGPR52_VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67 %VGPR53_VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68 %VGPR54_VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69 %VGPR55_VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70 %VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71 %VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72 %VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73 %VGPR59_VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74 %VGPR60_VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75 %VGPR61_VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76 %VGPR62_VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77 %VGPR63_VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78 %VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79 %VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80 %VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81 %VGPR67_VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82 %VGPR68_VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83 %VGPR69_VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84 %VGPR70_VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85 %VGPR71_VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86 %VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87 %VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88 %VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89 %VGPR75_VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90 %VGPR76_VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91 %VGPR77_VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92 %VGPR78_VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93 %VGPR79_VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94 %VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87_VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95 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%VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175 %VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176 %VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177 %VGPR163_VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178 %VGPR164_VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179 %VGPR165_VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180 %VGPR166_VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181 %VGPR167_VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182 %VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183 %VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184 %VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185 %VGPR171_VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186 %VGPR172_VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187 %VGPR173_VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188 %VGPR174_VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189 %VGPR175_VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190 %VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191 %VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192 %VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193 %VGPR179_VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194 %VGPR180_VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195 %VGPR181_VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196 %VGPR182_VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197 %VGPR183_VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198 %VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199 %VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200 %VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201 %VGPR187_VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202 %VGPR188_VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203 %VGPR189_VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204 %VGPR190_VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205 %VGPR191_VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206 %VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207 %VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208 %VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209 %VGPR195_VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210 %VGPR196_VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211 %VGPR197_VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212 %VGPR198_VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213 %VGPR199_VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214 %VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215 %VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216 %VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217 %VGPR203_VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218 %VGPR204_VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219 %VGPR205_VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220 %VGPR206_VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221 %VGPR207_VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222 %VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223 %VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224 %VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225 %VGPR211_VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226 %VGPR212_VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227 %VGPR213_VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228 %VGPR214_VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229 %VGPR215_VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230 %VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231 %VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232 %VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233 %VGPR219_VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234 %VGPR220_VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235 %VGPR221_VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236 %VGPR222_VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237 %VGPR223_VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238 %VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239 %VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240 %VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241 %VGPR227_VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242 %VGPR228_VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243 %VGPR229_VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244 %VGPR230_VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245 %VGPR231_VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246 %VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247 %VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248 %VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249 %VGPR235_VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250 %VGPR236_VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251 %VGPR237_VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252 %VGPR238_VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253 %VGPR239_VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254 %VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255 ]
assigning %vreg250 to %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29: VGPR14 VGPR15 VGPR16 VGPR17 VGPR18 VGPR19 VGPR20 VGPR21 VGPR22 VGPR23 VGPR24 VGPR25 VGPR26 VGPR27 VGPR28 VGPR29

selectOrSplit VReg_32:%vreg153 [3776r,3808r:0)  0@3776r w=3.703704e-02
assigning %vreg153 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg154 [3792r,3808r:0)  0@3792r w=inf
assigning %vreg154 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg155 [3808r,3824r:0)  0@3808r w=inf
assigning %vreg155 to %VGPR30: VGPR30

selectOrSplit VReg_32:%vreg157 [3840r,3872r:0)  0@3840r w=3.703704e-02
assigning %vreg157 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg158 [3856r,3872r:0)  0@3856r w=inf
assigning %vreg158 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg159 [3872r,3888r:0)  0@3872r w=inf
assigning %vreg159 to %VGPR30: VGPR30

selectOrSplit VReg_32:%vreg161 [3904r,3936r:0)  0@3904r w=3.703704e-02
assigning %vreg161 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg162 [3920r,3936r:0)  0@3920r w=inf
assigning %vreg162 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg163 [3936r,3952r:0)  0@3936r w=inf
assigning %vreg163 to %VGPR30: VGPR30

selectOrSplit VReg_32:%vreg165 [3968r,4000r:0)  0@3968r w=3.703704e-02
assigning %vreg165 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg166 [3984r,4000r:0)  0@3984r w=inf
assigning %vreg166 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg167 [4000r,4016r:0)  0@4000r w=inf
assigning %vreg167 to %VGPR30: VGPR30

selectOrSplit VReg_32:%vreg169 [4032r,4064r:0)  0@4032r w=3.703704e-02
assigning %vreg169 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg170 [4048r,4064r:0)  0@4048r w=inf
assigning %vreg170 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg171 [4064r,4080r:0)  0@4064r w=inf
assigning %vreg171 to %VGPR30: VGPR30

selectOrSplit VReg_32:%vreg173 [4096r,4128r:0)  0@4096r w=3.703704e-02
assigning %vreg173 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg174 [4112r,4128r:0)  0@4112r w=inf
assigning %vreg174 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg175 [4128r,4144r:0)  0@4128r w=inf
assigning %vreg175 to %VGPR30: VGPR30

selectOrSplit VReg_32:%vreg177 [4160r,4192r:0)  0@4160r w=3.703704e-02
assigning %vreg177 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg178 [4176r,4192r:0)  0@4176r w=inf
assigning %vreg178 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg179 [4192r,4208r:0)  0@4192r w=inf
assigning %vreg179 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg683 [4336r,4496r:0)  0@4336r w=4.328571e-02
assigning %vreg683 to %VGPR30_VGPR31: VGPR30 VGPR31

selectOrSplit VReg_64:%vreg672 [4480r,4496r:0)[4496r,4592r:1)  0@4480r 1@4496r w=inf
assigning %vreg672 to %VGPR32_VGPR33: VGPR32 VGPR33

selectOrSplit VReg_32:%vreg186 [4592r,4912r:0)  0@4592r w=2.222222e-02
assigning %vreg186 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg808 [4688r,4848r:0)  0@4688r w=4.328571e-02
assigning %vreg808 to %VGPR31_VGPR32: VGPR31 VGPR32

selectOrSplit VReg_64:%vreg797 [4832r,4848r:0)[4848r,4896r:1)  0@4832r 1@4848r w=inf
assigning %vreg797 to %VGPR33_VGPR34: VGPR33 VGPR34

selectOrSplit VGPR_32:%vreg190 [4896r,4912r:0)  0@4896r w=inf
assigning %vreg190 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg192 [4912r,4928r:0)  0@4912r w=inf
assigning %vreg192 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg668 [4976r,5136r:0)  0@4976r w=4.328571e-02
assigning %vreg668 to %VGPR30_VGPR31: VGPR30 VGPR31

selectOrSplit VReg_64:%vreg657 [5120r,5136r:0)[5136r,5184r:1)  0@5120r 1@5136r w=inf
assigning %vreg657 to %VGPR32_VGPR33: VGPR32 VGPR33

selectOrSplit VReg_32:%vreg196 [5184r,5424r:0)  0@5184r w=2.500000e-02
assigning %vreg196 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg793 [5200r,5360r:0)  0@5200r w=4.328571e-02
assigning %vreg793 to %VGPR31_VGPR32: VGPR31 VGPR32

selectOrSplit VReg_64:%vreg782 [5344r,5360r:0)[5360r,5408r:1)  0@5344r 1@5360r w=inf
assigning %vreg782 to %VGPR33_VGPR34: VGPR33 VGPR34

selectOrSplit VGPR_32:%vreg198 [5408r,5424r:0)  0@5408r w=inf
assigning %vreg198 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg200 [5424r,5440r:0)  0@5424r w=inf
assigning %vreg200 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg653 [5488r,5648r:0)  0@5488r w=4.328571e-02
assigning %vreg653 to %VGPR30_VGPR31: VGPR30 VGPR31

selectOrSplit VReg_64:%vreg642 [5632r,5648r:0)[5648r,5696r:1)  0@5632r 1@5648r w=inf
assigning %vreg642 to %VGPR32_VGPR33: VGPR32 VGPR33

selectOrSplit VReg_32:%vreg204 [5696r,5936r:0)  0@5696r w=2.500000e-02
assigning %vreg204 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg778 [5712r,5872r:0)  0@5712r w=4.328571e-02
assigning %vreg778 to %VGPR31_VGPR32: VGPR31 VGPR32

selectOrSplit VReg_64:%vreg767 [5856r,5872r:0)[5872r,5920r:1)  0@5856r 1@5872r w=inf
assigning %vreg767 to %VGPR33_VGPR34: VGPR33 VGPR34

selectOrSplit VGPR_32:%vreg206 [5920r,5936r:0)  0@5920r w=inf
assigning %vreg206 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg208 [5936r,5952r:0)  0@5936r w=inf
assigning %vreg208 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg638 [6000r,6160r:0)  0@6000r w=4.328571e-02
assigning %vreg638 to %VGPR30_VGPR31: VGPR30 VGPR31

selectOrSplit VReg_64:%vreg627 [6144r,6160r:0)[6160r,6208r:1)  0@6144r 1@6160r w=inf
assigning %vreg627 to %VGPR32_VGPR33: VGPR32 VGPR33

selectOrSplit VReg_32:%vreg212 [6208r,6448r:0)  0@6208r w=2.500000e-02
assigning %vreg212 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg763 [6224r,6384r:0)  0@6224r w=4.328571e-02
assigning %vreg763 to %VGPR31_VGPR32: VGPR31 VGPR32

selectOrSplit VReg_64:%vreg752 [6368r,6384r:0)[6384r,6432r:1)  0@6368r 1@6384r w=inf
assigning %vreg752 to %VGPR33_VGPR34: VGPR33 VGPR34

selectOrSplit VGPR_32:%vreg214 [6432r,6448r:0)  0@6432r w=inf
assigning %vreg214 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg216 [6448r,6464r:0)  0@6448r w=inf
assigning %vreg216 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg623 [6512r,6672r:0)  0@6512r w=4.328571e-02
assigning %vreg623 to %VGPR30_VGPR31: VGPR30 VGPR31

selectOrSplit VReg_64:%vreg612 [6656r,6672r:0)[6672r,6720r:1)  0@6656r 1@6672r w=inf
assigning %vreg612 to %VGPR32_VGPR33: VGPR32 VGPR33

selectOrSplit VReg_32:%vreg220 [6720r,6960r:0)  0@6720r w=2.500000e-02
assigning %vreg220 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg748 [6736r,6896r:0)  0@6736r w=4.328571e-02
assigning %vreg748 to %VGPR31_VGPR32: VGPR31 VGPR32

selectOrSplit VReg_64:%vreg737 [6880r,6896r:0)[6896r,6944r:1)  0@6880r 1@6896r w=inf
assigning %vreg737 to %VGPR33_VGPR34: VGPR33 VGPR34

selectOrSplit VGPR_32:%vreg222 [6944r,6960r:0)  0@6944r w=inf
assigning %vreg222 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg224 [6960r,6976r:0)  0@6960r w=inf
assigning %vreg224 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg608 [7024r,7184r:0)  0@7024r w=4.328571e-02
assigning %vreg608 to %VGPR30_VGPR31: VGPR30 VGPR31

selectOrSplit VReg_64:%vreg597 [7168r,7184r:0)[7184r,7232r:1)  0@7168r 1@7184r w=inf
assigning %vreg597 to %VGPR32_VGPR33: VGPR32 VGPR33

selectOrSplit VReg_32:%vreg228 [7232r,7472r:0)  0@7232r w=2.500000e-02
assigning %vreg228 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg733 [7248r,7408r:0)  0@7248r w=4.328571e-02
assigning %vreg733 to %VGPR31_VGPR32: VGPR31 VGPR32

selectOrSplit VReg_64:%vreg722 [7392r,7408r:0)[7408r,7456r:1)  0@7392r 1@7408r w=inf
assigning %vreg722 to %VGPR33_VGPR34: VGPR33 VGPR34

selectOrSplit VGPR_32:%vreg230 [7456r,7472r:0)  0@7456r w=inf
assigning %vreg230 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg232 [7472r,7488r:0)  0@7472r w=inf
assigning %vreg232 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg593 [7536r,7696r:0)  0@7536r w=4.328571e-02
assigning %vreg593 to %VGPR30_VGPR31: VGPR30 VGPR31

selectOrSplit VReg_64:%vreg582 [7680r,7696r:0)[7696r,7744r:1)  0@7680r 1@7696r w=inf
assigning %vreg582 to %VGPR32_VGPR33: VGPR32 VGPR33

selectOrSplit VReg_32:%vreg236 [7744r,7984r:0)  0@7744r w=2.500000e-02
assigning %vreg236 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg718 [7760r,7920r:0)  0@7760r w=4.328571e-02
assigning %vreg718 to %VGPR31_VGPR32: VGPR31 VGPR32

selectOrSplit VReg_64:%vreg707 [7904r,7920r:0)[7920r,7968r:1)  0@7904r 1@7920r w=inf
assigning %vreg707 to %VGPR33_VGPR34: VGPR33 VGPR34

selectOrSplit VGPR_32:%vreg238 [7968r,7984r:0)  0@7968r w=inf
assigning %vreg238 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg240 [7984r,8000r:0)  0@7984r w=inf
assigning %vreg240 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg578 [8048r,8208r:0)  0@8048r w=4.328571e-02
assigning %vreg578 to %VGPR30_VGPR31: VGPR30 VGPR31

selectOrSplit VReg_64:%vreg567 [8192r,8208r:0)[8208r,8256r:1)  0@8192r 1@8208r w=inf
assigning %vreg567 to %VGPR32_VGPR33: VGPR32 VGPR33

selectOrSplit VReg_32:%vreg244 [8256r,8496r:0)  0@8256r w=2.500000e-02
assigning %vreg244 to %VGPR30: VGPR30

selectOrSplit VReg_64:%vreg703 [8272r,8432r:0)  0@8272r w=4.328571e-02
assigning %vreg703 to %VGPR31_VGPR32: VGPR31 VGPR32

selectOrSplit VReg_64:%vreg692 [8416r,8432r:0)[8432r,8480r:1)  0@8416r 1@8432r w=inf
assigning %vreg692 to %VGPR33_VGPR34: VGPR33 VGPR34

selectOrSplit VGPR_32:%vreg246 [8480r,8496r:0)  0@8480r w=inf
assigning %vreg246 to %VGPR31: VGPR31

selectOrSplit VGPR_32:%vreg248 [8496r,8512r:0)  0@8496r w=inf
assigning %vreg248 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg253 [8816r,8848r:0)  0@8816r w=inf
assigning %vreg253 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg255 [8848r,8880r:0)  0@8848r w=inf
assigning %vreg255 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg257 [8880r,8912r:0)  0@8880r w=inf
assigning %vreg257 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg259 [8912r,8944r:0)  0@8912r w=inf
assigning %vreg259 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg261 [8944r,8976r:0)  0@8944r w=inf
assigning %vreg261 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg263 [8976r,9008r:0)  0@8976r w=inf
assigning %vreg263 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg265 [9008r,9040r:0)  0@9008r w=inf
assigning %vreg265 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg267 [9040r,9072r:0)  0@9040r w=inf
assigning %vreg267 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg269 [9072r,9104r:0)  0@9072r w=inf
assigning %vreg269 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg271 [9104r,9136r:0)  0@9104r w=inf
assigning %vreg271 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg273 [9136r,9168r:0)  0@9136r w=inf
assigning %vreg273 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg275 [9168r,9200r:0)  0@9168r w=inf
assigning %vreg275 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg277 [9200r,9232r:0)  0@9200r w=inf
assigning %vreg277 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg279 [9232r,9264r:0)  0@9232r w=inf
assigning %vreg279 to %VGPR30: VGPR30

selectOrSplit VGPR_32:%vreg281 [9264r,9280r:0)  0@9264r w=inf
assigning %vreg281 to %VGPR14: VGPR14

selectOrSplit VReg_32:%vreg818 [9376r,9392r:0)  0@9376r w=inf
assigning %vreg818 to %VGPR14: VGPR14

selectOrSplit VReg_32:%vreg827 [9488r,9504r:0)  0@9488r w=inf
assigning %vreg827 to %VGPR14: VGPR14

selectOrSplit VGPR_32:%vreg296 [9552r,9584r:0)  0@9552r w=3.740741e-02
assigning %vreg296 to %VGPR14: VGPR14

selectOrSplit SReg_64:%vreg297 [9584r,9600r:0)  0@9584r w=inf
assigning %vreg297 to %SGPR42_SGPR43: SGPR42 SGPR43

selectOrSplit VReg_64:%vreg830 [10032r,10064r:0)[10064r,10496r:1)  0@10032r 1@10064r w=3.740741e-02
hints: %VGPR8_VGPR9
assigning %vreg830 to %VGPR6_VGPR7: VGPR6 VGPR7

selectOrSplit VReg_32:%vreg836 [10048r,10064r:0)  0@10048r w=inf
assigning %vreg836 to %VGPR1: VGPR1

selectOrSplit VReg_64:%vreg839 [10144r,10176r:0)[10176r,10512r:1)  0@10144r 1@10176r w=4.208333e-02
hints: %VGPR10_VGPR11
assigning %vreg839 to %VGPR12_VGPR13: VGPR12 VGPR13

selectOrSplit VReg_32:%vreg845 [10160r,10176r:0)  0@10160r w=inf
assigning %vreg845 to %VGPR1: VGPR1

selectOrSplit VReg_32:%vreg367 [10288r,10320r:0)  0@10288r w=3.703704e-02
assigning %vreg367 to %VGPR1: VGPR1

selectOrSplit VGPR_32:%vreg368 [10304r,10320r:0)  0@10304r w=inf
assigning %vreg368 to %VGPR8: VGPR8

selectOrSplit VGPR_32:%vreg369 [10320r,10336r:0)  0@10320r w=inf
assigning %vreg369 to %VGPR1: VGPR1

selectOrSplit SReg_64:%vreg371 [10368r,10384r:0)  0@10368r w=inf
assigning %vreg371 to %SGPR18_SGPR19: SGPR18 SGPR19

selectOrSplit VGPR_32:%vreg373 [10672r,10688r:0)  0@10672r w=inf
assigning %vreg373 to %VGPR0: VGPR0

selectOrSplit VReg_32:%vreg374 [10688r,10704r:0)  0@10688r w=inf
assigning %vreg374 to %VGPR0: VGPR0

selectOrSplit VReg_64:%vreg425 [10704r,10720r:0)[10720r,10768r:1)  0@10704r 1@10720r w=inf
assigning %vreg425 to %VGPR0_VGPR1: VGPR0 VGPR1

selectOrSplit VReg_64:%vreg428 [10768r,10864r:0)  0@10768r w=3.024193e-03
assigning %vreg428 to %VGPR2_VGPR3: VGPR2 VGPR3

selectOrSplit VReg_32:%vreg847 [10816r,10848r:0)  0@10816r w=2.314815e-03
assigning %vreg847 to %VGPR0: VGPR0

selectOrSplit VReg_32:%vreg848 [10832r,10864r:0)  0@10832r w=2.314815e-03
assigning %vreg848 to %VGPR6: VGPR6

selectOrSplit VGPR_32:%vreg389 [10928r,10944r:0)  0@10928r w=inf
assigning %vreg389 to %VGPR3: VGPR3

selectOrSplit SReg_64:%vreg390 [10944r,10976r:0)  0@10944r w=2.314815e-03
assigning %vreg390 to %SGPR2_SGPR3: SGPR2 SGPR3

selectOrSplit SReg_64:%vreg391 [10960r,10976r:0)  0@10960r w=inf
assigning %vreg391 to %SGPR4_SGPR5: SGPR4 SGPR5

selectOrSplit SReg_64:%vreg392 [10976r,11008r:0)  0@10976r w=inf
assigning %vreg392 to %SGPR2_SGPR3: SGPR2 SGPR3

selectOrSplit SReg_128:%vreg396 [11120r,11136r:0)[11136r,11152r:1)[11152r,11248r:2)  0@11120r 1@11136r 2@11152r w=1.420455e-03
assigning %vreg396 to %SGPR4_SGPR5_SGPR6_SGPR7: SGPR4 SGPR5 SGPR6 SGPR7

selectOrSplit VReg_32:%vreg397 [11232r,11248r:0)  0@11232r w=inf
assigning %vreg397 to %VGPR2: VGPR2

selectOrSplit SReg_128:%vreg394 [11312r,11328r:0)[11328r,11344r:1)[11344r,11424r:2)  0@11312r 1@11328r 2@11344r w=inf
assigning %vreg394 to %SGPR4_SGPR5_SGPR6_SGPR7: SGPR4 SGPR5 SGPR6 SGPR7
# *** IR Dump Before Virtual Register Rewriter ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
32B		%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
48B		%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
64B		%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
112B		%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
224B		%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76, %vreg68; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
368B		%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
384B		%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
400B		%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
416B		%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
432B		%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
448B		%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
464B		%vreg86<def> = SI_IF %vreg77, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Predecessors according to CFG: BB#0
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9 SGPR_32:%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
752B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
832B		%vreg92<def> = SI_IF %vreg89, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SGPR_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
944B		%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0, %EXEC<imp-use>; VReg_64:%vreg104
992B		%vreg499<def> = V_LSHL_B64 %vreg104, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
1072B		%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
1088B		%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1, %vreg517, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
1168B		%vreg116<def> = S_MOV_B64 32; SGPR_64:%vreg116
1216B		%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
1232B		%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
1248B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1, %vreg508, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SGPR_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0, %EXEC<imp-use>; VReg_64:%vreg130
1408B		%vreg522<def> = V_LSHL_B64 %vreg130, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
1488B		%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
1504B		%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1, %vreg540, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
1584B		%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
1600B		%vreg531<def> = COPY %vreg116:sub1; VReg_32:%vreg531 SGPR_64:%vreg116
1616B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1, %vreg531, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
1664B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
1696B		%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
1728B		%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
1792B		%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
1808B		%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
1824B		%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
1840B		%vreg183:sub0<def> = S_MOV_B32 -4; SGPR_64:%vreg183
1856B		%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
1872B		%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
1888B		%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
1904B		%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
1920B		%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
1936B		%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
1952B		%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
1968B		%vreg283<def> = S_MOV_B64 64; SGPR_64:%vreg283
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299 SGPR_32:%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg459:sub0<def,read-undef> = COPY %vreg13; VReg_64:%vreg459 SReg_32:%vreg13
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
2336B		%vreg302<def> = SI_IF %vreg301, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5, %vreg304, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SGPR_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg444, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0, %EXEC<imp-use>; VReg_64:%vreg312
2528B		%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0, %EXEC<imp-use>; VReg_64:%vreg459
2608B		%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
2624B		%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
2672B		%vreg482<def> = V_LSHL_B64 %vreg479, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
2752B		%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
2768B		%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552, %vreg482:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
2816B		%vreg330<def> = COPY %vreg0; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1, %vreg330, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SGPR_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg447, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0, %EXEC<imp-use>; VReg_64:%vreg338
2960B		%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
2976B		%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
3024B		%vreg468<def> = V_LSHL_B64 %vreg465, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
3104B		%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
3120B		%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559, %vreg468:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
3168B		%vreg860<def> = V_SUB_I32_e32 %vreg55, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
3184B		%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
3248B		%vreg353<def> = S_MOV_B64 4; SGPR_64:%vreg353
3264B		%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
3280B		%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Predecessors according to CFG: BB#1 BB#3
3456B		%vreg56<def> = COPY %vreg78; VGPR_32:%vreg56 SGPR_32:%vreg78
3504B		SI_END_CF %vreg92, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Predecessors according to CFG: BB#2 BB#8
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150, %vreg149, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154, %vreg153, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg250:sub14<def> = V_MUL_F32_e32 %vreg155, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158, %vreg157, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg250:sub13<def> = V_MUL_F32_e32 %vreg159, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162, %vreg161, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg250:sub12<def> = V_MUL_F32_e32 %vreg163, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166, %vreg165, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg250:sub11<def> = V_MUL_F32_e32 %vreg167, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170, %vreg169, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg250:sub10<def> = V_MUL_F32_e32 %vreg171, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174, %vreg173, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg250:sub9<def> = V_MUL_F32_e32 %vreg175, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178, %vreg177, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg250:sub8<def> = V_MUL_F32_e32 %vreg179, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
4336B		%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
4480B		%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4496B		%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4688B		%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
4832B		%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4848B		%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190, %vreg186, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg250:sub7<def> = V_MUL_F32_e32 %vreg192, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
4960B		%vreg195:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg195
4976B		%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
5120B		%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5136B		%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
5344B		%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5360B		%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198, %vreg196, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg250:sub6<def> = V_MUL_F32_e32 %vreg200, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
5472B		%vreg203:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg203
5488B		%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
5632B		%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5648B		%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
5856B		%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5872B		%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206, %vreg204, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg250:sub5<def> = V_MUL_F32_e32 %vreg208, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
5984B		%vreg211:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg211
6000B		%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
6144B		%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6160B		%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
6368B		%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6384B		%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214, %vreg212, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg250:sub4<def> = V_MUL_F32_e32 %vreg216, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
6496B		%vreg219:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg219
6512B		%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
6656B		%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6672B		%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
6880B		%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6896B		%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222, %vreg220, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg250:sub3<def> = V_MUL_F32_e32 %vreg224, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
7008B		%vreg227:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg227
7024B		%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
7168B		%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7184B		%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
7392B		%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7408B		%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230, %vreg228, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg250:sub2<def> = V_MUL_F32_e32 %vreg232, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
7520B		%vreg235:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg235
7536B		%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
7680B		%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7696B		%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
7904B		%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7920B		%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238, %vreg236, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg250:sub1<def> = V_MUL_F32_e32 %vreg240, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
8032B		%vreg243:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg243
8048B		%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
8192B		%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8208B		%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
8416B		%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8432B		%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246, %vreg244, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg250:sub0<def> = V_MUL_F32_e32 %vreg248, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15, %vreg279, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
9280B		%vreg856<def> = V_ADD_F32_e32 %vreg856, %vreg281, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
9360B		%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
9376B		%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
9392B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg818, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
9472B		%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
9488B		%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
9504B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg827, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg854<def> = V_ADD_I32_e32 16, %vreg854, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
9600B		%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297, %vreg851:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
9776B		SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %vreg302, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Predecessors according to CFG: BB#6 BB#10
10032B		%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
10048B		%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
10064B		%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
10144B		%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
10160B		%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
10176B		%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368, %vreg367, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg856<def> = V_MAD_F32 %vreg369, %vreg369, %vreg856, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
10352B		%vreg860<def> = V_ADD_I32_e32 -1, %vreg860, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
10384B		%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371, %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
10496B		%vreg858<def> = COPY %vreg830; VReg_64:%vreg858,%vreg830
10512B		%vreg859<def> = COPY %vreg839; VReg_64:%vreg859,%vreg839
10560B		SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg857:sub0_sub1, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54; VGPR_32:%vreg373 SGPR_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440, %vreg373, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374, %vreg423, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
10720B		%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0, %EXEC<imp-use>; VReg_64:%vreg425
10768B		%vreg428<def> = V_LSHL_B64 %vreg425, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
10848B		%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
10864B		%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848, %vreg428:sub1, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg856, %vreg56, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390, %vreg391; SReg_64:%vreg392,%vreg390,%vreg391
11008B		%vreg395<def> = SI_IF %vreg392, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Predecessors according to CFG: BB#12 BB#15
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Predecessors according to CFG: BB#13
11120B		%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
11136B		%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
11152B		%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397, %vreg396, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Predecessors according to CFG: BB#12
11312B		%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
11328B		%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
11344B		%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
11424B		BUFFER_STORE_DWORD %vreg388, %vreg394, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

********** REWRITE VIRTUAL REGISTERS **********
********** Function: svm_rbf
********** REGISTER MAP **********
[%vreg0 -> %SGPR2] SReg_32
[%vreg1 -> %SGPR8] SGPR_32
[%vreg4 -> %SGPR3] SReg_32
[%vreg5 -> %SGPR14] SGPR_32
[%vreg9 -> %SGPR17] SReg_32
[%vreg13 -> %SGPR17] SReg_32
[%vreg45 -> %VGPR0_VGPR1] VReg_64
[%vreg48 -> %SGPR0_SGPR1] SReg_64
[%vreg49 -> %SGPR12_SGPR13] SReg_64_with_sub0
[%vreg50 -> %SGPR15] SGPR_32
[%vreg51 -> %SGPR10_SGPR11] SReg_64_with_sub0
[%vreg52 -> %SGPR9] SGPR_32
[%vreg53 -> %SGPR4_SGPR5] SReg_64_with_sub0
[%vreg54 -> %SGPR6] SGPR_32
[%vreg55 -> %SGPR7] SGPR_32
[%vreg56 -> %VGPR5] VGPR_32
[%vreg61 -> %VGPR2] VGPR_32
[%vreg63 -> %VGPR2] VReg_32
[%vreg66 -> %SGPR4] SGPR_32
[%vreg67 -> %VGPR3] VGPR_32
[%vreg68 -> %SGPR4_SGPR5] SReg_64
[%vreg69 -> %VGPR3] VGPR_32
[%vreg71 -> %VGPR3] VReg_32
[%vreg74 -> %SGPR6] SGPR_32
[%vreg75 -> %VGPR4] VGPR_32
[%vreg76 -> %SGPR6_SGPR7] SReg_64
[%vreg77 -> %SGPR18_SGPR19] SReg_64
[%vreg78 -> %SGPR16] SGPR_32
[%vreg86 -> %SGPR0_SGPR1] SReg_64
[%vreg89 -> %SGPR18_SGPR19] SReg_64
[%vreg92 -> %SGPR18_SGPR19] SReg_64
[%vreg96 -> %VGPR4] VGPR_32
[%vreg97 -> %VGPR4] VReg_32
[%vreg104 -> %VGPR4_VGPR5] VReg_64
[%vreg116 -> %SGPR20_SGPR21] SGPR_64
[%vreg122 -> %VGPR4] VGPR_32
[%vreg123 -> %VGPR4] VReg_32
[%vreg130 -> %VGPR9_VGPR10] VReg_64
[%vreg149 -> %VGPR14] VReg_32
[%vreg150 -> %VGPR15] VGPR_32
[%vreg151 -> %VGPR14] VGPR_32
[%vreg153 -> %VGPR30] VReg_32
[%vreg154 -> %VGPR31] VGPR_32
[%vreg155 -> %VGPR30] VGPR_32
[%vreg157 -> %VGPR30] VReg_32
[%vreg158 -> %VGPR31] VGPR_32
[%vreg159 -> %VGPR30] VGPR_32
[%vreg161 -> %VGPR30] VReg_32
[%vreg162 -> %VGPR31] VGPR_32
[%vreg163 -> %VGPR30] VGPR_32
[%vreg165 -> %VGPR30] VReg_32
[%vreg166 -> %VGPR31] VGPR_32
[%vreg167 -> %VGPR30] VGPR_32
[%vreg169 -> %VGPR30] VReg_32
[%vreg170 -> %VGPR31] VGPR_32
[%vreg171 -> %VGPR30] VGPR_32
[%vreg173 -> %VGPR30] VReg_32
[%vreg174 -> %VGPR31] VGPR_32
[%vreg175 -> %VGPR30] VGPR_32
[%vreg177 -> %VGPR30] VReg_32
[%vreg178 -> %VGPR31] VGPR_32
[%vreg179 -> %VGPR30] VGPR_32
[%vreg183 -> %SGPR24_SGPR25] SGPR_64
[%vreg186 -> %VGPR30] VReg_32
[%vreg190 -> %VGPR31] VGPR_32
[%vreg192 -> %VGPR30] VGPR_32
[%vreg195 -> %SGPR26_SGPR27] SGPR_64
[%vreg196 -> %VGPR30] VReg_32
[%vreg198 -> %VGPR31] VGPR_32
[%vreg200 -> %VGPR30] VGPR_32
[%vreg203 -> %SGPR28_SGPR29] SGPR_64
[%vreg204 -> %VGPR30] VReg_32
[%vreg206 -> %VGPR31] VGPR_32
[%vreg208 -> %VGPR30] VGPR_32
[%vreg211 -> %SGPR30_SGPR31] SGPR_64
[%vreg212 -> %VGPR30] VReg_32
[%vreg214 -> %VGPR31] VGPR_32
[%vreg216 -> %VGPR30] VGPR_32
[%vreg219 -> %SGPR32_SGPR33] SGPR_64
[%vreg220 -> %VGPR30] VReg_32
[%vreg222 -> %VGPR31] VGPR_32
[%vreg224 -> %VGPR30] VGPR_32
[%vreg227 -> %SGPR34_SGPR35] SGPR_64
[%vreg228 -> %VGPR30] VReg_32
[%vreg230 -> %VGPR31] VGPR_32
[%vreg232 -> %VGPR30] VGPR_32
[%vreg235 -> %SGPR36_SGPR37] SGPR_64
[%vreg236 -> %VGPR30] VReg_32
[%vreg238 -> %VGPR31] VGPR_32
[%vreg240 -> %VGPR30] VGPR_32
[%vreg243 -> %SGPR38_SGPR39] SGPR_64
[%vreg244 -> %VGPR30] VReg_32
[%vreg246 -> %VGPR31] VGPR_32
[%vreg248 -> %VGPR30] VGPR_32
[%vreg250 -> %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29] VReg_512
[%vreg253 -> %VGPR30] VGPR_32
[%vreg255 -> %VGPR30] VGPR_32
[%vreg257 -> %VGPR30] VGPR_32
[%vreg259 -> %VGPR30] VGPR_32
[%vreg261 -> %VGPR30] VGPR_32
[%vreg263 -> %VGPR30] VGPR_32
[%vreg265 -> %VGPR30] VGPR_32
[%vreg267 -> %VGPR30] VGPR_32
[%vreg269 -> %VGPR30] VGPR_32
[%vreg271 -> %VGPR30] VGPR_32
[%vreg273 -> %VGPR30] VGPR_32
[%vreg275 -> %VGPR30] VGPR_32
[%vreg277 -> %VGPR30] VGPR_32
[%vreg279 -> %VGPR30] VGPR_32
[%vreg281 -> %VGPR14] VGPR_32
[%vreg283 -> %SGPR40_SGPR41] SGPR_64
[%vreg296 -> %VGPR14] VGPR_32
[%vreg297 -> %SGPR42_SGPR43] SReg_64
[%vreg299 -> %SGPR17] SReg_32
[%vreg300 -> %VGPR8] VGPR_32
[%vreg301 -> %SGPR16_SGPR17] SReg_64
[%vreg302 -> %SGPR16_SGPR17] SReg_64
[%vreg304 -> %VGPR8] VGPR_32
[%vreg305 -> %VGPR8] VReg_32
[%vreg312 -> %VGPR8_VGPR9] VReg_64
[%vreg330 -> %VGPR1] VGPR_32
[%vreg331 -> %VGPR1] VReg_32
[%vreg338 -> %VGPR0_VGPR1] VReg_64
[%vreg353 -> %SGPR2_SGPR3] SGPR_64
[%vreg366 -> %SGPR8_SGPR9_SGPR10_SGPR11] SReg_128
[%vreg367 -> %VGPR1] VReg_32
[%vreg368 -> %VGPR8] VGPR_32
[%vreg369 -> %VGPR1] VGPR_32
[%vreg371 -> %SGPR18_SGPR19] SReg_64
[%vreg373 -> %VGPR0] VGPR_32
[%vreg374 -> %VGPR0] VReg_32
[%vreg388 -> %VGPR2] VGPR_32
[%vreg389 -> %VGPR3] VGPR_32
[%vreg390 -> %SGPR2_SGPR3] SReg_64
[%vreg391 -> %SGPR4_SGPR5] SReg_64
[%vreg392 -> %SGPR2_SGPR3] SReg_64
[%vreg394 -> %SGPR4_SGPR5_SGPR6_SGPR7] SReg_128
[%vreg395 -> %SGPR2_SGPR3] SReg_64
[%vreg396 -> %SGPR4_SGPR5_SGPR6_SGPR7] SReg_128
[%vreg397 -> %VGPR2] VReg_32
[%vreg423 -> %VGPR2] VReg_32
[%vreg425 -> %VGPR0_VGPR1] VReg_64
[%vreg428 -> %VGPR2_VGPR3] VReg_64
[%vreg440 -> %VGPR3] VReg_32
[%vreg442 -> %VGPR1] VReg_32
[%vreg443 -> %VGPR4] VGPR_32
[%vreg444 -> %VGPR1] VGPR_32
[%vreg445 -> %VGPR0] VReg_32
[%vreg446 -> %VGPR4] VGPR_32
[%vreg447 -> %VGPR0] VGPR_32
[%vreg459 -> %VGPR6_VGPR7] VReg_64
[%vreg465 -> %VGPR10_VGPR11] VReg_64
[%vreg468 -> %VGPR0_VGPR1] VReg_64
[%vreg479 -> %VGPR10_VGPR11] VReg_64
[%vreg482 -> %VGPR10_VGPR11] VReg_64
[%vreg499 -> %VGPR4_VGPR5] VReg_64
[%vreg503 -> %VGPR9_VGPR10] VReg_64
[%vreg508 -> %VGPR4] VReg_32
[%vreg516 -> %VGPR6] VReg_32
[%vreg517 -> %VGPR7] VReg_32
[%vreg522 -> %VGPR9_VGPR10] VReg_64
[%vreg526 -> %VGPR13_VGPR14] VReg_64
[%vreg531 -> %VGPR4] VReg_32
[%vreg539 -> %VGPR4] VReg_32
[%vreg540 -> %VGPR11] VReg_32
[%vreg551 -> %VGPR1] VReg_32
[%vreg552 -> %VGPR12] VReg_32
[%vreg558 -> %VGPR10] VReg_32
[%vreg559 -> %VGPR12] VReg_32
[%vreg562 -> %VGPR9_VGPR10_VGPR11_VGPR12] VReg_128
[%vreg567 -> %VGPR32_VGPR33] VReg_64
[%vreg578 -> %VGPR30_VGPR31] VReg_64
[%vreg582 -> %VGPR32_VGPR33] VReg_64
[%vreg593 -> %VGPR30_VGPR31] VReg_64
[%vreg597 -> %VGPR32_VGPR33] VReg_64
[%vreg608 -> %VGPR30_VGPR31] VReg_64
[%vreg612 -> %VGPR32_VGPR33] VReg_64
[%vreg623 -> %VGPR30_VGPR31] VReg_64
[%vreg627 -> %VGPR32_VGPR33] VReg_64
[%vreg638 -> %VGPR30_VGPR31] VReg_64
[%vreg642 -> %VGPR32_VGPR33] VReg_64
[%vreg653 -> %VGPR30_VGPR31] VReg_64
[%vreg657 -> %VGPR32_VGPR33] VReg_64
[%vreg668 -> %VGPR30_VGPR31] VReg_64
[%vreg672 -> %VGPR32_VGPR33] VReg_64
[%vreg676 -> %SGPR20_SGPR21_SGPR22_SGPR23] SReg_128
[%vreg683 -> %VGPR30_VGPR31] VReg_64
[%vreg687 -> %VGPR5_VGPR6_VGPR7_VGPR8] VReg_128
[%vreg692 -> %VGPR33_VGPR34] VReg_64
[%vreg703 -> %VGPR31_VGPR32] VReg_64
[%vreg707 -> %VGPR33_VGPR34] VReg_64
[%vreg718 -> %VGPR31_VGPR32] VReg_64
[%vreg722 -> %VGPR33_VGPR34] VReg_64
[%vreg733 -> %VGPR31_VGPR32] VReg_64
[%vreg737 -> %VGPR33_VGPR34] VReg_64
[%vreg748 -> %VGPR31_VGPR32] VReg_64
[%vreg752 -> %VGPR33_VGPR34] VReg_64
[%vreg763 -> %VGPR31_VGPR32] VReg_64
[%vreg767 -> %VGPR33_VGPR34] VReg_64
[%vreg778 -> %VGPR31_VGPR32] VReg_64
[%vreg782 -> %VGPR33_VGPR34] VReg_64
[%vreg793 -> %VGPR31_VGPR32] VReg_64
[%vreg797 -> %VGPR33_VGPR34] VReg_64
[%vreg808 -> %VGPR31_VGPR32] VReg_64
[%vreg818 -> %VGPR14] VReg_32
[%vreg827 -> %VGPR14] VReg_32
[%vreg830 -> %VGPR6_VGPR7] VReg_64
[%vreg836 -> %VGPR1] VReg_32
[%vreg839 -> %VGPR12_VGPR13] VReg_64
[%vreg845 -> %VGPR1] VReg_32
[%vreg847 -> %VGPR0] VReg_32
[%vreg848 -> %VGPR6] VReg_32
[%vreg851 -> %SGPR44_SGPR45_SGPR46_SGPR47] SReg_128
[%vreg854 -> %VGPR13] VReg_32
[%vreg856 -> %VGPR4] VGPR_32
[%vreg857 -> %SGPR12_SGPR13_SGPR14_SGPR15] SReg_128
[%vreg858 -> %VGPR8_VGPR9] VReg_64
[%vreg859 -> %VGPR10_VGPR11] VReg_64
[%vreg860 -> %VGPR0] VReg_32

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
16B		%vreg0<def> = COPY %SGPR2; SReg_32:%vreg0
32B		%vreg445<def> = COPY %VGPR0; VReg_32:%vreg445
48B		%vreg4<def> = COPY %SGPR3; SReg_32:%vreg4
64B		%vreg442<def> = COPY %VGPR1; VReg_32:%vreg442
80B		%vreg48<def> = COPY %SGPR0_SGPR1; SReg_64:%vreg48
96B		%vreg61<def> = COPY %vreg0; VGPR_32:%vreg61 SReg_32:%vreg0
112B		%vreg1<def> = S_LOAD_DWORD_IMM %vreg48, 6; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg1 SReg_64:%vreg48
128B		%vreg63<def> = V_MUL_LO_I32 %vreg1, %vreg61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg63 SGPR_32:%vreg1 VGPR_32:%vreg61
144B		%vreg423<def> = V_ADD_I32_e32 %vreg63<kill>, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg423,%vreg63,%vreg445
160B		%vreg66<def> = S_LOAD_DWORD_IMM %vreg48, 21; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg66 SReg_64:%vreg48
176B		%vreg67<def> = COPY %vreg66<kill>; VGPR_32:%vreg67 SGPR_32:%vreg66
192B		%vreg68<def> = V_CMP_LT_I32_e64 %vreg423, %vreg67<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg68 VReg_32:%vreg423 VGPR_32:%vreg67
208B		%vreg69<def> = COPY %vreg4; VGPR_32:%vreg69 SReg_32:%vreg4
224B		%vreg5<def> = S_LOAD_DWORD_IMM %vreg48, 7; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg5 SReg_64:%vreg48
240B		%vreg71<def> = V_MUL_LO_I32 %vreg5, %vreg69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg71 SGPR_32:%vreg5 VGPR_32:%vreg69
256B		%vreg440<def> = V_ADD_I32_e32 %vreg71<kill>, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg440,%vreg71,%vreg442
272B		%vreg74<def> = S_LOAD_DWORD_IMM %vreg48, 20; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg74 SReg_64:%vreg48
288B		%vreg75<def> = COPY %vreg74<kill>; VGPR_32:%vreg75 SGPR_32:%vreg74
304B		%vreg76<def> = V_CMP_LT_I32_e64 %vreg440, %vreg75<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg76 VReg_32:%vreg440 VGPR_32:%vreg75
320B		%vreg77<def> = S_AND_B64 %vreg76<kill>, %vreg68<kill>; SReg_64:%vreg77,%vreg76,%vreg68
336B		%vreg78<def> = S_LOAD_DWORD_IMM %vreg48, 23; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg78 SReg_64:%vreg48
352B		%vreg55<def> = S_LOAD_DWORD_IMM %vreg48, 22; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg55 SReg_64:%vreg48
368B		%vreg54<def> = S_LOAD_DWORD_IMM %vreg48, 19; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg54 SReg_64:%vreg48
384B		%vreg53<def> = S_LOAD_DWORDX2_IMM %vreg48, 17; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg53 SReg_64:%vreg48
400B		%vreg52<def> = S_LOAD_DWORD_IMM %vreg48, 15; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg52 SReg_64:%vreg48
416B		%vreg51<def> = S_LOAD_DWORDX2_IMM %vreg48, 13; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg51 SReg_64:%vreg48
432B		%vreg50<def> = S_LOAD_DWORD_IMM %vreg48, 11; mem:LD4[undef(addrspace=2)] SGPR_32:%vreg50 SReg_64:%vreg48
448B		%vreg49<def> = S_LOAD_DWORDX2_IMM %vreg48<kill>, 9; mem:LD8[undef(addrspace=2)] SReg_64_with_sub0:%vreg49 SReg_64:%vreg48
464B		%vreg86<def> = SI_IF %vreg77<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86,%vreg77
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)
> %SGPR2<def> = COPY %SGPR2
Deleting identity copy.
> %VGPR0<def> = COPY %VGPR0
Deleting identity copy.
> %SGPR3<def> = COPY %SGPR3
Deleting identity copy.
> %VGPR1<def> = COPY %VGPR1
Deleting identity copy.
> %SGPR0_SGPR1<def> = COPY %SGPR0_SGPR1
Deleting identity copy.
> %VGPR2<def> = COPY %SGPR2
> %SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
> %VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
> %SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
> %VGPR3<def> = COPY %SGPR4<kill>
> %SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR3<def> = COPY %SGPR3
> %SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
> %VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
> %SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
> %VGPR4<def> = COPY %SGPR6<kill>
> %SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
> %SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
> %SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
> %SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
> %SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
> %SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
> %SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
> %SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
> %SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
> %SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
> %SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#1>
496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
	    Predecessors according to CFG: BB#0
688B		%vreg9<def> = S_ADD_I32 %vreg55, -16, %SCC<imp-def,dead>; SReg_32:%vreg9 SGPR_32:%vreg55
704B		%vreg89<def> = V_CMP_GT_I32_e64 %vreg9, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg89 SReg_32:%vreg9
720B		%vreg459:sub0<def,read-undef> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_64:%vreg459
752B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
832B		%vreg92<def> = SI_IF %vreg89<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92,%vreg89
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)
> %SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
> %SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
> %VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
> %SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#2>
864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
	    Predecessors according to CFG: BB#1
880B		%vreg96<def> = COPY %vreg4; VGPR_32:%vreg96 SReg_32:%vreg4
896B		%vreg97<def> = V_MUL_LO_I32 %vreg5, %vreg96<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg97 SGPR_32:%vreg5 VGPR_32:%vreg96
912B		%vreg443<def> = V_ADD_I32_e32 %vreg97<kill>, %vreg442, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg443 VReg_32:%vreg97,%vreg442
928B		%vreg104:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50, %vreg443<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg104 SGPR_32:%vreg50 VGPR_32:%vreg443
944B		%vreg104:sub1<def> = V_ASHRREV_I32_e32 31, %vreg104:sub0<kill>, %EXEC<imp-use>; VReg_64:%vreg104
992B		%vreg499<def> = V_LSHL_B64 %vreg104<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg499,%vreg104
1040B		%vreg516<def> = COPY %vreg49:sub0; VReg_32:%vreg516 SReg_64_with_sub0:%vreg49
1056B		%vreg517<def> = COPY %vreg49:sub1; VReg_32:%vreg517 SReg_64_with_sub0:%vreg49
1072B		%vreg503:sub0<def,read-undef> = V_ADD_I32_e32 %vreg516<kill>, %vreg499:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg516
1088B		%vreg503:sub1<def> = V_ADDC_U32_e32 %vreg499:sub1<kill>, %vreg517<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg503,%vreg499 VReg_32:%vreg517
1168B		%vreg116<def> = S_MOV_B64 32; SGPR_64:%vreg116
1216B		%vreg687:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg503:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg116 VReg_64:%vreg503
1232B		%vreg508<def> = COPY %vreg116:sub1; VReg_32:%vreg508 SGPR_64:%vreg116
1248B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg503:sub1<kill>, %vreg508<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_64:%vreg503 VReg_32:%vreg508
1296B		%vreg122<def> = COPY %vreg0; VGPR_32:%vreg122 SReg_32:%vreg0
1312B		%vreg123<def> = V_MUL_LO_I32 %vreg1, %vreg122<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg123 SGPR_32:%vreg1 VGPR_32:%vreg122
1328B		%vreg446<def> = V_ADD_I32_e32 %vreg123<kill>, %vreg445, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg446 VReg_32:%vreg123,%vreg445
1344B		%vreg130:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52, %vreg446<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg130 SGPR_32:%vreg52 VGPR_32:%vreg446
1360B		%vreg130:sub1<def> = V_ASHRREV_I32_e32 31, %vreg130:sub0<kill>, %EXEC<imp-use>; VReg_64:%vreg130
1408B		%vreg522<def> = V_LSHL_B64 %vreg130<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg522,%vreg130
1456B		%vreg539<def> = COPY %vreg51:sub0; VReg_32:%vreg539 SReg_64_with_sub0:%vreg51
1472B		%vreg540<def> = COPY %vreg51:sub1; VReg_32:%vreg540 SReg_64_with_sub0:%vreg51
1488B		%vreg526:sub0<def,read-undef> = V_ADD_I32_e32 %vreg539<kill>, %vreg522:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg539
1504B		%vreg526:sub1<def> = V_ADDC_U32_e32 %vreg522:sub1<kill>, %vreg540<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg526,%vreg522 VReg_32:%vreg540
1584B		%vreg562:sub0<def,read-undef> = V_ADD_I32_e32 %vreg116:sub0, %vreg526:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg116 VReg_64:%vreg526
1600B		%vreg531<def> = COPY %vreg116:sub1<kill>; VReg_32:%vreg531 SGPR_64:%vreg116
1616B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg526:sub1<kill>, %vreg531<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_64:%vreg526 VReg_32:%vreg531
1664B		%vreg856<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>; VGPR_32:%vreg856
1696B		%vreg854<def> = V_MOV_B32_e32 0, %EXEC<imp-use>; VReg_32:%vreg854
1728B		%vreg676:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg676
1792B		%vreg676:sub2<def> = S_MOV_B32 0; SReg_128:%vreg676
1808B		%vreg676:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg676
1824B		%vreg183:sub1<def,read-undef> = S_MOV_B32 -1; SGPR_64:%vreg183
1840B		%vreg183:sub0<def> = S_MOV_B32 -4; SGPR_64:%vreg183
1856B		%vreg195:sub0<def,read-undef> = S_MOV_B32 -8; SGPR_64:%vreg195
1872B		%vreg203:sub0<def,read-undef> = S_MOV_B32 -12; SGPR_64:%vreg203
1888B		%vreg211:sub0<def,read-undef> = S_MOV_B32 -16; SGPR_64:%vreg211
1904B		%vreg219:sub0<def,read-undef> = S_MOV_B32 -20; SGPR_64:%vreg219
1920B		%vreg227:sub0<def,read-undef> = S_MOV_B32 -24; SGPR_64:%vreg227
1936B		%vreg235:sub0<def,read-undef> = S_MOV_B32 -28; SGPR_64:%vreg235
1952B		%vreg243:sub0<def,read-undef> = S_MOV_B32 -32; SGPR_64:%vreg243
1968B		%vreg283<def> = S_MOV_B64 64; SGPR_64:%vreg283
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8
> %VGPR4<def> = COPY %SGPR3
> %VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
> %VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
> %VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
> %VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
> %VGPR6<def> = COPY %SGPR12
> %VGPR7<def> = COPY %SGPR13
> %VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
> %VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
> %SGPR20_SGPR21<def> = S_MOV_B64 32
> %VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
> %VGPR4<def> = COPY %SGPR21
> %VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
> %VGPR4<def> = COPY %SGPR2
> %VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
> %VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
> %VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
> %VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
> %VGPR4<def> = COPY %SGPR10
> %VGPR11<def> = COPY %SGPR11
> %VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
> %VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
> %VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
> %VGPR4<def> = COPY %SGPR21, %SGPR20_SGPR21<imp-use,kill>
> %VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
> %VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
> %VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
> %SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
> %SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
> %SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
> %SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
> %SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
> %SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
> %SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
> %SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
> %SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
> %SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
> %SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
> %SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
> %SGPR40_SGPR41<def> = S_MOV_B64 64
> S_BRANCH <BB#8>
2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %vreg851:sub0_sub1<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
2128B		%vreg299<def> = S_ADD_I32 %vreg55, -1, %SCC<imp-def,dead>; SReg_32:%vreg299 SGPR_32:%vreg55
2144B		%vreg13<def> = S_AND_B32 %vreg299<kill>, -16; SReg_32:%vreg13,%vreg299
2160B		%vreg459:sub0<def,read-undef> = COPY %vreg13<kill>; VReg_64:%vreg459 SReg_32:%vreg13
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7
> SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
> %SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
> %SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
> %VGPR6<def> = COPY %SGPR17<kill>, %VGPR6_VGPR7<imp-def>
> S_BRANCH <BB#7>
2224B	BB#4: derived from LLVM BB %Flow48
	    Live Ins: %SGPR0_SGPR1
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %vreg86<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg86
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17
> SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#17>
2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
	    Predecessors according to CFG: BB#7
2288B		%vreg300<def> = COPY %vreg55; VGPR_32:%vreg300 SGPR_32:%vreg55
2304B		%vreg301<def> = V_CMP_LT_I32_e64 %vreg459:sub0, %vreg300<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg301 VReg_64:%vreg459 VGPR_32:%vreg300
2336B		%vreg302<def> = SI_IF %vreg301<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302,%vreg301
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)
> %VGPR8<def> = COPY %SGPR7
> %SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
> %SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#6>
2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
	    Predecessors according to CFG: BB#5
2384B		%vreg304<def> = COPY %vreg4<kill>; VGPR_32:%vreg304 SReg_32:%vreg4
2400B		%vreg305<def> = V_MUL_LO_I32 %vreg5<kill>, %vreg304<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg305 SGPR_32:%vreg5 VGPR_32:%vreg304
2416B		%vreg444<def> = V_ADD_I32_e32 %vreg305<kill>, %vreg442<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg444 VReg_32:%vreg305,%vreg442
2432B		%vreg312:sub0<def,read-undef> = V_MUL_LO_I32 %vreg50<kill>, %vreg444<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg312 SGPR_32:%vreg50 VGPR_32:%vreg444
2448B		%vreg312:sub1<def> = V_ASHRREV_I32_e32 31, %vreg312:sub0<kill>, %EXEC<imp-use>; VReg_64:%vreg312
2528B		%vreg459:sub1<def> = V_ASHRREV_I32_e32 31, %vreg459:sub0<kill>, %EXEC<imp-use>; VReg_64:%vreg459
2608B		%vreg479:sub0<def,read-undef> = V_ADD_I32_e32 %vreg312:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg479,%vreg312,%vreg459
2624B		%vreg479:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg312:sub1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg479,%vreg459,%vreg312
2672B		%vreg482<def> = V_LSHL_B64 %vreg479<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg482,%vreg479
2720B		%vreg551<def> = COPY %vreg49:sub0; VReg_32:%vreg551 SReg_64_with_sub0:%vreg49
2736B		%vreg552<def> = COPY %vreg49:sub1<kill>; VReg_32:%vreg552 SReg_64_with_sub0:%vreg49
2752B		%vreg858:sub0<def,read-undef> = V_ADD_I32_e32 %vreg551<kill>, %vreg482:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg551
2768B		%vreg858:sub1<def> = V_ADDC_U32_e32 %vreg552<kill>, %vreg482:sub1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg858,%vreg482 VReg_32:%vreg552
2816B		%vreg330<def> = COPY %vreg0<kill>; VGPR_32:%vreg330 SReg_32:%vreg0
2832B		%vreg331<def> = V_MUL_LO_I32 %vreg1<kill>, %vreg330<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg331 SGPR_32:%vreg1 VGPR_32:%vreg330
2848B		%vreg447<def> = V_ADD_I32_e32 %vreg331<kill>, %vreg445<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VGPR_32:%vreg447 VReg_32:%vreg331,%vreg445
2864B		%vreg338:sub0<def,read-undef> = V_MUL_LO_I32 %vreg52<kill>, %vreg447<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_64:%vreg338 SGPR_32:%vreg52 VGPR_32:%vreg447
2880B		%vreg338:sub1<def> = V_ASHRREV_I32_e32 31, %vreg338:sub0<kill>, %EXEC<imp-use>; VReg_64:%vreg338
2960B		%vreg465:sub0<def,read-undef> = V_ADD_I32_e32 %vreg338:sub0, %vreg459:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg465,%vreg338,%vreg459
2976B		%vreg465:sub1<def> = V_ADDC_U32_e32 %vreg459:sub1, %vreg338:sub1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg465,%vreg459,%vreg338
3024B		%vreg468<def> = V_LSHL_B64 %vreg465<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg468,%vreg465
3072B		%vreg558<def> = COPY %vreg51:sub0; VReg_32:%vreg558 SReg_64_with_sub0:%vreg51
3088B		%vreg559<def> = COPY %vreg51:sub1<kill>; VReg_32:%vreg559 SReg_64_with_sub0:%vreg51
3104B		%vreg859:sub0<def,read-undef> = V_ADD_I32_e32 %vreg558<kill>, %vreg468:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg558
3120B		%vreg859:sub1<def> = V_ADDC_U32_e32 %vreg559<kill>, %vreg468:sub1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg859,%vreg468 VReg_32:%vreg559
3168B		%vreg860<def> = V_SUB_I32_e32 %vreg55<kill>, %vreg459:sub0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860 SGPR_32:%vreg55 VReg_64:%vreg459
3184B		%vreg366:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg366
3248B		%vreg353<def> = S_MOV_B64 4; SGPR_64:%vreg353
3264B		%vreg366:sub2<def> = S_MOV_B32 0; SReg_128:%vreg366
3280B		%vreg366:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg366
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10
> %VGPR8<def> = COPY %SGPR3<kill>
> %VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
> %VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
> %VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
> %VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
> %VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
> %VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
> %VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
> %VGPR1<def> = COPY %SGPR12
> %VGPR12<def> = COPY %SGPR13, %SGPR12_SGPR13<imp-use,kill>
> %VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
> %VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
> %VGPR1<def> = COPY %SGPR2<kill>
> %VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
> %VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
> %VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
> %VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
> %VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
> %VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
> %VGPR10<def> = COPY %SGPR10
> %VGPR12<def> = COPY %SGPR11, %SGPR10_SGPR11<imp-use,kill>
> %VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
> %VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
> %VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
> %SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
> %SGPR2_SGPR3<def> = S_MOV_B64 4
> %SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
> %SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
> S_BRANCH <BB#10>
3408B	BB#7: derived from LLVM BB %Flow47
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
	    Predecessors according to CFG: BB#1 BB#3
3456B		%vreg56<def> = COPY %vreg78<kill>; VGPR_32:%vreg56 SGPR_32:%vreg78
3504B		SI_END_CF %vreg92<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg92
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5
> %VGPR5<def> = COPY %SGPR16<kill>
> SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#5>
3552B	BB#8: derived from LLVM BB %for.body
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
	    Predecessors according to CFG: BB#2 BB#8
3712B		%vreg149<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>) VReg_32:%vreg149 SReg_128:%vreg676 VReg_128:%vreg562
3728B		%vreg150<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg150 SReg_128:%vreg676 VReg_128:%vreg687
3744B		%vreg151<def> = V_SUB_F32_e32 %vreg150<kill>, %vreg149<kill>, %EXEC<imp-use>; VGPR_32:%vreg151,%vreg150 VReg_32:%vreg149
3760B		%vreg250:sub15<def,read-undef> = V_MUL_F32_e32 %vreg151<kill>, %vreg151, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg151
3776B		%vreg153<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>) VReg_32:%vreg153 SReg_128:%vreg676 VReg_128:%vreg562
3792B		%vreg154<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg154 SReg_128:%vreg676 VReg_128:%vreg687
3808B		%vreg155<def> = V_SUB_F32_e32 %vreg154<kill>, %vreg153<kill>, %EXEC<imp-use>; VGPR_32:%vreg155,%vreg154 VReg_32:%vreg153
3824B		%vreg250:sub14<def> = V_MUL_F32_e32 %vreg155<kill>, %vreg155, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg155
3840B		%vreg157<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>) VReg_32:%vreg157 SReg_128:%vreg676 VReg_128:%vreg562
3856B		%vreg158<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg158 SReg_128:%vreg676 VReg_128:%vreg687
3872B		%vreg159<def> = V_SUB_F32_e32 %vreg158<kill>, %vreg157<kill>, %EXEC<imp-use>; VGPR_32:%vreg159,%vreg158 VReg_32:%vreg157
3888B		%vreg250:sub13<def> = V_MUL_F32_e32 %vreg159<kill>, %vreg159, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg159
3904B		%vreg161<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>) VReg_32:%vreg161 SReg_128:%vreg676 VReg_128:%vreg562
3920B		%vreg162<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg162 SReg_128:%vreg676 VReg_128:%vreg687
3936B		%vreg163<def> = V_SUB_F32_e32 %vreg162<kill>, %vreg161<kill>, %EXEC<imp-use>; VGPR_32:%vreg163,%vreg162 VReg_32:%vreg161
3952B		%vreg250:sub12<def> = V_MUL_F32_e32 %vreg163<kill>, %vreg163, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg163
3968B		%vreg165<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>) VReg_32:%vreg165 SReg_128:%vreg676 VReg_128:%vreg562
3984B		%vreg166<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg166 SReg_128:%vreg676 VReg_128:%vreg687
4000B		%vreg167<def> = V_SUB_F32_e32 %vreg166<kill>, %vreg165<kill>, %EXEC<imp-use>; VGPR_32:%vreg167,%vreg166 VReg_32:%vreg165
4016B		%vreg250:sub11<def> = V_MUL_F32_e32 %vreg167<kill>, %vreg167, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg167
4032B		%vreg169<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>) VReg_32:%vreg169 SReg_128:%vreg676 VReg_128:%vreg562
4048B		%vreg170<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg170 SReg_128:%vreg676 VReg_128:%vreg687
4064B		%vreg171<def> = V_SUB_F32_e32 %vreg170<kill>, %vreg169<kill>, %EXEC<imp-use>; VGPR_32:%vreg171,%vreg170 VReg_32:%vreg169
4080B		%vreg250:sub10<def> = V_MUL_F32_e32 %vreg171<kill>, %vreg171, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg171
4096B		%vreg173<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>) VReg_32:%vreg173 SReg_128:%vreg676 VReg_128:%vreg562
4112B		%vreg174<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg174 SReg_128:%vreg676 VReg_128:%vreg687
4128B		%vreg175<def> = V_SUB_F32_e32 %vreg174<kill>, %vreg173<kill>, %EXEC<imp-use>; VGPR_32:%vreg175,%vreg174 VReg_32:%vreg173
4144B		%vreg250:sub9<def> = V_MUL_F32_e32 %vreg175<kill>, %vreg175, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg175
4160B		%vreg177<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg562:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>) VReg_32:%vreg177 SReg_128:%vreg676 VReg_128:%vreg562
4176B		%vreg178<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg687:sub0_sub1, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg178 SReg_128:%vreg676 VReg_128:%vreg687
4192B		%vreg179<def> = V_SUB_F32_e32 %vreg178<kill>, %vreg177<kill>, %EXEC<imp-use>; VGPR_32:%vreg179,%vreg178 VReg_32:%vreg177
4208B		%vreg250:sub8<def> = V_MUL_F32_e32 %vreg179<kill>, %vreg179, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg179
4336B		%vreg683<def> = COPY %vreg183; VReg_64:%vreg683 SGPR_64:%vreg183
4480B		%vreg672:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg683:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4496B		%vreg672:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg683:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg672,%vreg683 VReg_128:%vreg562
4592B		%vreg186<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg672<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>) VReg_32:%vreg186 SReg_128:%vreg676 VReg_64:%vreg672
4688B		%vreg808<def> = COPY %vreg183; VReg_64:%vreg808 SGPR_64:%vreg183
4832B		%vreg797:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg808:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4848B		%vreg797:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg808:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg797,%vreg808 VReg_128:%vreg687
4896B		%vreg190<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg797<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg190 SReg_128:%vreg676 VReg_64:%vreg797
4912B		%vreg192<def> = V_SUB_F32_e32 %vreg190<kill>, %vreg186<kill>, %EXEC<imp-use>; VGPR_32:%vreg192,%vreg190 VReg_32:%vreg186
4928B		%vreg250:sub7<def> = V_MUL_F32_e32 %vreg192<kill>, %vreg192, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg192
4960B		%vreg195:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg195
4976B		%vreg668<def> = COPY %vreg195; VReg_64:%vreg668 SGPR_64:%vreg195
5120B		%vreg657:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg668:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5136B		%vreg657:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg668:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg657,%vreg668 VReg_128:%vreg562
5184B		%vreg196<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg657<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>) VReg_32:%vreg196 SReg_128:%vreg676 VReg_64:%vreg657
5200B		%vreg793<def> = COPY %vreg195; VReg_64:%vreg793 SGPR_64:%vreg195
5344B		%vreg782:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg793:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5360B		%vreg782:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg793:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg782,%vreg793 VReg_128:%vreg687
5408B		%vreg198<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg782<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg198 SReg_128:%vreg676 VReg_64:%vreg782
5424B		%vreg200<def> = V_SUB_F32_e32 %vreg198<kill>, %vreg196<kill>, %EXEC<imp-use>; VGPR_32:%vreg200,%vreg198 VReg_32:%vreg196
5440B		%vreg250:sub6<def> = V_MUL_F32_e32 %vreg200<kill>, %vreg200, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg200
5472B		%vreg203:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg203
5488B		%vreg653<def> = COPY %vreg203; VReg_64:%vreg653 SGPR_64:%vreg203
5632B		%vreg642:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg653:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5648B		%vreg642:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg653:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg642,%vreg653 VReg_128:%vreg562
5696B		%vreg204<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg642<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>) VReg_32:%vreg204 SReg_128:%vreg676 VReg_64:%vreg642
5712B		%vreg778<def> = COPY %vreg203; VReg_64:%vreg778 SGPR_64:%vreg203
5856B		%vreg767:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg778:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5872B		%vreg767:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg778:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg767,%vreg778 VReg_128:%vreg687
5920B		%vreg206<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg767<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg206 SReg_128:%vreg676 VReg_64:%vreg767
5936B		%vreg208<def> = V_SUB_F32_e32 %vreg206<kill>, %vreg204<kill>, %EXEC<imp-use>; VGPR_32:%vreg208,%vreg206 VReg_32:%vreg204
5952B		%vreg250:sub5<def> = V_MUL_F32_e32 %vreg208<kill>, %vreg208, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg208
5984B		%vreg211:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg211
6000B		%vreg638<def> = COPY %vreg211; VReg_64:%vreg638 SGPR_64:%vreg211
6144B		%vreg627:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg638:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6160B		%vreg627:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg638:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg627,%vreg638 VReg_128:%vreg562
6208B		%vreg212<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg627<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>) VReg_32:%vreg212 SReg_128:%vreg676 VReg_64:%vreg627
6224B		%vreg763<def> = COPY %vreg211; VReg_64:%vreg763 SGPR_64:%vreg211
6368B		%vreg752:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg763:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6384B		%vreg752:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg763:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg752,%vreg763 VReg_128:%vreg687
6432B		%vreg214<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg752<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg214 SReg_128:%vreg676 VReg_64:%vreg752
6448B		%vreg216<def> = V_SUB_F32_e32 %vreg214<kill>, %vreg212<kill>, %EXEC<imp-use>; VGPR_32:%vreg216,%vreg214 VReg_32:%vreg212
6464B		%vreg250:sub4<def> = V_MUL_F32_e32 %vreg216<kill>, %vreg216, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg216
6496B		%vreg219:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg219
6512B		%vreg623<def> = COPY %vreg219; VReg_64:%vreg623 SGPR_64:%vreg219
6656B		%vreg612:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg623:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6672B		%vreg612:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg623:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg612,%vreg623 VReg_128:%vreg562
6720B		%vreg220<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg612<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>) VReg_32:%vreg220 SReg_128:%vreg676 VReg_64:%vreg612
6736B		%vreg748<def> = COPY %vreg219; VReg_64:%vreg748 SGPR_64:%vreg219
6880B		%vreg737:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg748:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6896B		%vreg737:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg748:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg737,%vreg748 VReg_128:%vreg687
6944B		%vreg222<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg737<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg222 SReg_128:%vreg676 VReg_64:%vreg737
6960B		%vreg224<def> = V_SUB_F32_e32 %vreg222<kill>, %vreg220<kill>, %EXEC<imp-use>; VGPR_32:%vreg224,%vreg222 VReg_32:%vreg220
6976B		%vreg250:sub3<def> = V_MUL_F32_e32 %vreg224<kill>, %vreg224, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg224
7008B		%vreg227:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg227
7024B		%vreg608<def> = COPY %vreg227; VReg_64:%vreg608 SGPR_64:%vreg227
7168B		%vreg597:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg608:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7184B		%vreg597:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg608:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg597,%vreg608 VReg_128:%vreg562
7232B		%vreg228<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg597<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>) VReg_32:%vreg228 SReg_128:%vreg676 VReg_64:%vreg597
7248B		%vreg733<def> = COPY %vreg227; VReg_64:%vreg733 SGPR_64:%vreg227
7392B		%vreg722:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg733:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7408B		%vreg722:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg733:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg722,%vreg733 VReg_128:%vreg687
7456B		%vreg230<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg722<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg230 SReg_128:%vreg676 VReg_64:%vreg722
7472B		%vreg232<def> = V_SUB_F32_e32 %vreg230<kill>, %vreg228<kill>, %EXEC<imp-use>; VGPR_32:%vreg232,%vreg230 VReg_32:%vreg228
7488B		%vreg250:sub2<def> = V_MUL_F32_e32 %vreg232<kill>, %vreg232, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg232
7520B		%vreg235:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg235
7536B		%vreg593<def> = COPY %vreg235; VReg_64:%vreg593 SGPR_64:%vreg235
7680B		%vreg582:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg593:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7696B		%vreg582:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg593:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg582,%vreg593 VReg_128:%vreg562
7744B		%vreg236<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg582<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>) VReg_32:%vreg236 SReg_128:%vreg676 VReg_64:%vreg582
7760B		%vreg718<def> = COPY %vreg235; VReg_64:%vreg718 SGPR_64:%vreg235
7904B		%vreg707:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg718:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7920B		%vreg707:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg718:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg707,%vreg718 VReg_128:%vreg687
7968B		%vreg238<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg707<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg238 SReg_128:%vreg676 VReg_64:%vreg707
7984B		%vreg240<def> = V_SUB_F32_e32 %vreg238<kill>, %vreg236<kill>, %EXEC<imp-use>; VGPR_32:%vreg240,%vreg238 VReg_32:%vreg236
8000B		%vreg250:sub1<def> = V_MUL_F32_e32 %vreg240<kill>, %vreg240, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg240
8032B		%vreg243:sub1<def> = S_MOV_B32 -1[TF=2]; SGPR_64:%vreg243
8048B		%vreg578<def> = COPY %vreg243; VReg_64:%vreg578 SGPR_64:%vreg243
8192B		%vreg567:sub0<def,read-undef> = V_ADD_I32_e32 %vreg562:sub0, %vreg578:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8208B		%vreg567:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1, %vreg578:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg567,%vreg578 VReg_128:%vreg562
8256B		%vreg244<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg567<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>) VReg_32:%vreg244 SReg_128:%vreg676 VReg_64:%vreg567
8272B		%vreg703<def> = COPY %vreg243; VReg_64:%vreg703 SGPR_64:%vreg243
8416B		%vreg692:sub0<def,read-undef> = V_ADD_I32_e32 %vreg687:sub0, %vreg703:sub0, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8432B		%vreg692:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1, %vreg703:sub1<kill>, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>; VReg_64:%vreg692,%vreg703 VReg_128:%vreg687
8480B		%vreg246<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg676, %vreg692<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg246 SReg_128:%vreg676 VReg_64:%vreg692
8496B		%vreg248<def> = V_SUB_F32_e32 %vreg246<kill>, %vreg244<kill>, %EXEC<imp-use>; VGPR_32:%vreg248,%vreg246 VReg_32:%vreg244
8512B		%vreg250:sub0<def> = V_MUL_F32_e32 %vreg248<kill>, %vreg248, %EXEC<imp-use>; VReg_512:%vreg250 VGPR_32:%vreg248
8816B		%vreg253<def> = V_ADD_F32_e32 %vreg250:sub0, %vreg250:sub1, %EXEC<imp-use>; VGPR_32:%vreg253 VReg_512:%vreg250
8848B		%vreg255<def> = V_ADD_F32_e32 %vreg250:sub2, %vreg253<kill>, %EXEC<imp-use>; VGPR_32:%vreg255,%vreg253 VReg_512:%vreg250
8880B		%vreg257<def> = V_ADD_F32_e32 %vreg250:sub3, %vreg255<kill>, %EXEC<imp-use>; VGPR_32:%vreg257,%vreg255 VReg_512:%vreg250
8912B		%vreg259<def> = V_ADD_F32_e32 %vreg250:sub4, %vreg257<kill>, %EXEC<imp-use>; VGPR_32:%vreg259,%vreg257 VReg_512:%vreg250
8944B		%vreg261<def> = V_ADD_F32_e32 %vreg250:sub5, %vreg259<kill>, %EXEC<imp-use>; VGPR_32:%vreg261,%vreg259 VReg_512:%vreg250
8976B		%vreg263<def> = V_ADD_F32_e32 %vreg250:sub6, %vreg261<kill>, %EXEC<imp-use>; VGPR_32:%vreg263,%vreg261 VReg_512:%vreg250
9008B		%vreg265<def> = V_ADD_F32_e32 %vreg250:sub7, %vreg263<kill>, %EXEC<imp-use>; VGPR_32:%vreg265,%vreg263 VReg_512:%vreg250
9040B		%vreg267<def> = V_ADD_F32_e32 %vreg250:sub8, %vreg265<kill>, %EXEC<imp-use>; VGPR_32:%vreg267,%vreg265 VReg_512:%vreg250
9072B		%vreg269<def> = V_ADD_F32_e32 %vreg250:sub9, %vreg267<kill>, %EXEC<imp-use>; VGPR_32:%vreg269,%vreg267 VReg_512:%vreg250
9104B		%vreg271<def> = V_ADD_F32_e32 %vreg250:sub10, %vreg269<kill>, %EXEC<imp-use>; VGPR_32:%vreg271,%vreg269 VReg_512:%vreg250
9136B		%vreg273<def> = V_ADD_F32_e32 %vreg250:sub11, %vreg271<kill>, %EXEC<imp-use>; VGPR_32:%vreg273,%vreg271 VReg_512:%vreg250
9168B		%vreg275<def> = V_ADD_F32_e32 %vreg250:sub12, %vreg273<kill>, %EXEC<imp-use>; VGPR_32:%vreg275,%vreg273 VReg_512:%vreg250
9200B		%vreg277<def> = V_ADD_F32_e32 %vreg250:sub13, %vreg275<kill>, %EXEC<imp-use>; VGPR_32:%vreg277,%vreg275 VReg_512:%vreg250
9232B		%vreg279<def> = V_ADD_F32_e32 %vreg250:sub14, %vreg277<kill>, %EXEC<imp-use>; VGPR_32:%vreg279,%vreg277 VReg_512:%vreg250
9264B		%vreg281<def> = V_ADD_F32_e32 %vreg250:sub15<kill>, %vreg279<kill>, %EXEC<imp-use>; VGPR_32:%vreg281,%vreg279 VReg_512:%vreg250
9280B		%vreg856<def> = V_ADD_F32_e32 %vreg856<kill>, %vreg281<kill>, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg281
9360B		%vreg687:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg687:sub0<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg687 SGPR_64:%vreg283
9376B		%vreg818<def> = COPY %vreg283:sub1; VReg_32:%vreg818 SGPR_64:%vreg283
9392B		%vreg687:sub1<def> = V_ADDC_U32_e32 %vreg687:sub1<kill>, %vreg818<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg687 VReg_32:%vreg818
9472B		%vreg562:sub0<def> = V_ADD_I32_e32 %vreg283:sub0, %vreg562:sub0<kill>, %EXEC<imp-use>, %VCC<imp-def>; VReg_128:%vreg562 SGPR_64:%vreg283
9488B		%vreg827<def> = COPY %vreg283:sub1; VReg_32:%vreg827 SGPR_64:%vreg283
9504B		%vreg562:sub1<def> = V_ADDC_U32_e32 %vreg562:sub1<kill>, %vreg827<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_128:%vreg562 VReg_32:%vreg827
9552B		%vreg296<def> = COPY %vreg9; VGPR_32:%vreg296 SReg_32:%vreg9
9568B		%vreg854<def> = V_ADD_I32_e32 16, %vreg854<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg854
9584B		%vreg297<def> = V_CMP_GE_I32_e64 %vreg854, %vreg296<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg297 VReg_32:%vreg854 VGPR_32:%vreg296
9600B		%vreg851:sub0_sub1<def> = SI_IF_BREAK %vreg297<kill>, %vreg851:sub0_sub1<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851 SReg_64:%vreg297
9776B		SI_LOOP %vreg851:sub0_sub1, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg851
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)
> %VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
> %VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
> %VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
> %VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %VGPR30_VGPR31<def> = COPY %SGPR24_SGPR25
> %VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
> %VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
> %VGPR31_VGPR32<def> = COPY %SGPR24_SGPR25
> %VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
> %VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
> %VGPR30_VGPR31<def> = COPY %SGPR26_SGPR27
> %VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
> %VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
> %VGPR31_VGPR32<def> = COPY %SGPR26_SGPR27
> %VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
> %VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
> %VGPR30_VGPR31<def> = COPY %SGPR28_SGPR29
> %VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
> %VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
> %VGPR31_VGPR32<def> = COPY %SGPR28_SGPR29
> %VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
> %VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
> %VGPR30_VGPR31<def> = COPY %SGPR30_SGPR31
> %VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
> %VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
> %VGPR31_VGPR32<def> = COPY %SGPR30_SGPR31
> %VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
> %VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
> %VGPR30_VGPR31<def> = COPY %SGPR32_SGPR33
> %VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
> %VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
> %VGPR31_VGPR32<def> = COPY %SGPR32_SGPR33
> %VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
> %VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
> %VGPR30_VGPR31<def> = COPY %SGPR34_SGPR35
> %VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
> %VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
> %VGPR31_VGPR32<def> = COPY %SGPR34_SGPR35
> %VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
> %VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
> %VGPR30_VGPR31<def> = COPY %SGPR36_SGPR37
> %VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
> %VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
> %VGPR31_VGPR32<def> = COPY %SGPR36_SGPR37
> %VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
> %VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
> %VGPR30_VGPR31<def> = COPY %SGPR38_SGPR39
> %VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
> %VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
> %VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
> %VGPR31_VGPR32<def> = COPY %SGPR38_SGPR39
> %VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
> %VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
> %VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
> %VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
> %VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
> %VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
> %VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
> %VGPR14<def> = COPY %SGPR41
> %VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
> %VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
> %VGPR14<def> = COPY %SGPR41
> %VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
> %VGPR14<def> = COPY %SGPR17
> %VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
> %SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
> %SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
> SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#3>
9808B	BB#9: derived from LLVM BB %Flow46
	    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %vreg302<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg302
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12
> SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#12>
9872B	BB#10: derived from LLVM BB %for.body31
	    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
	    Predecessors according to CFG: BB#6 BB#10
10032B		%vreg830:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg858:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg830,%vreg858 SGPR_64:%vreg353
10048B		%vreg836<def> = COPY %vreg353:sub1; VReg_32:%vreg836 SGPR_64:%vreg353
10064B		%vreg830:sub1<def> = V_ADDC_U32_e32 %vreg858:sub1, %vreg836<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg830,%vreg858 VReg_32:%vreg836
10144B		%vreg839:sub0<def,read-undef> = V_ADD_I32_e32 %vreg353:sub0, %vreg859:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg839,%vreg859 SGPR_64:%vreg353
10160B		%vreg845<def> = COPY %vreg353:sub1; VReg_32:%vreg845 SGPR_64:%vreg353
10176B		%vreg839:sub1<def> = V_ADDC_U32_e32 %vreg859:sub1, %vreg845<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg839,%vreg859 VReg_32:%vreg845
10288B		%vreg367<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg859<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>) VReg_32:%vreg367 SReg_128:%vreg366 VReg_64:%vreg859
10304B		%vreg368<def> = BUFFER_LOAD_DWORD_ADDR64 %vreg366, %vreg858<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg368 SReg_128:%vreg366 VReg_64:%vreg858
10320B		%vreg369<def> = V_SUB_F32_e32 %vreg368<kill>, %vreg367<kill>, %EXEC<imp-use>; VGPR_32:%vreg369,%vreg368 VReg_32:%vreg367
10336B		%vreg856<def> = V_MAD_F32 %vreg369<kill>, %vreg369, %vreg856<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg856,%vreg369,%vreg369
10352B		%vreg860<def> = V_ADD_I32_e32 -1, %vreg860<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_32:%vreg860
10368B		%vreg371<def> = V_CMP_EQ_I32_e64 %vreg860, 0, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg371 VReg_32:%vreg860
10384B		%vreg857:sub0_sub1<def> = SI_IF_BREAK %vreg371<kill>, %vreg857:sub0_sub1<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857 SReg_64:%vreg371
10496B		%vreg858<def> = COPY %vreg830<kill>; VReg_64:%vreg858,%vreg830
10512B		%vreg859<def> = COPY %vreg839<kill>; VReg_64:%vreg859,%vreg839
10560B		SI_LOOP %vreg857:sub0_sub1, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)
> %VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
> %VGPR1<def> = COPY %SGPR3
> %VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
> %VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
> %VGPR1<def> = COPY %SGPR3
> %VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
> %VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
> %VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
> %VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
> %VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
> %SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
> %SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
> %VGPR8_VGPR9<def> = COPY %VGPR6_VGPR7<kill>
> %VGPR10_VGPR11<def> = COPY %VGPR12_VGPR13<kill>
> SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#11>
10592B	BB#11: derived from LLVM BB %Flow45
	    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %vreg857:sub0_sub1<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_128:%vreg857
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9
> SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
> S_BRANCH <BB#9>
10656B	BB#12: derived from LLVM BB %for.end48
	    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
	    Predecessors according to CFG: BB#9
10672B		%vreg373<def> = COPY %vreg54<kill>; VGPR_32:%vreg373 SGPR_32:%vreg54
10688B		%vreg374<def> = V_MUL_LO_I32 %vreg440<kill>, %vreg373<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>; VReg_32:%vreg374,%vreg440 VGPR_32:%vreg373
10704B		%vreg425:sub0<def,read-undef> = V_ADD_I32_e32 %vreg374<kill>, %vreg423<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>; VReg_64:%vreg425 VReg_32:%vreg374,%vreg423
10720B		%vreg425:sub1<def> = V_ASHRREV_I32_e32 31, %vreg425:sub0<kill>, %EXEC<imp-use>; VReg_64:%vreg425
10768B		%vreg428<def> = V_LSHL_B64 %vreg425<kill>, 2, %EXEC<imp-use>; VReg_64:%vreg428,%vreg425
10816B		%vreg847<def> = COPY %vreg53:sub0; VReg_32:%vreg847 SReg_64_with_sub0:%vreg53
10832B		%vreg848<def> = COPY %vreg53:sub1<kill>; VReg_32:%vreg848 SReg_64_with_sub0:%vreg53
10848B		%vreg45:sub0<def,read-undef> = V_ADD_I32_e32 %vreg847<kill>, %vreg428:sub0, %EXEC<imp-use>, %VCC<imp-def>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg847
10864B		%vreg45:sub1<def> = V_ADDC_U32_e32 %vreg848<kill>, %vreg428:sub1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>; VReg_64:%vreg45,%vreg428 VReg_32:%vreg848
10912B		%vreg388<def> = V_MUL_F32_e64 %vreg856<kill>, %vreg56<kill>, 0, 0, 0, 0, %EXEC<imp-use>; VGPR_32:%vreg388,%vreg856,%vreg56
10928B		%vreg389<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>; VGPR_32:%vreg389
10944B		%vreg390<def> = V_CMP_LE_F32_e64 %vreg388, %vreg389<kill>, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg390 VGPR_32:%vreg388,%vreg389
10960B		%vreg391<def> = V_CMP_U_F32_e64 %vreg388, %vreg388, 0, 0, 0, 0, %EXEC<imp-use>; SReg_64:%vreg391 VGPR_32:%vreg388
10976B		%vreg392<def> = S_OR_B64 %vreg390<kill>, %vreg391<kill>; SReg_64:%vreg392,%vreg390,%vreg391
11008B		%vreg395<def> = SI_IF %vreg392<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395,%vreg392
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)
> %VGPR0<def> = COPY %SGPR6<kill>
> %VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
> %VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
> %VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
> %VGPR0<def> = COPY %SGPR4
> %VGPR6<def> = COPY %SGPR5, %SGPR4_SGPR5<imp-use,kill>
> %VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
> %VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
> %VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
> %VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
> %SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
> %SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
> %SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
> %SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#15>
11040B	BB#13: derived from LLVM BB %Flow
	    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
	    Predecessors according to CFG: BB#12 BB#15
11072B		%vreg395<def,tied1> = SI_ELSE %vreg395<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)
> %SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#14>
11104B	BB#14: derived from LLVM BB %if.then51
	    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
	    Predecessors according to CFG: BB#13
11120B		%vreg396:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg396
11136B		%vreg396:sub2<def> = S_MOV_B32 0; SReg_128:%vreg396
11152B		%vreg396:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg396
11232B		%vreg397<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>; VReg_32:%vreg397
11248B		BUFFER_STORE_DWORD %vreg397<kill>, %vreg396<kill>, %vreg45<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VReg_32:%vreg397 SReg_128:%vreg396 VReg_64:%vreg45
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16
> %SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
> %SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
> %SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
> %VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
> BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
> S_BRANCH <BB#16>
11280B	BB#15: derived from LLVM BB %if.else
	    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
	    Predecessors according to CFG: BB#12
11312B		%vreg394:sub0_sub1<def,read-undef> = S_MOV_B64 0; SReg_128:%vreg394
11328B		%vreg394:sub2<def> = S_MOV_B32 0; SReg_128:%vreg394
11344B		%vreg394:sub3<def> = S_MOV_B32 61440; SReg_128:%vreg394
11424B		BUFFER_STORE_DWORD %vreg388<kill>, %vreg394<kill>, %vreg45, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>) VGPR_32:%vreg388 SReg_128:%vreg394 VReg_64:%vreg45
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13
> %SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
> %SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
> %SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
> BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
> S_BRANCH <BB#13>
11456B	BB#16: derived from LLVM BB %Flow44
	    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %vreg395<kill>, %EXEC<imp-def>, %EXEC<imp-use>; SReg_64:%vreg395
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4
> SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
> S_BRANCH <BB#4>
11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM
> S_ENDPGM
# *** IR Dump Before Stack Slot Coloring ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

0B	BB#0: derived from LLVM BB %entry
	    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
96B		%VGPR2<def> = COPY %SGPR2
112B		%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
128B		%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
144B		%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
160B		%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
176B		%VGPR3<def> = COPY %SGPR4<kill>
192B		%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
208B		%VGPR3<def> = COPY %SGPR3
224B		%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
240B		%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
256B		%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
272B		%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
288B		%VGPR4<def> = COPY %SGPR6<kill>
304B		%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
320B		%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
336B		%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
352B		%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
368B		%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
384B		%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
400B		%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
416B		%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
432B		%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
448B		%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
464B		%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
480B		S_BRANCH <BB#1>
	    Successors according to CFG: BB#1(16) BB#4(16)

496B	BB#1: derived from LLVM BB %for.cond.preheader
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
	    Predecessors according to CFG: BB#0
688B		%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
704B		%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
720B		%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
752B		%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
832B		%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
848B		S_BRANCH <BB#2>
	    Successors according to CFG: BB#2(16) BB#7(16)

864B	BB#2: derived from LLVM BB %for.body.lr.ph
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
	    Predecessors according to CFG: BB#1
880B		%VGPR4<def> = COPY %SGPR3
896B		%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
912B		%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
928B		%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
944B		%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
992B		%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
1040B		%VGPR6<def> = COPY %SGPR12
1056B		%VGPR7<def> = COPY %SGPR13
1072B		%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
1088B		%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
1168B		%SGPR20_SGPR21<def> = S_MOV_B64 32
1216B		%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
1232B		%VGPR4<def> = COPY %SGPR21
1248B		%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
1296B		%VGPR4<def> = COPY %SGPR2
1312B		%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
1328B		%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
1344B		%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
1360B		%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
1408B		%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
1456B		%VGPR4<def> = COPY %SGPR10
1472B		%VGPR11<def> = COPY %SGPR11
1488B		%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
1504B		%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
1584B		%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
1600B		%VGPR4<def> = COPY %SGPR21, %SGPR20_SGPR21<imp-use,kill>
1616B		%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
1664B		%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
1696B		%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
1728B		%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
1792B		%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
1808B		%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
1824B		%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
1840B		%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
1856B		%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
1872B		%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
1888B		%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
1904B		%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
1920B		%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
1936B		%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
1952B		%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
1968B		%SGPR40_SGPR41<def> = S_MOV_B64 64
2080B		S_BRANCH <BB#8>
	    Successors according to CFG: BB#8

2096B	BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
	    Predecessors according to CFG: BB#8
2112B		SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
2128B		%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
2144B		%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
2160B		%VGPR6<def> = COPY %SGPR17<kill>, %VGPR6_VGPR7<imp-def>
2208B		S_BRANCH <BB#7>
	    Successors according to CFG: BB#7

2224B	BB#4: derived from LLVM BB %Flow48
	    Live Ins: %SGPR0_SGPR1
	    Predecessors according to CFG: BB#0 BB#16
2240B		SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
2256B		S_BRANCH <BB#17>
	    Successors according to CFG: BB#17

2272B	BB#5: derived from LLVM BB %for.cond29.preheader
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
	    Predecessors according to CFG: BB#7
2288B		%VGPR8<def> = COPY %SGPR7
2304B		%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
2336B		%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
2352B		S_BRANCH <BB#6>
	    Successors according to CFG: BB#6(16) BB#9(16)

2368B	BB#6: derived from LLVM BB %for.body31.lr.ph
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
	    Predecessors according to CFG: BB#5
2384B		%VGPR8<def> = COPY %SGPR3<kill>
2400B		%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
2416B		%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
2432B		%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
2448B		%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
2528B		%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
2608B		%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
2624B		%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
2672B		%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
2720B		%VGPR1<def> = COPY %SGPR12
2736B		%VGPR12<def> = COPY %SGPR13, %SGPR12_SGPR13<imp-use,kill>
2752B		%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
2768B		%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
2816B		%VGPR1<def> = COPY %SGPR2<kill>
2832B		%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
2848B		%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
2864B		%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
2880B		%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
2960B		%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
2976B		%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
3024B		%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
3072B		%VGPR10<def> = COPY %SGPR10
3088B		%VGPR12<def> = COPY %SGPR11, %SGPR10_SGPR11<imp-use,kill>
3104B		%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
3120B		%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
3168B		%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
3184B		%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
3248B		%SGPR2_SGPR3<def> = S_MOV_B64 4
3264B		%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
3280B		%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
3392B		S_BRANCH <BB#10>
	    Successors according to CFG: BB#10

3408B	BB#7: derived from LLVM BB %Flow47
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
	    Predecessors according to CFG: BB#1 BB#3
3456B		%VGPR5<def> = COPY %SGPR16<kill>
3504B		SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
3536B		S_BRANCH <BB#5>
	    Successors according to CFG: BB#5

3552B	BB#8: derived from LLVM BB %for.body
	    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
	    Predecessors according to CFG: BB#2 BB#8
3712B		%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
3728B		%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
3744B		%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
3760B		%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
3776B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
3792B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
3808B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
3824B		%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
3840B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
3856B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
3872B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
3888B		%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
3904B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
3920B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
3936B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
3952B		%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
3968B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
3984B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
4000B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
4016B		%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
4032B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
4048B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
4064B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
4080B		%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
4096B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
4112B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
4128B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
4144B		%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
4160B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
4176B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
4192B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
4208B		%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
4336B		%VGPR30_VGPR31<def> = COPY %SGPR24_SGPR25
4480B		%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
4496B		%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
4592B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
4688B		%VGPR31_VGPR32<def> = COPY %SGPR24_SGPR25
4832B		%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
4848B		%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
4896B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
4912B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
4928B		%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
4960B		%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
4976B		%VGPR30_VGPR31<def> = COPY %SGPR26_SGPR27
5120B		%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
5136B		%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
5184B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
5200B		%VGPR31_VGPR32<def> = COPY %SGPR26_SGPR27
5344B		%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
5360B		%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
5408B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
5424B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
5440B		%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
5472B		%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
5488B		%VGPR30_VGPR31<def> = COPY %SGPR28_SGPR29
5632B		%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
5648B		%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
5696B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
5712B		%VGPR31_VGPR32<def> = COPY %SGPR28_SGPR29
5856B		%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
5872B		%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
5920B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
5936B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
5952B		%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
5984B		%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
6000B		%VGPR30_VGPR31<def> = COPY %SGPR30_SGPR31
6144B		%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
6160B		%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
6208B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
6224B		%VGPR31_VGPR32<def> = COPY %SGPR30_SGPR31
6368B		%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
6384B		%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
6432B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
6448B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
6464B		%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
6496B		%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
6512B		%VGPR30_VGPR31<def> = COPY %SGPR32_SGPR33
6656B		%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
6672B		%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
6720B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
6736B		%VGPR31_VGPR32<def> = COPY %SGPR32_SGPR33
6880B		%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
6896B		%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
6944B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
6960B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
6976B		%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
7008B		%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
7024B		%VGPR30_VGPR31<def> = COPY %SGPR34_SGPR35
7168B		%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
7184B		%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
7232B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
7248B		%VGPR31_VGPR32<def> = COPY %SGPR34_SGPR35
7392B		%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
7408B		%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
7456B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
7472B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
7488B		%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
7520B		%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
7536B		%VGPR30_VGPR31<def> = COPY %SGPR36_SGPR37
7680B		%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
7696B		%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
7744B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
7760B		%VGPR31_VGPR32<def> = COPY %SGPR36_SGPR37
7904B		%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
7920B		%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
7968B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
7984B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
8000B		%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
8032B		%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
8048B		%VGPR30_VGPR31<def> = COPY %SGPR38_SGPR39
8192B		%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
8208B		%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
8256B		%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
8272B		%VGPR31_VGPR32<def> = COPY %SGPR38_SGPR39
8416B		%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
8432B		%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
8480B		%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
8496B		%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
8512B		%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
8816B		%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
8848B		%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
8880B		%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
8912B		%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
8944B		%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
8976B		%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
9008B		%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
9040B		%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
9072B		%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
9104B		%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
9136B		%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
9168B		%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
9200B		%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
9232B		%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
9264B		%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
9280B		%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
9360B		%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
9376B		%VGPR14<def> = COPY %SGPR41
9392B		%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
9472B		%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
9488B		%VGPR14<def> = COPY %SGPR41
9504B		%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
9552B		%VGPR14<def> = COPY %SGPR17
9568B		%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
9584B		%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
9600B		%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
9776B		SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
9792B		S_BRANCH <BB#3>
	    Successors according to CFG: BB#3(4) BB#8(124)

9808B	BB#9: derived from LLVM BB %Flow46
	    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
	    Predecessors according to CFG: BB#5 BB#11
9840B		SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
9856B		S_BRANCH <BB#12>
	    Successors according to CFG: BB#12

9872B	BB#10: derived from LLVM BB %for.body31
	    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
	    Predecessors according to CFG: BB#6 BB#10
10032B		%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
10048B		%VGPR1<def> = COPY %SGPR3
10064B		%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
10144B		%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
10160B		%VGPR1<def> = COPY %SGPR3
10176B		%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
10288B		%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
10304B		%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
10320B		%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
10336B		%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
10352B		%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
10368B		%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
10384B		%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
10496B		%VGPR8_VGPR9<def> = COPY %VGPR6_VGPR7<kill>
10512B		%VGPR10_VGPR11<def> = COPY %VGPR12_VGPR13<kill>
10560B		SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
10576B		S_BRANCH <BB#11>
	    Successors according to CFG: BB#11(4) BB#10(124)

10592B	BB#11: derived from LLVM BB %Flow45
	    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
	    Predecessors according to CFG: BB#10
10608B		SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
10640B		S_BRANCH <BB#9>
	    Successors according to CFG: BB#9

10656B	BB#12: derived from LLVM BB %for.end48
	    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
	    Predecessors according to CFG: BB#9
10672B		%VGPR0<def> = COPY %SGPR6<kill>
10688B		%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
10704B		%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
10720B		%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
10768B		%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
10816B		%VGPR0<def> = COPY %SGPR4
10832B		%VGPR6<def> = COPY %SGPR5, %SGPR4_SGPR5<imp-use,kill>
10848B		%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
10864B		%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
10912B		%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
10928B		%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
10944B		%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
10960B		%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
10976B		%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
11008B		%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
11024B		S_BRANCH <BB#15>
	    Successors according to CFG: BB#15(16) BB#13(16)

11040B	BB#13: derived from LLVM BB %Flow
	    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
	    Predecessors according to CFG: BB#12 BB#15
11072B		%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
11088B		S_BRANCH <BB#14>
	    Successors according to CFG: BB#14(16) BB#16(16)

11104B	BB#14: derived from LLVM BB %if.then51
	    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
	    Predecessors according to CFG: BB#13
11120B		%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
11136B		%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
11152B		%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
11232B		%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
11248B		BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
11264B		S_BRANCH <BB#16>
	    Successors according to CFG: BB#16

11280B	BB#15: derived from LLVM BB %if.else
	    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
	    Predecessors according to CFG: BB#12
11312B		%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
11328B		%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
11344B		%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
11424B		BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
11440B		S_BRANCH <BB#13>
	    Successors according to CFG: BB#13

11456B	BB#16: derived from LLVM BB %Flow44
	    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
	    Predecessors according to CFG: BB#13 BB#14
11472B		SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
11488B		S_BRANCH <BB#4>
	    Successors according to CFG: BB#4

11504B	BB#17: derived from LLVM BB %if.end58
	    Predecessors according to CFG: BB#4
11520B		S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Machine Loop Invariant Code Motion ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%VGPR2<def> = COPY %SGPR2
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
	%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
	%VGPR3<def> = COPY %SGPR4<kill>
	%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = COPY %SGPR3
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
	%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
	%VGPR4<def> = COPY %SGPR6<kill>
	%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
	%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
	%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
	%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
	%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#0
	%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR4<def> = COPY %SGPR3
	%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
	%VGPR6<def> = COPY %SGPR12
	%VGPR7<def> = COPY %SGPR13
	%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR20_SGPR21<def> = S_MOV_B64 32
	%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR21
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR2
	%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
	%VGPR4<def> = COPY %SGPR10
	%VGPR11<def> = COPY %SGPR11
	%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = COPY %SGPR21, %SGPR20_SGPR21<imp-use,kill>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
	%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
	%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
	%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
	%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
	%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
	%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
	%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
	%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
	%SGPR40_SGPR41<def> = S_MOV_B64 64
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
    Predecessors according to CFG: BB#8
	SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
	%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
	%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
	%VGPR6<def> = COPY %SGPR17<kill>, %VGPR6_VGPR7<imp-def>
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Live Ins: %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#7
	%VGPR8<def> = COPY %SGPR7
	%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#5
	%VGPR8<def> = COPY %SGPR3<kill>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = COPY %SGPR12
	%VGPR12<def> = COPY %SGPR13, %SGPR12_SGPR13<imp-use,kill>
	%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = COPY %SGPR2<kill>
	%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR10<def> = COPY %SGPR10
	%VGPR12<def> = COPY %SGPR11, %SGPR10_SGPR11<imp-use,kill>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
	%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR2_SGPR3<def> = S_MOV_B64 4
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#1 BB#3
	%VGPR5<def> = COPY %SGPR16<kill>
	SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
    Predecessors according to CFG: BB#2 BB#8
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
	%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR24_SGPR25
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR24_SGPR25
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR26_SGPR27
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR26_SGPR27
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR28_SGPR29
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR28_SGPR29
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR30_SGPR31
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR30_SGPR31
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR32_SGPR33
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR32_SGPR33
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR34_SGPR35
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR34_SGPR35
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR36_SGPR37
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR36_SGPR37
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR38_SGPR39
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR38_SGPR39
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR17
	%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
	SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#5 BB#11
	SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
    Predecessors according to CFG: BB#6 BB#10
	%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
	%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
	%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
	%VGPR8_VGPR9<def> = COPY %VGPR6_VGPR7<kill>
	%VGPR10_VGPR11<def> = COPY %VGPR12_VGPR13<kill>
	SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
    Predecessors according to CFG: BB#10
	SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#9
	%VGPR0<def> = COPY %SGPR6<kill>
	%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
	%VGPR0<def> = COPY %SGPR4
	%VGPR6<def> = COPY %SGPR5, %SGPR4_SGPR5<imp-use,kill>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12 BB#15
	%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Prologue/Epilogue Insertion & Frame Finalization ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%VGPR2<def> = COPY %SGPR2
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = COPY %SGPR4<kill>
	%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = COPY %SGPR3
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR4<def> = COPY %SGPR6<kill>
	%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
	%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
	%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
	%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#0
	%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR4<def> = COPY %SGPR3
	%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
	%VGPR6<def> = COPY %SGPR12
	%VGPR7<def> = COPY %SGPR13
	%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR20_SGPR21<def> = S_MOV_B64 32
	%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR21
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR2
	%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
	%VGPR4<def> = COPY %SGPR10
	%VGPR11<def> = COPY %SGPR11
	%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = COPY %SGPR21, %SGPR20_SGPR21<imp-use,kill>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
	%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
	%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
	%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
	%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
	%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
	%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
	%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
	%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
	%SGPR40_SGPR41<def> = S_MOV_B64 64
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
    Predecessors according to CFG: BB#8
	SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
	%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
	%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
	%VGPR6<def> = COPY %SGPR17<kill>, %VGPR6_VGPR7<imp-def>
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Live Ins: %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#7
	%VGPR8<def> = COPY %SGPR7
	%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#5
	%VGPR8<def> = COPY %SGPR3<kill>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = COPY %SGPR12
	%VGPR12<def> = COPY %SGPR13, %SGPR12_SGPR13<imp-use,kill>
	%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = COPY %SGPR2<kill>
	%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR10<def> = COPY %SGPR10
	%VGPR12<def> = COPY %SGPR11, %SGPR10_SGPR11<imp-use,kill>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
	%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR2_SGPR3<def> = S_MOV_B64 4
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#1 BB#3
	%VGPR5<def> = COPY %SGPR16<kill>
	SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
    Predecessors according to CFG: BB#2 BB#8
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR24_SGPR25
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR24_SGPR25
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR26_SGPR27
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR26_SGPR27
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR28_SGPR29
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR28_SGPR29
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR30_SGPR31
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR30_SGPR31
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR32_SGPR33
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR32_SGPR33
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR34_SGPR35
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR34_SGPR35
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR36_SGPR37
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR36_SGPR37
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR38_SGPR39
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR38_SGPR39
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR17
	%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
	SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#5 BB#11
	SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
    Predecessors according to CFG: BB#6 BB#10
	%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
	%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
	%VGPR8_VGPR9<def> = COPY %VGPR6_VGPR7<kill>
	%VGPR10_VGPR11<def> = COPY %VGPR12_VGPR13<kill>
	SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
    Predecessors according to CFG: BB#10
	SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#9
	%VGPR0<def> = COPY %SGPR6<kill>
	%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
	%VGPR0<def> = COPY %SGPR4
	%VGPR6<def> = COPY %SGPR5, %SGPR4_SGPR5<imp-use,kill>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12 BB#15
	%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Control Flow Optimizer ***:
# Machine code for function svm_rbf: Post SSA
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%VGPR2<def> = COPY %SGPR2
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = COPY %SGPR4<kill>
	%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = COPY %SGPR3
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR4<def> = COPY %SGPR6<kill>
	%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
	%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
	%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
	%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#0
	%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR4<def> = COPY %SGPR3
	%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
	%VGPR6<def> = COPY %SGPR12
	%VGPR7<def> = COPY %SGPR13
	%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR20_SGPR21<def> = S_MOV_B64 32
	%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR21
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR2
	%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
	%VGPR4<def> = COPY %SGPR10
	%VGPR11<def> = COPY %SGPR11
	%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = COPY %SGPR21, %SGPR20_SGPR21<imp-use,kill>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
	%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
	%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
	%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
	%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
	%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
	%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
	%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
	%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
	%SGPR40_SGPR41<def> = S_MOV_B64 64
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
    Predecessors according to CFG: BB#8
	SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
	%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
	%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
	%VGPR6<def> = COPY %SGPR17<kill>, %VGPR6_VGPR7<imp-def>
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Live Ins: %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#7
	%VGPR8<def> = COPY %SGPR7
	%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#5
	%VGPR8<def> = COPY %SGPR3<kill>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = COPY %SGPR12
	%VGPR12<def> = COPY %SGPR13, %SGPR12_SGPR13<imp-use,kill>
	%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = COPY %SGPR2<kill>
	%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR10<def> = COPY %SGPR10
	%VGPR12<def> = COPY %SGPR11, %SGPR10_SGPR11<imp-use,kill>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
	%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR2_SGPR3<def> = S_MOV_B64 4
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#1 BB#3
	%VGPR5<def> = COPY %SGPR16<kill>
	SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
    Predecessors according to CFG: BB#2 BB#8
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR24_SGPR25
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR24_SGPR25
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR26_SGPR27
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR26_SGPR27
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR28_SGPR29
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR28_SGPR29
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR30_SGPR31
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR30_SGPR31
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR32_SGPR33
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR32_SGPR33
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR34_SGPR35
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR34_SGPR35
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR36_SGPR37
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR36_SGPR37
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR38_SGPR39
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR38_SGPR39
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR17
	%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
	SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#5 BB#11
	SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
    Predecessors according to CFG: BB#6 BB#10
	%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
	%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
	%VGPR8_VGPR9<def> = COPY %VGPR6_VGPR7<kill>
	%VGPR10_VGPR11<def> = COPY %VGPR12_VGPR13<kill>
	SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
    Predecessors according to CFG: BB#10
	SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#9
	%VGPR0<def> = COPY %SGPR6<kill>
	%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
	%VGPR0<def> = COPY %SGPR4
	%VGPR6<def> = COPY %SGPR5, %SGPR4_SGPR5<imp-use,kill>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12 BB#15
	%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Machine Copy Propagation Pass ***:
# Machine code for function svm_rbf: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%VGPR2<def> = COPY %SGPR2
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = COPY %SGPR4<kill>
	%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = COPY %SGPR3
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR4<def> = COPY %SGPR6<kill>
	%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
	%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
	%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
	%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#0
	%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR4<def> = COPY %SGPR3
	%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
	%VGPR6<def> = COPY %SGPR12
	%VGPR7<def> = COPY %SGPR13
	%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR20_SGPR21<def> = S_MOV_B64 32
	%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR21
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR2
	%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
	%VGPR4<def> = COPY %SGPR10
	%VGPR11<def> = COPY %SGPR11
	%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = COPY %SGPR21, %SGPR20_SGPR21<imp-use,kill>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
	%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
	%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
	%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
	%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
	%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
	%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
	%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
	%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
	%SGPR40_SGPR41<def> = S_MOV_B64 64
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
    Predecessors according to CFG: BB#8
	SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
	%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
	%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
	%VGPR6<def> = COPY %SGPR17<kill>, %VGPR6_VGPR7<imp-def>
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Live Ins: %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#7
	%VGPR8<def> = COPY %SGPR7
	%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#5
	%VGPR8<def> = COPY %SGPR3<kill>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = COPY %SGPR12
	%VGPR12<def> = COPY %SGPR13, %SGPR12_SGPR13<imp-use,kill>
	%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = COPY %SGPR2<kill>
	%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR10<def> = COPY %SGPR10
	%VGPR12<def> = COPY %SGPR11, %SGPR10_SGPR11<imp-use,kill>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
	%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR2_SGPR3<def> = S_MOV_B64 4
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#1 BB#3
	%VGPR5<def> = COPY %SGPR16<kill>
	SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
    Predecessors according to CFG: BB#2 BB#8
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR24_SGPR25
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR24_SGPR25
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR26_SGPR27
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR26_SGPR27
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR28_SGPR29
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR28_SGPR29
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR30_SGPR31
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR30_SGPR31
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR32_SGPR33
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR32_SGPR33
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR34_SGPR35
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR34_SGPR35
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR36_SGPR37
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR36_SGPR37
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR38_SGPR39
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR38_SGPR39
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR17
	%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
	SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#5 BB#11
	SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
    Predecessors according to CFG: BB#6 BB#10
	%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
	%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
	%VGPR8_VGPR9<def> = COPY %VGPR6_VGPR7<kill>
	%VGPR10_VGPR11<def> = COPY %VGPR12_VGPR13<kill>
	SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
    Predecessors according to CFG: BB#10
	SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#9
	%VGPR0<def> = COPY %SGPR6<kill>
	%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
	%VGPR0<def> = COPY %SGPR4
	%VGPR6<def> = COPY %SGPR5, %SGPR4_SGPR5<imp-use,kill>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12 BB#15
	%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Post-RA pseudo instruction expansion pass ***:
# Machine code for function svm_rbf: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%VGPR2<def> = COPY %SGPR2
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = COPY %SGPR4<kill>
	%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = COPY %SGPR3
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR4<def> = COPY %SGPR6<kill>
	%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
	%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
	%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
	%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#0
	%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR4<def> = COPY %SGPR3
	%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
	%VGPR6<def> = COPY %SGPR12
	%VGPR7<def> = COPY %SGPR13
	%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR20_SGPR21<def> = S_MOV_B64 32
	%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR21
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = COPY %SGPR2
	%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
	%VGPR4<def> = COPY %SGPR10
	%VGPR11<def> = COPY %SGPR11
	%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = COPY %SGPR21, %SGPR20_SGPR21<imp-use,kill>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
	%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
	%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
	%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
	%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
	%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
	%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
	%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
	%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
	%SGPR40_SGPR41<def> = S_MOV_B64 64
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
    Predecessors according to CFG: BB#8
	SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
	%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
	%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
	%VGPR6<def> = COPY %SGPR17<kill>, %VGPR6_VGPR7<imp-def>
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Live Ins: %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#7
	%VGPR8<def> = COPY %SGPR7
	%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#5
	%VGPR8<def> = COPY %SGPR3<kill>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = COPY %SGPR12
	%VGPR12<def> = COPY %SGPR13, %SGPR12_SGPR13<imp-use,kill>
	%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = COPY %SGPR2<kill>
	%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR10<def> = COPY %SGPR10
	%VGPR12<def> = COPY %SGPR11, %SGPR10_SGPR11<imp-use,kill>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
	%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR2_SGPR3<def> = S_MOV_B64 4
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#1 BB#3
	%VGPR5<def> = COPY %SGPR16<kill>
	SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
    Predecessors according to CFG: BB#2 BB#8
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR24_SGPR25
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR24_SGPR25
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR26_SGPR27
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR26_SGPR27
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR28_SGPR29
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR28_SGPR29
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR30_SGPR31
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR30_SGPR31
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR32_SGPR33
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR32_SGPR33
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR34_SGPR35
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR34_SGPR35
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR36_SGPR37
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR36_SGPR37
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
	%VGPR30_VGPR31<def> = COPY %SGPR38_SGPR39
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
	%VGPR31_VGPR32<def> = COPY %SGPR38_SGPR39
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR41
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = COPY %SGPR17
	%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
	SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#5 BB#11
	SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
    Predecessors according to CFG: BB#6 BB#10
	%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = COPY %SGPR3
	%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
	%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
	%VGPR8_VGPR9<def> = COPY %VGPR6_VGPR7<kill>
	%VGPR10_VGPR11<def> = COPY %VGPR12_VGPR13<kill>
	SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
    Predecessors according to CFG: BB#10
	SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#9
	%VGPR0<def> = COPY %SGPR6<kill>
	%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
	%VGPR0<def> = COPY %SGPR4
	%VGPR6<def> = COPY %SGPR5, %SGPR4_SGPR5<imp-use,kill>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12 BB#15
	%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before If Converter ***:
# Machine code for function svm_rbf: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%VGPR2<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
	%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
	%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
	%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#0
	%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR4<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 %SGPR13, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR20_SGPR21<def> = S_MOV_B64 32
	%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR21, %EXEC<imp-use>
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR21, %EXEC<imp-use>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
	%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
	%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
	%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
	%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
	%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
	%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
	%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
	%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
	%SGPR40_SGPR41<def> = S_MOV_B64 64
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
    Predecessors according to CFG: BB#8
	SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
	%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
	%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
	%VGPR6<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Live Ins: %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#7
	%VGPR8<def> = V_MOV_B32_e32 %SGPR7, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#5
	%VGPR8<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR13, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
	%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR2_SGPR3<def> = S_MOV_B64 4
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#1 BB#3
	%VGPR5<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
    Predecessors according to CFG: BB#2 BB#8
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR24, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR25, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR24, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR25, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR26, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR27, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR26, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR27, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR28, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR29, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR28, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR29, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR30, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR31, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR30, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR31, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR32, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR33, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR32, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR33, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR34, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR35, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR34, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR35, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR36, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR37, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR36, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR37, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR38, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR39, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR38, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR39, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR41, %EXEC<imp-use>
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR41, %EXEC<imp-use>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR17, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
	SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#5 BB#11
	SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
    Predecessors according to CFG: BB#6 BB#10
	%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
	%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
	%VGPR8<def> = V_MOV_B32_e32 %VGPR6<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_MOV_B32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %VGPR12<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_MOV_B32_e32 %VGPR13<kill>, %EXEC<imp-use>
	SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
    Predecessors according to CFG: BB#10
	SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#9
	%VGPR0<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
	%VGPR0<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12 BB#15
	%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Post RA top-down list latency scheduler ***:
# Machine code for function svm_rbf: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%VGPR2<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
	%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
	%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
	%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#0
	%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR4<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 %SGPR13, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR20_SGPR21<def> = S_MOV_B64 32
	%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR21, %EXEC<imp-use>
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR21, %EXEC<imp-use>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
	%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
	%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
	%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
	%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
	%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
	%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
	%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
	%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
	%SGPR40_SGPR41<def> = S_MOV_B64 64
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
    Predecessors according to CFG: BB#8
	SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
	%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
	%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
	%VGPR6<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Live Ins: %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#7
	%VGPR8<def> = V_MOV_B32_e32 %SGPR7, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#5
	%VGPR8<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR13, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
	%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR2_SGPR3<def> = S_MOV_B64 4
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#1 BB#3
	%VGPR5<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
    Predecessors according to CFG: BB#2 BB#8
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR24, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR25, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR24, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR25, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR26, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR27, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR26, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR27, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR28, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR29, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR28, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR29, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR30, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR31, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR30, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR31, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR32, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR33, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR32, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR33, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR34, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR35, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR34, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR35, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR36, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR37, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR36, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR37, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR38, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR39, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR38, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR39, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR41, %EXEC<imp-use>
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR41, %EXEC<imp-use>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR17, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
	SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#5 BB#11
	SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
    Predecessors according to CFG: BB#6 BB#10
	%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
	%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
	%VGPR8<def> = V_MOV_B32_e32 %VGPR6<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_MOV_B32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %VGPR12<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_MOV_B32_e32 %VGPR13<kill>, %EXEC<imp-use>
	SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
    Predecessors according to CFG: BB#10
	SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#9
	%VGPR0<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
	%VGPR0<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12 BB#15
	%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Analyze Machine Code For Garbage Collection ***:
# Machine code for function svm_rbf: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%VGPR2<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
	%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
	%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
	%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#0
	%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR4<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 %SGPR13, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR20_SGPR21<def> = S_MOV_B64 32
	%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR21, %EXEC<imp-use>
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR21, %EXEC<imp-use>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
	%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
	%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
	%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
	%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
	%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
	%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
	%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
	%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
	%SGPR40_SGPR41<def> = S_MOV_B64 64
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
    Predecessors according to CFG: BB#8
	SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
	%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
	%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
	%VGPR6<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Live Ins: %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#7
	%VGPR8<def> = V_MOV_B32_e32 %SGPR7, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#5
	%VGPR8<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR13, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
	%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR2_SGPR3<def> = S_MOV_B64 4
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#1 BB#3
	%VGPR5<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
    Predecessors according to CFG: BB#2 BB#8
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR24, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR25, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR24, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR25, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR26, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR27, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR26, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR27, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR28, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR29, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR28, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR29, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR30, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR31, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR30, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR31, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR32, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR33, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR32, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR33, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR34, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR35, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR34, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR35, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR36, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR37, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR36, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR37, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR38, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR39, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR38, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR39, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR41, %EXEC<imp-use>
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR41, %EXEC<imp-use>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR17, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
	SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#5 BB#11
	SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
    Predecessors according to CFG: BB#6 BB#10
	%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
	%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
	%VGPR8<def> = V_MOV_B32_e32 %VGPR6<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_MOV_B32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %VGPR12<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_MOV_B32_e32 %VGPR13<kill>, %EXEC<imp-use>
	SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
    Predecessors according to CFG: BB#10
	SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#9
	%VGPR0<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
	%VGPR0<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12 BB#15
	%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

# *** IR Dump Before Branch Probability Basic Block Placement ***:
# Machine code for function svm_rbf: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg48, %VGPR1 in %vreg57, %SGPR3 in %vreg58, %VGPR0 in %vreg59, %SGPR2 in %vreg60

BB#0: derived from LLVM BB %entry
    Live Ins: %SGPR0_SGPR1 %VGPR1 %SGPR3 %VGPR0 %SGPR2
	%VGPR2<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%SGPR8<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 6; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_LO_I32 %SGPR8, %VGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_I32_e32 %VGPR2<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 21; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_LT_I32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%SGPR14<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 7; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_LO_I32 %SGPR14, %VGPR3<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_I32_e32 %VGPR3<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 20; mem:LD4[undef(addrspace=2)]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_I32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = S_AND_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%SGPR16<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 23; mem:LD4[undef(addrspace=2)]
	%SGPR7<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 22; mem:LD4[undef(addrspace=2)]
	%SGPR6<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 19; mem:LD4[undef(addrspace=2)]
	%SGPR4_SGPR5<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 17; mem:LD8[undef(addrspace=2)]
	%SGPR9<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 15; mem:LD4[undef(addrspace=2)]
	%SGPR10_SGPR11<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1, 13; mem:LD8[undef(addrspace=2)]
	%SGPR15<def> = S_LOAD_DWORD_IMM %SGPR0_SGPR1, 11; mem:LD4[undef(addrspace=2)]
	%SGPR12_SGPR13<def> = S_LOAD_DWORDX2_IMM %SGPR0_SGPR1<kill>, 9; mem:LD8[undef(addrspace=2)]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#4>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#1>
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %for.cond.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#0
	%SGPR17<def> = S_ADD_I32 %SGPR7, -16, %SCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_GT_I32_e64 %SGPR17, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR18_SGPR19<def> = SI_IF %SGPR18_SGPR19<kill>, <BB#7>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#2>
    Successors according to CFG: BB#2(16) BB#7(16)

BB#2: derived from LLVM BB %for.body.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR4<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR14, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR1, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR15, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def> = V_ASHRREV_I32_e32 31, %VGPR4, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4_VGPR5<def> = V_LSHL_B64 %VGPR4_VGPR5<kill>, 2, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 %SGPR13, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_I32_e32 %VGPR6<kill>, %VGPR4, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR5, %VGPR7<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR4_VGPR5<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR20_SGPR21<def> = S_MOV_B64 32
	%VGPR5<def> = V_ADD_I32_e32 %SGPR20, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR21, %EXEC<imp-use>
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR10, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR2, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_LO_I32 %SGPR8, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR9<def> = V_MUL_LO_I32 %SGPR9, %VGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_ASHRREV_I32_e32 31, %VGPR9, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9_VGPR10<def> = V_LSHL_B64 %VGPR9_VGPR10<kill>, 2, %EXEC<imp-use>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 %VGPR4<kill>, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_ADDC_U32_e32 %VGPR10, %VGPR11<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR20, %VGPR13, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR21, %EXEC<imp-use>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR14, %VGPR4<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR13_VGPR14<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_MOV_B64 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR22<def> = S_MOV_B32 0, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR23<def> = S_MOV_B32 61440, %SGPR20_SGPR21_SGPR22_SGPR23<imp-use,kill>, %SGPR20_SGPR21_SGPR22_SGPR23<imp-def>
	%SGPR25<def> = S_MOV_B32 -1, %SGPR24_SGPR25<imp-def>
	%SGPR24<def> = S_MOV_B32 -4, %SGPR24_SGPR25<imp-use,kill>, %SGPR24_SGPR25<imp-def>
	%SGPR26<def> = S_MOV_B32 -8, %SGPR26_SGPR27<imp-def>
	%SGPR28<def> = S_MOV_B32 -12, %SGPR28_SGPR29<imp-def>
	%SGPR30<def> = S_MOV_B32 -16, %SGPR30_SGPR31<imp-def>
	%SGPR32<def> = S_MOV_B32 -20, %SGPR32_SGPR33<imp-def>
	%SGPR34<def> = S_MOV_B32 -24, %SGPR34_SGPR35<imp-def>
	%SGPR36<def> = S_MOV_B32 -28, %SGPR36_SGPR37<imp-def>
	%SGPR38<def> = S_MOV_B32 -32, %SGPR38_SGPR39<imp-def>
	%SGPR40_SGPR41<def> = S_MOV_B64 64
	S_BRANCH <BB#8>
    Successors according to CFG: BB#8

BB#3: derived from LLVM BB %for.cond.for.cond29.preheader_crit_edge
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR4
    Predecessors according to CFG: BB#8
	SI_END_CF %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>
	%SGPR17<def> = S_ADD_I32 %SGPR7, -1, %SCC<imp-def,dead>
	%SGPR17<def> = S_AND_B32 %SGPR17<kill>, -16
	%VGPR6<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	S_BRANCH <BB#7>
    Successors according to CFG: BB#7

BB#4: derived from LLVM BB %Flow48
    Live Ins: %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#16
	SI_END_CF %SGPR0_SGPR1<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#17>
    Successors according to CFG: BB#17

BB#5: derived from LLVM BB %for.cond29.preheader
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#7
	%VGPR8<def> = V_MOV_B32_e32 %SGPR7, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = V_CMP_LT_I32_e64 %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR16_SGPR17<def> = SI_IF %SGPR16_SGPR17<kill>, <BB#9>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#6>
    Successors according to CFG: BB#6(16) BB#9(16)

BB#6: derived from LLVM BB %for.body31.lr.ph
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#5
	%VGPR8<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR14<kill>, %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_I32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR8<def> = V_MUL_LO_I32 %SGPR15<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ASHRREV_I32_e32 31, %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR7<def> = V_ASHRREV_I32_e32 31, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR8, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR9, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR10_VGPR11<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR13, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR11, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9<imp-use,kill>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_LO_I32 %SGPR8<kill>, %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_MUL_LO_I32 %SGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR0, %VGPR6, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR7, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0_VGPR1<def> = V_LSHL_B64 %VGPR10_VGPR11<kill>, 2, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_I32_e32 %VGPR10<kill>, %VGPR0, %EXEC<imp-use>, %VCC<imp-def>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_ADDC_U32_e32 %VGPR12<kill>, %VGPR1, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-use,kill>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR0<def> = V_SUB_I32_e32 %SGPR7<kill>, %VGPR6, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>
	%SGPR8_SGPR9<def> = S_MOV_B64 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR2_SGPR3<def> = S_MOV_B64 4
	%SGPR10<def> = S_MOV_B32 0, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	%SGPR11<def> = S_MOV_B32 61440, %SGPR8_SGPR9_SGPR10_SGPR11<imp-use,kill>, %SGPR8_SGPR9_SGPR10_SGPR11<imp-def>
	S_BRANCH <BB#10>
    Successors according to CFG: BB#10

BB#7: derived from LLVM BB %Flow47
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR6_VGPR7 %VGPR4
    Predecessors according to CFG: BB#1 BB#3
	%VGPR5<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	SI_END_CF %SGPR18_SGPR19<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#5>
    Successors according to CFG: BB#5

BB#8: derived from LLVM BB %for.body
    Live Ins: %SGPR2 %SGPR8 %SGPR3 %SGPR14 %SGPR17 %SGPR12_SGPR13 %SGPR15 %SGPR10_SGPR11 %SGPR9 %SGPR4_SGPR5 %SGPR6 %SGPR7 %SGPR16 %SGPR0_SGPR1 %SGPR18_SGPR19 %SGPR24_SGPR25 %SGPR26_SGPR27 %SGPR28_SGPR29 %SGPR30_SGPR31 %SGPR32_SGPR33 %SGPR34_SGPR35 %SGPR36_SGPR37 %SGPR38_SGPR39 %SGPR40_SGPR41 %VGPR2 %VGPR3 %VGPR1 %VGPR0 %VGPR9_VGPR10_VGPR11_VGPR12 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR13 %VGPR4
    Predecessors according to CFG: BB#2 BB#8
	%VGPR14<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 28, %EXEC<imp-use>; mem:LD4[%scevgep11(addrspace=1)](tbaa=<badref>)
	%VGPR15<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 28, %EXEC<imp-use>; mem:LD4[%scevgep29(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR14<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 24, %EXEC<imp-use>; mem:LD4[%scevgep12(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 24, %EXEC<imp-use>; mem:LD4[%scevgep30(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 20, %EXEC<imp-use>; mem:LD4[%scevgep13(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 20, %EXEC<imp-use>; mem:LD4[%scevgep31(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 16, %EXEC<imp-use>; mem:LD4[%scevgep14(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 16, %EXEC<imp-use>; mem:LD4[%scevgep32(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 12, %EXEC<imp-use>; mem:LD4[%scevgep15(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 12, %EXEC<imp-use>; mem:LD4[%scevgep33(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 8, %EXEC<imp-use>; mem:LD4[%scevgep16(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 8, %EXEC<imp-use>; mem:LD4[%scevgep34(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 4, %EXEC<imp-use>; mem:LD4[%scevgep17(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 4, %EXEC<imp-use>; mem:LD4[%scevgep35(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR9_VGPR10, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv9(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR5_VGPR6, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv27(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR24, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR25, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep18(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR24, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR25, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep36(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR27<def> = S_MOV_B32 -1[TF=2], %SGPR26_SGPR27<imp-use,kill>, %SGPR26_SGPR27<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR26, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR27, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep19(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR26, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR27, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep37(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR29<def> = S_MOV_B32 -1[TF=2], %SGPR28_SGPR29<imp-use,kill>, %SGPR28_SGPR29<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR28, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR29, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep20(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR28, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR29, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep38(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR31<def> = S_MOV_B32 -1[TF=2], %SGPR30_SGPR31<imp-use,kill>, %SGPR30_SGPR31<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR30, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR31, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep21(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR30, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR31, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep39(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR33<def> = S_MOV_B32 -1[TF=2], %SGPR32_SGPR33<imp-use,kill>, %SGPR32_SGPR33<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR32, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR33, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep22(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR32, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR33, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep40(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR35<def> = S_MOV_B32 -1[TF=2], %SGPR34_SGPR35<imp-use,kill>, %SGPR34_SGPR35<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR34, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR35, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep23(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR34, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR35, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep41(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR37<def> = S_MOV_B32 -1[TF=2], %SGPR36_SGPR37<imp-use,kill>, %SGPR36_SGPR37<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR36, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR37, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep24(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR36, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR37, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep42(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%SGPR39<def> = S_MOV_B32 -1[TF=2], %SGPR38_SGPR39<imp-use,kill>, %SGPR38_SGPR39<imp-def>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR38, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR39, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_I32_e32 %VGPR9, %VGPR30, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR32_VGPR33<imp-def>
	%VGPR33<def> = V_ADDC_U32_e32 %VGPR10, %VGPR31, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR30<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR32_VGPR33<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep25(addrspace=1)](tbaa=<badref>)
	%VGPR31<def> = V_MOV_B32_e32 %SGPR38, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR39, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_I32_e32 %VGPR5, %VGPR31, %VCC<imp-def>, %EXEC<imp-use>, %VCC<imp-def>, %VGPR33_VGPR34<imp-def>
	%VGPR34<def> = V_ADDC_U32_e32 %VGPR6, %VGPR32, %VCC<imp-def,dead>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VCC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR31<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR20_SGPR21_SGPR22_SGPR23, %VGPR33_VGPR34<kill>, 0, %EXEC<imp-use>; mem:LD4[%scevgep43(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR30<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR30, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-def>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR14, %VGPR15, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR16, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR17, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR18, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR19, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR20, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR21, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR22, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR29, %VGPR30<kill>, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23_VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_I32_e32 %SGPR40, %VGPR5, %EXEC<imp-use>, %VCC<imp-def>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR41, %EXEC<imp-use>
	%VGPR6<def> = V_ADDC_U32_e32 %VGPR6, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-def>
	%VGPR9<def> = V_ADD_I32_e32 %SGPR40, %VGPR9, %EXEC<imp-use>, %VCC<imp-def>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR41, %EXEC<imp-use>
	%VGPR10<def> = V_ADDC_U32_e32 %VGPR10, %VGPR14<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR17, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_I32_e32 16, %VGPR13<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR42_SGPR43<def> = V_CMP_GE_I32_e64 %VGPR13, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = SI_IF_BREAK %SGPR42_SGPR43<kill>, %SGPR44_SGPR45, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-use,kill>, %SGPR44_SGPR45_SGPR46_SGPR47<imp-def>
	SI_LOOP %SGPR44_SGPR45, <BB#8>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#3>
    Successors according to CFG: BB#3(4) BB#8(124)

BB#9: derived from LLVM BB %Flow46
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#5 BB#11
	SI_END_CF %SGPR16_SGPR17<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#12>
    Successors according to CFG: BB#12

BB#10: derived from LLVM BB %for.body31
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %SGPR2_SGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15 %VGPR8_VGPR9 %VGPR10_VGPR11 %VGPR0
    Predecessors according to CFG: BB#6 BB#10
	%VGPR6<def> = V_ADD_I32_e32 %SGPR2, %VGPR8, %EXEC<imp-use>, %VCC<imp-def>, %VGPR6_VGPR7<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR7<def> = V_ADDC_U32_e32 %VGPR9, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR12<def> = V_ADD_I32_e32 %SGPR2, %VGPR10, %EXEC<imp-use>, %VCC<imp-def>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR13<def> = V_ADDC_U32_e32 %VGPR11, %VGPR1<kill>, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR1<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR10_VGPR11<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv1(addrspace=1)](tbaa=<badref>)
	%VGPR8<def> = BUFFER_LOAD_DWORD_ADDR64 %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR8_VGPR9<kill>, 0, %EXEC<imp-use>; mem:LD4[%lsr.iv4(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1904
	%VGPR1<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 -1, %VGPR0<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR18_SGPR19<def> = V_CMP_EQ_I32_e64 %VGPR0, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = SI_IF_BREAK %SGPR18_SGPR19<kill>, %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-def>
	%VGPR8<def> = V_MOV_B32_e32 %VGPR6<kill>, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_MOV_B32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %VGPR12<kill>, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_MOV_B32_e32 %VGPR13<kill>, %EXEC<imp-use>
	SI_LOOP %SGPR12_SGPR13, <BB#10>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#11>
    Successors according to CFG: BB#11(4) BB#10(124)

BB#11: derived from LLVM BB %Flow45
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %SGPR16_SGPR17 %VGPR2 %VGPR3 %VGPR4 %SGPR12_SGPR13_SGPR14_SGPR15
    Predecessors according to CFG: BB#10
	SI_END_CF %SGPR12_SGPR13, %EXEC<imp-def>, %EXEC<imp-use>, %SGPR12_SGPR13_SGPR14_SGPR15<imp-use,kill>
	S_BRANCH <BB#9>
    Successors according to CFG: BB#9

BB#12: derived from LLVM BB %for.end48
    Live Ins: %SGPR4_SGPR5 %SGPR6 %VGPR5 %SGPR0_SGPR1 %VGPR2 %VGPR3 %VGPR4
    Predecessors according to CFG: BB#9
	%VGPR0<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_LO_I32 %VGPR3<kill>, %VGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ASHRREV_I32_e32 31, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2_VGPR3<def> = V_LSHL_B64 %VGPR0_VGPR1<kill>, 2, %EXEC<imp-use>
	%VGPR0<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VCC<imp-def>, %VGPR0_VGPR1<imp-def>
	%VGPR1<def> = V_ADDC_U32_e32 %VGPR6<kill>, %VGPR3, %VCC<imp-use,kill>, %VCC<imp-def,dead>, %VGPR2_VGPR3<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.402823e+35, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%SGPR2_SGPR3<def> = SI_IF %SGPR2_SGPR3<kill>, <BB#13>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#15>
    Successors according to CFG: BB#15(16) BB#13(16)

BB#13: derived from LLVM BB %Flow
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12 BB#15
	%SGPR2_SGPR3<def,tied1> = SI_ELSE %SGPR2_SGPR3<kill,tied0>, <BB#16>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#14>
    Successors according to CFG: BB#14(16) BB#16(16)

BB#14: derived from LLVM BB %if.then51
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%VGPR2<def> = V_MOV_B32_e32 2055410286, %EXEC<imp-use>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1<kill>, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#16>
    Successors according to CFG: BB#16

BB#15: derived from LLVM BB %if.else
    Live Ins: %VGPR0_VGPR1 %SGPR0_SGPR1 %VGPR2 %SGPR2_SGPR3
    Predecessors according to CFG: BB#12
	%SGPR4_SGPR5<def> = S_MOV_B64 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR6<def> = S_MOV_B32 0, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	%SGPR7<def> = S_MOV_B32 61440, %SGPR4_SGPR5_SGPR6_SGPR7<imp-use,kill>, %SGPR4_SGPR5_SGPR6_SGPR7<imp-def>
	BUFFER_STORE_DWORD %VGPR2<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0_VGPR1, 0, %EXEC<imp-use>; mem:ST4[%arrayidx54(addrspace=1)](tbaa=<badref>)
	S_WAITCNT 1792
	S_BRANCH <BB#13>
    Successors according to CFG: BB#13

BB#16: derived from LLVM BB %Flow44
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3
    Predecessors according to CFG: BB#13 BB#14
	SI_END_CF %SGPR2_SGPR3<kill>, %EXEC<imp-def>, %EXEC<imp-use>
	S_BRANCH <BB#4>
    Successors according to CFG: BB#4

BB#17: derived from LLVM BB %if.end58
    Predecessors according to CFG: BB#4
	S_ENDPGM

# End machine code for function svm_rbf.

	.text
	;@svm_rbf:
	.section	.AMDGPU.config
.long	47176
.long	328
.long	47180
.long	0
	.text
; BB#0:                                 ; %entry
	V_MOV_B32_e32 v2, s2
	S_LOAD_DWORD s8, s[0:1], 6
	S_WAITCNT lgkmcnt(0)
	V_MUL_LO_I32 v2, s8, v2, 0, 0, 0, 0, 0
	V_ADD_I32_e32 v2, v2, v0
	S_LOAD_DWORD s4, s[0:1], 21
	S_WAITCNT lgkmcnt(0)
	V_MOV_B32_e32 v3, s4
	V_CMP_LT_I32_e64 s[4:5], v2, v3, 0, 0, 0, 0
	V_MOV_B32_e32 v3, s3
	S_LOAD_DWORD s14, s[0:1], 7
	S_WAITCNT lgkmcnt(0)
	V_MUL_LO_I32 v3, s14, v3, 0, 0, 0, 0, 0
	V_ADD_I32_e32 v3, v3, v1
	S_LOAD_DWORD s6, s[0:1], 20
	S_WAITCNT lgkmcnt(0)
	V_MOV_B32_e32 v4, s6
	V_CMP_LT_I32_e64 s[6:7], v3, v4, 0, 0, 0, 0
	S_AND_B64 s[18:19], s[6:7], s[4:5]
	S_LOAD_DWORD s16, s[0:1], 23
	S_LOAD_DWORD s7, s[0:1], 22
	S_LOAD_DWORD s6, s[0:1], 19
	S_LOAD_DWORDX2 s[4:5], s[0:1], 17
	S_LOAD_DWORD s9, s[0:1], 15
	S_LOAD_DWORDX2 s[10:11], s[0:1], 13
	S_LOAD_DWORD s15, s[0:1], 11
	S_LOAD_DWORDX2 s[12:13], s[0:1], 9
	S_WAITCNT lgkmcnt(0)
	S_AND_SAVEEXEC_B64 s[0:1], s[18:19]
	S_XOR_B64 s[0:1], exec, s[0:1]
	S_CBRANCH_EXECZ BB0_4
; BB#1:                                 ; %for.cond.preheader
	S_ADD_I32 s17, s7, -16
	V_CMP_GT_I32_e64 s[18:19], s17, 0, 0, 0, 0, 0
	V_MOV_B32_e32 v6, 0
	V_MOV_B32_e32 v4, 0.000000e+00
	S_AND_SAVEEXEC_B64 s[18:19], s[18:19]
	S_XOR_B64 s[18:19], exec, s[18:19]
	S_CBRANCH_EXECZ BB0_7
; BB#2:                                 ; %for.body.lr.ph
	V_MOV_B32_e32 v4, s3
	V_MUL_LO_I32 v4, s14, v4, 0, 0, 0, 0, 0
	V_ADD_I32_e32 v4, v4, v1
	V_MUL_LO_I32 v4, s15, v4, 0, 0, 0, 0, 0
	V_ASHRREV_I32_e32 v5, 31, v4
	V_LSHL_B64 v[4:5], v[4:5], 2
	V_MOV_B32_e32 v6, s12
	V_MOV_B32_e32 v7, s13
	V_ADD_I32_e32 v9, v6, v4
	V_ADDC_U32_e32 v10, v5, v7
	S_MOV_B64 s[20:21], 32
	V_ADD_I32_e32 v5, s20, v9
	V_MOV_B32_e32 v4, s21
	V_ADDC_U32_e32 v6, v10, v4
	V_MOV_B32_e32 v4, s2
	V_MUL_LO_I32 v4, s8, v4, 0, 0, 0, 0, 0
	V_ADD_I32_e32 v4, v4, v0
	V_MUL_LO_I32 v9, s9, v4, 0, 0, 0, 0, 0
	V_ASHRREV_I32_e32 v10, 31, v9
	V_LSHL_B64 v[9:10], v[9:10], 2
	V_MOV_B32_e32 v4, s10
	V_MOV_B32_e32 v11, s11
	V_ADD_I32_e32 v13, v4, v9
	V_ADDC_U32_e32 v14, v10, v11
	V_ADD_I32_e32 v9, s20, v13
	V_MOV_B32_e32 v4, s21
	V_ADDC_U32_e32 v10, v14, v4
	V_MOV_B32_e32 v4, 0.000000e+00
	V_MOV_B32_e32 v13, 0
	S_MOV_B64 s[20:21], 0
	S_MOV_B32 s22, 0
	S_MOV_B32 s23, 61440
	S_MOV_B32 s25, -1
	S_MOV_B32 s24, -4
	S_MOV_B32 s26, -8
	S_MOV_B32 s28, -12
	S_MOV_B32 s30, -16
	S_MOV_B32 s32, -20
	S_MOV_B32 s34, -24
	S_MOV_B32 s36, -28
	S_MOV_B32 s38, -32
	S_MOV_B64 s[40:41], 64
BB0_8:                                  ; %for.body
                                        ; =>This Inner Loop Header: Depth=1
	S_SETHALT
	BUFFER_LOAD_DWORD v14, s[20:23] + v[9:10] + 28
	S_SETHALT
	BUFFER_LOAD_DWORD v15, s[20:23] + v[5:6] + 28
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v14, v15, v14
	V_MUL_F32_e32 v29, v14, v14
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[9:10] + 24
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[5:6] + 24
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v28, v30, v30
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[9:10] + 20
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[5:6] + 20
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v27, v30, v30
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[9:10] + 16
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[5:6] + 16
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v26, v30, v30
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[9:10] + 12
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[5:6] + 12
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v25, v30, v30
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[9:10] + 8
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[5:6] + 8
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v24, v30, v30
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[9:10] + 4
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[5:6] + 4
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v23, v30, v30
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[9:10] + 0
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[5:6] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v22, v30, v30
	V_MOV_B32_e32 v30, s24
	V_MOV_B32_e32 v31, s25
	V_ADD_I32_e32 v32, v9, v30
	V_ADDC_U32_e32 v33, v10, v31
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[32:33] + 0
	V_MOV_B32_e32 v31, s24
	V_MOV_B32_e32 v32, s25
	V_ADD_I32_e32 v33, v5, v31
	V_ADDC_U32_e32 v34, v6, v32
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[33:34] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v21, v30, v30
	S_MOV_B32 s27, -1
	V_MOV_B32_e32 v30, s26
	V_MOV_B32_e32 v31, s27
	V_ADD_I32_e32 v32, v9, v30
	V_ADDC_U32_e32 v33, v10, v31
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[32:33] + 0
	V_MOV_B32_e32 v31, s26
	V_MOV_B32_e32 v32, s27
	V_ADD_I32_e32 v33, v5, v31
	V_ADDC_U32_e32 v34, v6, v32
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[33:34] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v20, v30, v30
	S_MOV_B32 s29, -1
	V_MOV_B32_e32 v30, s28
	V_MOV_B32_e32 v31, s29
	V_ADD_I32_e32 v32, v9, v30
	V_ADDC_U32_e32 v33, v10, v31
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[32:33] + 0
	V_MOV_B32_e32 v31, s28
	V_MOV_B32_e32 v32, s29
	V_ADD_I32_e32 v33, v5, v31
	V_ADDC_U32_e32 v34, v6, v32
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[33:34] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v19, v30, v30
	S_MOV_B32 s31, -1
	V_MOV_B32_e32 v30, s30
	V_MOV_B32_e32 v31, s31
	V_ADD_I32_e32 v32, v9, v30
	V_ADDC_U32_e32 v33, v10, v31
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[32:33] + 0
	V_MOV_B32_e32 v31, s30
	V_MOV_B32_e32 v32, s31
	V_ADD_I32_e32 v33, v5, v31
	V_ADDC_U32_e32 v34, v6, v32
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[33:34] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v18, v30, v30
	S_MOV_B32 s33, -1
	V_MOV_B32_e32 v30, s32
	V_MOV_B32_e32 v31, s33
	V_ADD_I32_e32 v32, v9, v30
	V_ADDC_U32_e32 v33, v10, v31
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[32:33] + 0
	V_MOV_B32_e32 v31, s32
	V_MOV_B32_e32 v32, s33
	V_ADD_I32_e32 v33, v5, v31
	V_ADDC_U32_e32 v34, v6, v32
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[33:34] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v17, v30, v30
	S_MOV_B32 s35, -1
	V_MOV_B32_e32 v30, s34
	V_MOV_B32_e32 v31, s35
	V_ADD_I32_e32 v32, v9, v30
	V_ADDC_U32_e32 v33, v10, v31
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[32:33] + 0
	V_MOV_B32_e32 v31, s34
	V_MOV_B32_e32 v32, s35
	V_ADD_I32_e32 v33, v5, v31
	V_ADDC_U32_e32 v34, v6, v32
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[33:34] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v16, v30, v30
	S_MOV_B32 s37, -1
	V_MOV_B32_e32 v30, s36
	V_MOV_B32_e32 v31, s37
	V_ADD_I32_e32 v32, v9, v30
	V_ADDC_U32_e32 v33, v10, v31
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[32:33] + 0
	V_MOV_B32_e32 v31, s36
	V_MOV_B32_e32 v32, s37
	V_ADD_I32_e32 v33, v5, v31
	V_ADDC_U32_e32 v34, v6, v32
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[33:34] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v15, v30, v30
	S_MOV_B32 s39, -1
	V_MOV_B32_e32 v30, s38
	V_MOV_B32_e32 v31, s39
	V_ADD_I32_e32 v32, v9, v30
	V_ADDC_U32_e32 v33, v10, v31
	S_SETHALT
	BUFFER_LOAD_DWORD v30, s[20:23] + v[32:33] + 0
	V_MOV_B32_e32 v31, s38
	V_MOV_B32_e32 v32, s39
	V_ADD_I32_e32 v33, v5, v31
	V_ADDC_U32_e32 v34, v6, v32
	S_SETHALT
	BUFFER_LOAD_DWORD v31, s[20:23] + v[33:34] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v30, v31, v30
	V_MUL_F32_e32 v14, v30, v30
	V_ADD_F32_e32 v30, v14, v15
	V_ADD_F32_e32 v30, v16, v30
	V_ADD_F32_e32 v30, v17, v30
	V_ADD_F32_e32 v30, v18, v30
	V_ADD_F32_e32 v30, v19, v30
	V_ADD_F32_e32 v30, v20, v30
	V_ADD_F32_e32 v30, v21, v30
	V_ADD_F32_e32 v30, v22, v30
	V_ADD_F32_e32 v30, v23, v30
	V_ADD_F32_e32 v30, v24, v30
	V_ADD_F32_e32 v30, v25, v30
	V_ADD_F32_e32 v30, v26, v30
	V_ADD_F32_e32 v30, v27, v30
	V_ADD_F32_e32 v30, v28, v30
	V_ADD_F32_e32 v14, v29, v30
	V_ADD_F32_e32 v4, v4, v14
	V_ADD_I32_e32 v5, s40, v5
	V_MOV_B32_e32 v14, s41
	V_ADDC_U32_e32 v6, v6, v14
	V_ADD_I32_e32 v9, s40, v9
	V_MOV_B32_e32 v14, s41
	V_ADDC_U32_e32 v10, v10, v14
	V_MOV_B32_e32 v14, s17
	V_ADD_I32_e32 v13, 16, v13
	V_CMP_GE_I32_e64 s[42:43], v13, v14, 0, 0, 0, 0
	S_OR_B64 s[44:45], s[42:43], s[44:45]
	S_ANDN2_B64 exec, exec, s[44:45]
	S_CBRANCH_EXECNZ BB0_8
; BB#3:                                 ; %for.cond.for.cond29.preheader_crit_edge
	S_OR_B64 exec, exec, s[44:45]
	S_ADD_I32 s17, s7, -1
	S_AND_B32 s17, s17, -16
	V_MOV_B32_e32 v6, s17
BB0_7:                                  ; %Flow47
	S_OR_B64 exec, exec, s[18:19]
	V_MOV_B32_e32 v5, s16
; BB#5:                                 ; %for.cond29.preheader
	V_MOV_B32_e32 v8, s7
	V_CMP_LT_I32_e64 s[16:17], v6, v8, 0, 0, 0, 0
	S_AND_SAVEEXEC_B64 s[16:17], s[16:17]
	S_XOR_B64 s[16:17], exec, s[16:17]
	S_CBRANCH_EXECZ BB0_9
; BB#6:                                 ; %for.body31.lr.ph
	V_MOV_B32_e32 v8, s3
	V_MUL_LO_I32 v8, s14, v8, 0, 0, 0, 0, 0
	V_ADD_I32_e32 v1, v8, v1
	V_MUL_LO_I32 v8, s15, v1, 0, 0, 0, 0, 0
	V_ASHRREV_I32_e32 v9, 31, v8
	V_ASHRREV_I32_e32 v7, 31, v6
	V_ADD_I32_e32 v10, v8, v6
	V_ADDC_U32_e32 v11, v7, v9
	V_LSHL_B64 v[10:11], v[10:11], 2
	V_MOV_B32_e32 v1, s12
	V_MOV_B32_e32 v12, s13
	V_ADD_I32_e32 v8, v1, v10
	V_ADDC_U32_e32 v9, v12, v11
	V_MOV_B32_e32 v1, s2
	V_MUL_LO_I32 v1, s8, v1, 0, 0, 0, 0, 0
	V_ADD_I32_e32 v0, v1, v0
	V_MUL_LO_I32 v0, s9, v0, 0, 0, 0, 0, 0
	V_ASHRREV_I32_e32 v1, 31, v0
	V_ADD_I32_e32 v10, v0, v6
	V_ADDC_U32_e32 v11, v7, v1
	V_LSHL_B64 v[0:1], v[10:11], 2
	V_MOV_B32_e32 v10, s10
	V_MOV_B32_e32 v12, s11
	V_ADD_I32_e32 v10, v10, v0
	V_ADDC_U32_e32 v11, v12, v1
	V_SUB_I32_e32 v0, s7, v6
	S_MOV_B64 s[8:9], 0
	S_MOV_B64 s[2:3], 4
	S_MOV_B32 s10, 0
	S_MOV_B32 s11, 61440
BB0_10:                                 ; %for.body31
                                        ; =>This Inner Loop Header: Depth=1
	V_ADD_I32_e32 v6, s2, v8
	V_MOV_B32_e32 v1, s3
	V_ADDC_U32_e32 v7, v9, v1
	V_ADD_I32_e32 v12, s2, v10
	V_MOV_B32_e32 v1, s3
	V_ADDC_U32_e32 v13, v11, v1
	S_SETHALT
	BUFFER_LOAD_DWORD v1, s[8:11] + v[10:11] + 0
	S_SETHALT
	BUFFER_LOAD_DWORD v8, s[8:11] + v[8:9] + 0
	S_WAITCNT vmcnt(0) 
	V_SUB_F32_e32 v1, v8, v1
	V_MAD_F32 v4, v1, v1, v4, 0, 0, 0, 0
	V_ADD_I32_e32 v0, -1, v0
	V_CMP_EQ_I32_e64 s[18:19], v0, 0, 0, 0, 0, 0
	S_OR_B64 s[12:13], s[18:19], s[12:13]
	V_MOV_B32_e32 v8, v6
	V_MOV_B32_e32 v9, v7
	V_MOV_B32_e32 v10, v12
	V_MOV_B32_e32 v11, v13
	S_ANDN2_B64 exec, exec, s[12:13]
	S_CBRANCH_EXECNZ BB0_10
; BB#11:                                ; %Flow45
	S_OR_B64 exec, exec, s[12:13]
BB0_9:                                  ; %Flow46
	S_OR_B64 exec, exec, s[16:17]
; BB#12:                                ; %for.end48
	V_MOV_B32_e32 v0, s6
	V_MUL_LO_I32 v0, v3, v0, 0, 0, 0, 0, 0
	V_ADD_I32_e32 v0, v0, v2
	V_ASHRREV_I32_e32 v1, 31, v0
	V_LSHL_B64 v[2:3], v[0:1], 2
	V_MOV_B32_e32 v0, s4
	V_MOV_B32_e32 v6, s5
	V_ADD_I32_e32 v0, v0, v2
	V_ADDC_U32_e32 v1, v6, v3
	V_MUL_F32_e64 v2, v4, v5, 0, 0, 0, 0
	V_MOV_B32_e32 v3, 3.402823e+35
	V_CMP_LE_F32_e64 s[2:3], v2, v3, 0, 0, 0, 0
	V_CMP_U_F32_e64 s[4:5], v2, v2, 0, 0, 0, 0
	S_OR_B64 s[2:3], s[2:3], s[4:5]
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]
	S_XOR_B64 s[2:3], exec, s[2:3]
; BB#15:                                ; %if.else
	S_MOV_B64 s[4:5], 0
	S_MOV_B32 s6, 0
	S_MOV_B32 s7, 61440
	S_SETHALT
	BUFFER_STORE_DWORD v2, s[4:7] + v[0:1] + 0
	S_WAITCNT vmcnt(0) expcnt(0) 
BB0_13:                                 ; %Flow
	S_OR_SAVEEXEC_B64 s[2:3], s[2:3]
	S_XOR_B64 exec, exec, s[2:3]
; BB#14:                                ; %if.then51
	S_MOV_B64 s[4:5], 0
	S_MOV_B32 s6, 0
	S_MOV_B32 s7, 61440
	V_MOV_B32_e32 v2, 2055410286
	S_SETHALT
	BUFFER_STORE_DWORD v2, s[4:7] + v[0:1] + 0
	S_WAITCNT vmcnt(0) expcnt(0) 
BB0_16:                                 ; %Flow44
	S_OR_B64 exec, exec, s[2:3]
BB0_4:                                  ; %Flow48
	S_OR_B64 exec, exec, s[0:1]
; BB#17:                                ; %if.end58
	S_ENDPGM

	.section	.AMDGPU.csdata
; Kernel info:
; NumSgprs: 47
; NumVgprs: 34